Instance: DIB
Component: DIB
Base address: 0xE000EFB0
|
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
|
32 |
0x0000 0000 |
0x0000 0000 |
0xE000 EFB0 |
||
|
32 |
0x4770 2A04 |
0x0000 0004 |
0xE000 EFB4 |
||
|
32 |
0x4770 2A04 |
0x0000 0008 |
0xE000 EFB8 |
||
|
32 |
0x4770 2A04 |
0x0000 000C |
0xE000 EFBC |
||
|
32 |
0x0000 0000 |
0x0000 001C |
0xE000 EFCC |
||
|
32 |
0x0000 0004 |
0x0000 0020 |
0xE000 EFD0 |
||
|
32 |
0x0000 0000 |
0x0000 0024 |
0xE000 EFD4 |
||
|
32 |
0x0000 0000 |
0x0000 0028 |
0xE000 EFD8 |
||
|
32 |
0x0000 0000 |
0x0000 002C |
0xE000 EFDC |
||
|
32 |
0x0000 0021 |
0x0000 0030 |
0xE000 EFE0 |
||
|
32 |
0x0000 00BD |
0x0000 0034 |
0xE000 EFE4 |
||
|
32 |
0x0000 000B |
0x0000 0038 |
0xE000 EFE8 |
||
|
32 |
0x0000 0000 |
0x0000 003C |
0xE000 EFEC |
||
|
32 |
0x0000 000D |
0x0000 0040 |
0xE000 EFF0 |
||
|
32 |
0x0000 0090 |
0x0000 0044 |
0xE000 EFF4 |
||
|
32 |
0x0000 0005 |
0x0000 0048 |
0xE000 EFF8 |
||
|
32 |
0x0000 00B1 |
0x0000 004C |
0xE000 EFFC |
| Address Offset | 0x0000 0000 | ||
| Physical Address | 0xE000 EFB0 | Instance | 0xE000 EFB0 |
| Description | Provides CoreSight discovery information for the SCS | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
| 0 | KEY | Indicates whether Non-secure invasive debug is allowed | RO | 0 | ||
| Address Offset | 0x0000 0004 | ||
| Physical Address | 0xE000 EFB4 | Instance | 0xE000 EFB4 |
| Description | Provides CoreSight discovery information for the SCS | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:3 | RESERVED4 | Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code. | RO | 0b0 1000 1110 1110 0000 0101 0100 0000 | ||
| 2 | nTT | Indicates whether Secure invasive debug is implemented and allowed | RO | 1 | ||
| 1 | SLK | Indicates whether Non-secure non-invasive debug is allowed | RO | 0 | ||
| 0 | SLI | Indicates whether Non-secure invasive debug is allowed | RO | 0 | ||
| Address Offset | 0x0000 0008 | ||
| Physical Address | 0xE000 EFB8 | Instance | 0xE000 EFB8 |
| Description | Provides CoreSight discovery information for the SCS | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:4 | RESERVED4 | Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code. | RO | 0x477 02A0 | ||
| 3 | SNID | Indicates whether Secure non-invasive debug is implemented and allowed | RO | 0 | ||
| 2 | SID | Indicates whether Secure invasive debug is implemented and allowed | RO | 1 | ||
| 1 | NSNID | Indicates whether Non-secure non-invasive debug is allowed | RO | 0 | ||
| 0 | NSID | Indicates whether Non-secure invasive debug is allowed | RO | 0 | ||
| Address Offset | 0x0000 000C | ||
| Physical Address | 0xE000 EFBC | Instance | 0xE000 EFBC |
| Description | Provides CoreSight discovery information for the SCS | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:21 | ARCHITECT | Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code. | RO | 0b010 0011 1011 | ||
| 20 | PRESENT | Defines that the DEVARCH register is present | RO | 1 | ||
| 19:16 | REVISION | Defines the architecture revision of the component | RO | 0x0 | ||
| 15:12 | ARCHVER | Defines the architecture version of the component | RO | 0x2 | ||
| 11:0 | ARCHPART | Defines the architecture of the component | RO | 0xA04 | ||
| Address Offset | 0x0000 001C | ||
| Physical Address | 0xE000 EFCC | Instance | 0xE000 EFCC |
| Description | Provides CoreSight discovery information for the SCS | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RES0 | Reserved, RES0 | RO | 0x00 0000 | ||
| 7:4 | SUB | Component sub-type | RO | 0x0 | ||
| 3:0 | MAJOR | CoreSight major type | RO | 0x0 | ||
| Address Offset | 0x0000 0020 | ||
| Physical Address | 0xE000 EFD0 | Instance | 0xE000 EFD0 |
| Description | Provides CoreSight discovery information for the SCS | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RES0 | Reserved, RES0 | RO | 0x00 0000 | ||
| 7:4 | SIZE | See CoreSight Architecture Specification | RO | 0x0 | ||
| 3:0 | DES_2 | See CoreSight Architecture Specification | RO | 0x4 | ||
| Address Offset | 0x0000 0024 | ||
| Physical Address | 0xE000 EFD4 | Instance | 0xE000 EFD4 |
| Description | Provides CoreSight discovery information for the SCS | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | RES0 | Reserved, RES0 | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0028 | ||
| Physical Address | 0xE000 EFD8 | Instance | 0xE000 EFD8 |
| Description | Provides CoreSight discovery information for the SCS | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | RES0 | Reserved, RES0 | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 002C | ||
| Physical Address | 0xE000 EFDC | Instance | 0xE000 EFDC |
| Description | Provides CoreSight discovery information for the SCS | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | RES0 | Reserved, RES0 | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0030 | ||
| Physical Address | 0xE000 EFE0 | Instance | 0xE000 EFE0 |
| Description | Provides CoreSight discovery information for the SCS | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RES0 | Reserved, RES0 | RO | 0x00 0000 | ||
| 7:0 | PART_0 | See CoreSight Architecture Specification | RO | 0x21 | ||
| Address Offset | 0x0000 0034 | ||
| Physical Address | 0xE000 EFE4 | Instance | 0xE000 EFE4 |
| Description | Provides CoreSight discovery information for the SCS | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RES0 | Reserved, RES0 | RO | 0x00 0000 | ||
| 7:4 | DES_0 | See CoreSight Architecture Specification | RO | 0xB | ||
| 3:0 | PART_1 | See CoreSight Architecture Specification | RO | 0xD | ||
| Address Offset | 0x0000 0038 | ||
| Physical Address | 0xE000 EFE8 | Instance | 0xE000 EFE8 |
| Description | Provides CoreSight discovery information for the SCS | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RES0 | Reserved, RES0 | RO | 0x00 0000 | ||
| 7:4 | REVISION | See CoreSight Architecture Specification | RO | 0x0 | ||
| 3 | JEDEC | See CoreSight Architecture Specification | RO | 1 | ||
| 2:0 | DES_1 | See CoreSight Architecture Specification | RO | 0b011 | ||
| Address Offset | 0x0000 003C | ||
| Physical Address | 0xE000 EFEC | Instance | 0xE000 EFEC |
| Description | Provides CoreSight discovery information for the SCS | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RES0 | Reserved, RES0 | RO | 0x00 0000 | ||
| 7:4 | REVAND | See CoreSight Architecture Specification | RO | 0x0 | ||
| 3:0 | CMOD | See CoreSight Architecture Specification | RO | 0x0 | ||
| Address Offset | 0x0000 0040 | ||
| Physical Address | 0xE000 EFF0 | Instance | 0xE000 EFF0 |
| Description | Provides CoreSight discovery information for the SCS | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RES0 | Reserved, RES0 | RO | 0x00 0000 | ||
| 7:0 | PRMBL_0 | See CoreSight Architecture Specification | RO | 0x0D | ||
| Address Offset | 0x0000 0044 | ||
| Physical Address | 0xE000 EFF4 | Instance | 0xE000 EFF4 |
| Description | Provides CoreSight discovery information for the SCS | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RES0 | Reserved, RES0 | RO | 0x00 0000 | ||
| 7:4 | CLASS | See CoreSight Architecture Specification | RO | 0x9 | ||
| 3:0 | PRMBL_1 | See CoreSight Architecture Specification | RO | 0x0 | ||
| Address Offset | 0x0000 0048 | ||
| Physical Address | 0xE000 EFF8 | Instance | 0xE000 EFF8 |
| Description | Provides CoreSight discovery information for the SCS | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RES0 | Reserved, RES0 | RO | 0x00 0000 | ||
| 7:0 | PRMBL_2 | See CoreSight Architecture Specification | RO | 0x05 | ||
| Address Offset | 0x0000 004C | ||
| Physical Address | 0xE000 EFFC | Instance | 0xE000 EFFC |
| Description | Provides CoreSight discovery information for the SCS | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RES0 | Reserved, RES0 | RO | 0x00 0000 | ||
| 7:0 | PRMBL_3 | See CoreSight Architecture Specification | RO | 0xB1 | ||
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