This component is the clock controller. Here SW can turn on and off IP clocks and read IP and system clock status.
Bits |
Field Name |
Description |
Type |
Reset |
31
|
RESERVED31 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
30
|
LGPT3 |
IP status on device
Value |
ENUM Name |
Description |
0x0 |
IP_UNAVAIL |
IP is unavailable |
0x1 |
IP_AVAIL |
IP is available |
|
RO |
1 |
29
|
LGPT2 |
IP status on device
Value |
ENUM Name |
Description |
0x0 |
IP_UNAVAIL |
IP is unavailable |
0x1 |
IP_AVAIL |
IP is available |
|
RO |
1 |
28
|
LGPT1 |
IP status on device
Value |
ENUM Name |
Description |
0x0 |
IP_UNAVAIL |
IP is unavailable |
0x1 |
IP_AVAIL |
IP is available |
|
RO |
1 |
27
|
LGPT0 |
IP status on device
Value |
ENUM Name |
Description |
0x0 |
IP_UNAVAIL |
IP is unavailable |
0x1 |
IP_AVAIL |
IP is available |
|
RO |
1 |
26:21
|
RESERVED21 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 0000 |
20
|
I2S |
IP status on device
Value |
ENUM Name |
Description |
0x0 |
IP_UNAVAIL |
IP is unavailable |
0x1 |
IP_AVAIL |
IP is available |
|
RO |
1 |
19:18
|
RESERVED18 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 |
17
|
DMA |
IP status on device
Value |
ENUM Name |
Description |
0x0 |
IP_UNAVAIL |
IP is unavailable |
0x1 |
IP_AVAIL |
IP is available |
|
RO |
1 |
16
|
LAES |
IP status on device
Value |
ENUM Name |
Description |
0x0 |
IP_UNAVAIL |
IP is unavailable |
0x1 |
IP_AVAIL |
IP is available |
|
RO |
1 |
15
|
RESERVED15 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
14
|
ADC0 |
IP status on device
Value |
ENUM Name |
Description |
0x0 |
IP_UNAVAIL |
IP is unavailable |
0x1 |
IP_AVAIL |
IP is available |
|
RO |
1 |
13:12
|
RESERVED12 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 |
11
|
SPI1 |
IP status on device
Value |
ENUM Name |
Description |
0x0 |
IP_UNAVAIL |
IP is unavailable |
0x1 |
IP_AVAIL |
IP is available |
|
RO |
1 |
10
|
SPI0 |
IP status on device
Value |
ENUM Name |
Description |
0x0 |
IP_UNAVAIL |
IP is unavailable |
0x1 |
IP_AVAIL |
IP is available |
|
RO |
1 |
9:7
|
RESERVED7 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b000 |
6
|
I2C0 |
IP status on device
Value |
ENUM Name |
Description |
0x0 |
IP_UNAVAIL |
IP is unavailable |
0x1 |
IP_AVAIL |
IP is available |
|
RO |
1 |
5:4
|
RESERVED4 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 |
3
|
UART1 |
IP status on device
Value |
ENUM Name |
Description |
0x0 |
IP_UNAVAIL |
IP is unavailable |
0x1 |
IP_AVAIL |
IP is available |
|
RO |
1 |
2
|
UART0 |
IP status on device
Value |
ENUM Name |
Description |
0x0 |
IP_UNAVAIL |
IP is unavailable |
0x1 |
IP_AVAIL |
IP is available |
|
RO |
1 |
1
|
LRFD |
IP status on device
Value |
ENUM Name |
Description |
0x0 |
IP_UNAVAIL |
IP is unavailable |
0x1 |
IP_AVAIL |
IP is available |
|
RO |
1 |
0
|
GPIO |
IP status on device
Value |
ENUM Name |
Description |
0x0 |
IP_UNAVAIL |
IP is unavailable |
0x1 |
IP_AVAIL |
IP is available |
|
RO |
1 |
Bits |
Field Name |
Description |
Type |
Reset |
31:30
|
FLASHSZ |
System flash availability
Value |
ENUM Name |
Description |
0x0 |
SZ0 |
Flash size set to level 0 (Min size) |
0x1 |
SZ1 |
Flash size set to level 1 |
0x2 |
SZ2 |
Flash size set to level 2 |
0x3 |
SZ3 |
Flash size set to level 3 (Max size) |
|
RO |
0b11 |
29:28
|
SRAMSZ |
System SRAM availability
Value |
ENUM Name |
Description |
0x0 |
SZ0 |
SRAM size set to level 0 (Min size) |
0x1 |
SZ1 |
SRAM size set to level 1 |
0x2 |
SZ2 |
SRAM size set to level 2 |
0x3 |
SZ3 |
SRAM size set to level 3 (Max size) |
|
RO |
0b11 |
27:19
|
RESERVED19 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b0 0000 0000 |
18:17
|
CANOPT |
CAN IP feature availability
Value |
ENUM Name |
Description |
0x3 |
MAX |
All features available |
|
RO |
0b11 |
16
|
RESERVED16 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
15:8
|
ROPT |
System radio feature availability
Value |
ENUM Name |
Description |
0xFF |
MAX |
All features available |
|
RO |
0xFF |
7
|
RESERVED7 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
6
|
MCAN |
IP status on device
Value |
ENUM Name |
Description |
0x0 |
IP_UNAVAIL |
IP is unavailable |
0x1 |
IP_AVAIL |
IP is available |
|
RO |
1 |
5
|
VCE |
IP status on device
Value |
ENUM Name |
Description |
0x0 |
IP_UNAVAIL |
IP is unavailable |
0x1 |
IP_AVAIL |
IP is available |
|
RO |
1 |
4
|
HSM |
IP status on device
Value |
ENUM Name |
Description |
0x0 |
IP_UNAVAIL |
IP is unavailable |
0x1 |
IP_AVAIL |
IP is available |
|
RO |
1 |
3:0
|
RESERVED0 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0x0 |
Bits |
Field Name |
Description |
Type |
Reset |
31
|
RESERVED31 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
30
|
LGPT3 |
IP clock configuration
Value |
ENUM Name |
Description |
0x0 |
CLK_DIS |
Clock is disabled |
0x1 |
CLK_EN |
Clock is enabled |
|
RO |
0 |
29
|
LGPT2 |
IP clock configuration
Value |
ENUM Name |
Description |
0x0 |
CLK_DIS |
Clock is disabled |
0x1 |
CLK_EN |
Clock is enabled |
|
RO |
0 |
28
|
LGPT1 |
IP clock configuration
Value |
ENUM Name |
Description |
0x0 |
CLK_DIS |
Clock is disabled |
0x1 |
CLK_EN |
Clock is enabled |
|
RO |
0 |
27
|
LGPT0 |
IP clock configuration
Value |
ENUM Name |
Description |
0x0 |
CLK_DIS |
Clock is disabled |
0x1 |
CLK_EN |
Clock is enabled |
|
RO |
0 |
26:21
|
RESERVED21 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 0000 |
20
|
I2S |
IP clock configuration
Value |
ENUM Name |
Description |
0x0 |
CLK_DIS |
Clock is disabled |
0x1 |
CLK_EN |
Clock is enabled |
|
RO |
0 |
19:18
|
RESERVED18 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 |
17
|
DMA |
IP clock configuration
Value |
ENUM Name |
Description |
0x0 |
CLK_DIS |
Clock is disabled |
0x1 |
CLK_EN |
Clock is enabled |
|
RO |
0 |
16
|
LAES |
IP clock configuration
Value |
ENUM Name |
Description |
0x0 |
CLK_DIS |
Clock is disabled |
0x1 |
CLK_EN |
Clock is enabled |
|
RO |
0 |
15
|
RESERVED15 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
14
|
ADC0 |
IP clock configuration
Value |
ENUM Name |
Description |
0x0 |
CLK_DIS |
Clock is disabled |
0x1 |
CLK_EN |
Clock is enabled |
|
RO |
0 |
13:12
|
RESERVED12 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 |
11
|
SPI1 |
IP clock configuration
Value |
ENUM Name |
Description |
0x0 |
CLK_DIS |
Clock is disabled |
0x1 |
CLK_EN |
Clock is enabled |
|
RO |
0 |
10
|
SPI0 |
IP clock configuration
Value |
ENUM Name |
Description |
0x0 |
CLK_DIS |
Clock is disabled |
0x1 |
CLK_EN |
Clock is enabled |
|
RO |
0 |
9:7
|
RESERVED7 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b000 |
6
|
I2C0 |
IP clock configuration
Value |
ENUM Name |
Description |
0x0 |
CLK_DIS |
Clock is disabled |
0x1 |
CLK_EN |
Clock is enabled |
|
RO |
0 |
5:4
|
RESERVED4 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 |
3
|
UART1 |
IP clock configuration
Value |
ENUM Name |
Description |
0x0 |
CLK_DIS |
Clock is disabled |
0x1 |
CLK_EN |
Clock is enabled |
|
RO |
0 |
2
|
UART0 |
IP clock configuration
Value |
ENUM Name |
Description |
0x0 |
CLK_DIS |
Clock is disabled |
0x1 |
CLK_EN |
Clock is enabled |
|
RO |
0 |
1
|
LRFD |
IP clock configuration
Value |
ENUM Name |
Description |
0x0 |
CLK_DIS |
Clock is disabled |
0x1 |
CLK_EN |
Clock is enabled |
|
RO |
0 |
0
|
GPIO |
IP clock configuration
Value |
ENUM Name |
Description |
0x0 |
CLK_DIS |
Clock is disabled |
0x1 |
CLK_EN |
Clock is enabled |
|
RO |
1 |
Bits |
Field Name |
Description |
Type |
Reset |
31
|
RESERVED31 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
30
|
LGPT3 |
Configure IP clock enable
Value |
ENUM Name |
Description |
0x0 |
CLK_UNCHGD |
IP clock enable is unchanged |
0x1 |
CLK_SET |
Set IP clock enable |
|
WO |
0 |
29
|
LGPT2 |
Configure IP clock enable
Value |
ENUM Name |
Description |
0x0 |
CLK_UNCHGD |
IP clock enable is unchanged |
0x1 |
CLK_SET |
Set IP clock enable |
|
WO |
0 |
28
|
LGPT1 |
Configure IP clock enable
Value |
ENUM Name |
Description |
0x0 |
CLK_UNCHGD |
IP clock enable is unchanged |
0x1 |
CLK_SET |
Set IP clock enable |
|
WO |
0 |
27
|
LGPT0 |
Configure IP clock enable
Value |
ENUM Name |
Description |
0x0 |
CLK_UNCHGD |
IP clock enable is unchanged |
0x1 |
CLK_SET |
Set IP clock enable |
|
WO |
0 |
26:21
|
RESERVED21 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 0000 |
20
|
I2S |
Configure IP clock enable
Value |
ENUM Name |
Description |
0x0 |
CLK_UNCHGD |
IP clock enable is unchanged |
0x1 |
CLK_SET |
Set IP clock enable |
|
WO |
0 |
19:18
|
RESERVED18 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 |
17
|
DMA |
Configure IP clock enable
Value |
ENUM Name |
Description |
0x0 |
CLK_UNCHGD |
IP clock enable is unchanged |
0x1 |
CLK_SET |
Set IP clock enable |
|
WO |
0 |
16
|
LAES |
Configure IP clock enable
Value |
ENUM Name |
Description |
0x0 |
CLK_UNCHGD |
IP clock enable is unchanged |
0x1 |
CLK_SET |
Set IP clock enable |
|
WO |
0 |
15
|
RESERVED15 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
14
|
ADC0 |
Configure IP clock enable
Value |
ENUM Name |
Description |
0x0 |
CLK_UNCHGD |
IP clock enable is unchanged |
0x1 |
CLK_SET |
Set IP clock enable |
|
WO |
0 |
13:12
|
RESERVED12 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 |
11
|
SPI1 |
Configure IP clock enable
Value |
ENUM Name |
Description |
0x0 |
CLK_UNCHGD |
IP clock enable is unchanged |
0x1 |
CLK_SET |
Set IP clock enable |
|
WO |
0 |
10
|
SPI0 |
Configure IP clock enable
Value |
ENUM Name |
Description |
0x0 |
CLK_UNCHGD |
IP clock enable is unchanged |
0x1 |
CLK_SET |
Set IP clock enable |
|
WO |
0 |
9:7
|
RESERVED7 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b000 |
6
|
I2C0 |
Configure IP clock enable
Value |
ENUM Name |
Description |
0x0 |
CLK_UNCHGD |
IP clock enable is unchanged |
0x1 |
CLK_SET |
Set IP clock enable |
|
WO |
0 |
5:4
|
RESERVED4 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 |
3
|
UART1 |
Configure IP clock enable
Value |
ENUM Name |
Description |
0x0 |
CLK_UNCHGD |
IP clock enable is unchanged |
0x1 |
CLK_SET |
Set IP clock enable |
|
WO |
0 |
2
|
UART0 |
Configure IP clock enable
Value |
ENUM Name |
Description |
0x0 |
CLK_UNCHGD |
IP clock enable is unchanged |
0x1 |
CLK_SET |
Set IP clock enable |
|
WO |
0 |
1
|
LRFD |
Configure IP clock enable
Value |
ENUM Name |
Description |
0x0 |
CLK_UNCHGD |
IP clock enable is unchanged |
0x1 |
CLK_SET |
Set IP clock enable |
|
WO |
0 |
0
|
GPIO |
Configure IP clock enable
Value |
ENUM Name |
Description |
0x0 |
CLK_UNCHGD |
IP clock enable is unchanged |
0x1 |
CLK_SET |
Set IP clock enable |
|
WO |
0 |
Bits |
Field Name |
Description |
Type |
Reset |
31
|
RESERVED31 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
30
|
LGPT3 |
Configure IP clock enable
Value |
ENUM Name |
Description |
0x0 |
CLK_UNCHGD |
IP clock enable is unchanged |
0x1 |
CLK_CLR |
Clear IP clock enable |
|
WO |
0 |
29
|
LGPT2 |
Configure IP clock enable
Value |
ENUM Name |
Description |
0x0 |
CLK_UNCHGD |
IP clock enable is unchanged |
0x1 |
CLK_CLR |
Clear IP clock enable |
|
WO |
0 |
28
|
LGPT1 |
Configure IP clock enable
Value |
ENUM Name |
Description |
0x0 |
CLK_UNCHGD |
IP clock enable is unchanged |
0x1 |
CLK_CLR |
Clear IP clock enable |
|
WO |
0 |
27
|
LGPT0 |
Configure IP clock enable
Value |
ENUM Name |
Description |
0x0 |
CLK_UNCHGD |
IP clock enable is unchanged |
0x1 |
CLK_CLR |
Clear IP clock enable |
|
WO |
0 |
26:21
|
RESERVED21 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 0000 |
20
|
I2S |
Configure IP clock enable
Value |
ENUM Name |
Description |
0x0 |
CLK_UNCHGD |
IP clock enable is unchanged |
0x1 |
CLK_CLR |
Clear IP clock enable |
|
WO |
0 |
19:18
|
RESERVED18 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 |
17
|
DMA |
Configure IP clock enable
Value |
ENUM Name |
Description |
0x0 |
CLK_UNCHGD |
IP clock enable is unchanged |
0x1 |
CLK_CLR |
Clear IP clock enable |
|
WO |
0 |
16
|
LAES |
Configure IP clock enable
Value |
ENUM Name |
Description |
0x0 |
CLK_UNCHGD |
IP clock enable is unchanged |
0x1 |
CLK_CLR |
Clear IP clock enable |
|
WO |
0 |
15
|
RESERVED15 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
14
|
ADC0 |
Configure IP clock enable
Value |
ENUM Name |
Description |
0x0 |
CLK_UNCHGD |
IP clock enable is unchanged |
0x1 |
CLK_CLR |
Clear IP clock enable |
|
WO |
0 |
13:12
|
RESERVED12 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 |
11
|
SPI1 |
Configure IP clock enable
Value |
ENUM Name |
Description |
0x0 |
CLK_UNCHGD |
IP clock enable is unchanged |
0x1 |
CLK_CLR |
Clear IP clock enable |
|
WO |
0 |
10
|
SPI0 |
Configure IP clock enable
Value |
ENUM Name |
Description |
0x0 |
CLK_UNCHGD |
IP clock enable is unchanged |
0x1 |
CLK_CLR |
Clear IP clock enable |
|
WO |
0 |
9:7
|
RESERVED7 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b000 |
6
|
I2C0 |
Configure IP clock enable
Value |
ENUM Name |
Description |
0x0 |
CLK_UNCHGD |
IP clock enable is unchanged |
0x1 |
CLK_CLR |
Clear IP clock enable |
|
WO |
0 |
5:4
|
RESERVED4 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0b00 |
3
|
UART1 |
Configure IP clock enable
Value |
ENUM Name |
Description |
0x0 |
CLK_UNCHGD |
IP clock enable is unchanged |
0x1 |
CLK_CLR |
Clear IP clock enable |
|
WO |
0 |
2
|
UART0 |
Configure IP clock enable
Value |
ENUM Name |
Description |
0x0 |
CLK_UNCHGD |
IP clock enable is unchanged |
0x1 |
CLK_CLR |
Clear IP clock enable |
|
WO |
0 |
1
|
LRFD |
Configure IP clock enable
Value |
ENUM Name |
Description |
0x0 |
CLK_UNCHGD |
IP clock enable is unchanged |
0x1 |
CLK_CLR |
Clear IP clock enable |
|
WO |
0 |
0
|
GPIO |
Configure IP clock enable
Value |
ENUM Name |
Description |
0x0 |
CLK_UNCHGD |
IP clock enable is unchanged |
0x1 |
CLK_CLR |
Clear IP clock enable |
|
WO |
0 |