Instance: CANFD
Component: CANFD
Base address: 0x400D0000
IPXACT generated on 6/2/2017 at 11:21 by the IPXCEL-to-IPXACT Converter Script v3.1
|
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
|
RO |
32 |
0x3238 0608 |
0x0000 0000 |
0x400D 0000 |
|
|
RO |
32 |
0x8765 4321 |
0x0000 0004 |
0x400D 0004 |
|
|
RW |
32 |
0x0000 0A33 |
0x0000 000C |
0x400D 000C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0010 |
0x400D 0010 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0014 |
0x400D 0014 |
|
|
RW |
32 |
0x0000 0001 |
0x0000 0018 |
0x400D 0018 |
|
|
RW |
32 |
0x0600 0A03 |
0x0000 001C |
0x400D 001C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0020 |
0x400D 0020 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0024 |
0x400D 0024 |
|
|
RW |
32 |
0xFFFF 0000 |
0x0000 0028 |
0x400D 0028 |
|
|
RW |
32 |
0x0000 FFFF |
0x0000 002C |
0x400D 002C |
|
|
RO |
32 |
0x0000 0000 |
0x0000 0040 |
0x400D 0040 |
|
|
RO |
32 |
0x0000 0707 |
0x0000 0044 |
0x400D 0044 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0048 |
0x400D 0048 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0050 |
0x400D 0050 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0054 |
0x400D 0054 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0058 |
0x400D 0058 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 005C |
0x400D 005C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0080 |
0x400D 0080 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0084 |
0x400D 0084 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0088 |
0x400D 0088 |
|
|
RW |
32 |
0x1FFF FFFF |
0x0000 0090 |
0x400D 0090 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 0094 |
0x400D 0094 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0098 |
0x400D 0098 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 009C |
0x400D 009C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 00A0 |
0x400D 00A0 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 00A4 |
0x400D 00A4 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 00A8 |
0x400D 00A8 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 00AC |
0x400D 00AC |
|
|
RW |
32 |
0x0000 0000 |
0x0000 00B0 |
0x400D 00B0 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 00B4 |
0x400D 00B4 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 00B8 |
0x400D 00B8 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 00BC |
0x400D 00BC |
|
|
RW |
32 |
0x0000 0000 |
0x0000 00C0 |
0x400D 00C0 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 00C4 |
0x400D 00C4 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 00C8 |
0x400D 00C8 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 00CC |
0x400D 00CC |
|
|
RW |
32 |
0x0000 0000 |
0x0000 00D0 |
0x400D 00D0 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 00D4 |
0x400D 00D4 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 00D8 |
0x400D 00D8 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 00DC |
0x400D 00DC |
|
|
RW |
32 |
0x0000 0000 |
0x0000 00E0 |
0x400D 00E0 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 00E4 |
0x400D 00E4 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 00F0 |
0x400D 00F0 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 00F4 |
0x400D 00F4 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 00F8 |
0x400D 00F8 |
|
|
RO |
32 |
0x68E0 4901 |
0x0000 0200 |
0x400D 0200 |
|
|
RW |
32 |
0x0000 0008 |
0x0000 0204 |
0x400D 0204 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 0208 |
0x400D 0208 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 020C |
0x400D 020C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0210 |
0x400D 0210 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0214 |
0x400D 0214 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0218 |
0x400D 0218 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 021C |
0x400D 021C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0220 |
0x400D 0220 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0224 |
0x400D 0224 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 0228 |
0x400D 0228 |
|
|
RO |
32 |
0x66A0 EA00 |
0x0000 0400 |
0x400D 0400 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0408 |
0x400D 0408 |
|
|
RO |
32 |
0x0000 0002 |
0x0000 040C |
0x400D 040C |
|
|
RO |
32 |
0x66A4 6A02 |
0x0000 0410 |
0x400D 0410 |
|
|
RW |
32 |
0x0000 0187 |
0x0000 0414 |
0x400D 0414 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0418 |
0x400D 0418 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 041C |
0x400D 041C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0420 |
0x400D 0420 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 0424 |
0x400D 0424 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0428 |
0x400D 0428 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 043C |
0x400D 043C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0440 |
0x400D 0440 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0480 |
0x400D 0480 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 04C0 |
0x400D 04C0 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 053C |
0x400D 053C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0540 |
0x400D 0540 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0580 |
0x400D 0580 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 05C0 |
0x400D 05C0 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0600 |
0x400D 0600 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0604 |
0x400D 0604 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0608 |
0x400D 0608 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 060C |
0x400D 060C |
|
|
RO |
32 |
0xC64F 0000 |
0x0000 0800 |
0x400D 0800 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0844 |
0x400D 0844 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 0848 |
0x400D 0848 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 084C |
0x400D 084C |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0850 |
0x400D 0850 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0854 |
0x400D 0854 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0864 |
0x400D 0864 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0868 |
0x400D 0868 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 086C |
0x400D 086C |
|
|
RO |
32 |
0x0000 0000 |
0x0000 0870 |
0x400D 0870 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0874 |
0x400D 0874 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0878 |
0x400D 0878 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0904 |
0x400D 0904 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0908 |
0x400D 0908 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 090C |
0x400D 090C |
|
|
RW |
32 |
0x0002 0000 |
0x0000 0924 |
0x400D 0924 |
|
|
RW |
32 |
0x0002 0000 |
0x0000 092C |
0x400D 092C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0938 |
0x400D 0938 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0948 |
0x400D 0948 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 0950 |
0x400D 0950 |
| Address Offset | 0x0000 0000 | ||
| Physical Address | 0x400D 0000 | Instance | 0x400D 0000 |
| Description | MCAN Core Release Register | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:28 | REL | Core Release. One digit, BCD-coded. | RO | 0x3 | ||
| 27:24 | STEP | Step of Core Release. One digit, BCD-coded. | RO | 0x2 | ||
| 23:20 | SUBSTEP | Sub-Step of Core Release. One digit, BCD-coded. | RO | 0x3 | ||
| 19:16 | YEAR | Time Stamp Year. One digit, BCD-coded. | RO | 0x8 | ||
| 15:8 | MON | Time Stamp Month. Two digits, BCD-coded. | RO | 0x06 | ||
| 7:0 | DAY | Time Stamp Day. Two digits, BCD-coded. | RO | 0x08 | ||
| Address Offset | 0x0000 0004 | ||
| Physical Address | 0x400D 0004 | Instance | 0x400D 0004 |
| Description | MCAN Endian Register | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | ETV | Endianess Test Value. Reading the constant value maintained in this register allows software to determine the endianess of the host CPU. | RO | 0x8765 4321 | ||
| Address Offset | 0x0000 000C | ||
| Physical Address | 0x400D 000C | Instance | 0x400D 000C |
| Description | This register is only writable if bits CCCR.CCE and CCCR.INIT are set. The CAN bit time may be programed in the range of 4 to 49 time quanta. The CAN time quantum may be programmed in the range of 1 to 32 m_can_cclk periods. tq = (DBRP + 1) mtq. DTSEG1 is the sum of Prop_Seg and Phase_Seg1. DTSEG2 is Phase_Seg2. Therefore the length of the bit time is (programmed values) (DTSEG1 + DTSEG2 + 3) tq or (functional values) (Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2) tq. The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 | ||
| 23 | TDC | Transmitter Delay Compensation 0 Transmitter Delay Compensation disabled 1 Transmitter Delay Compensation enabled +I107 |
RW | 0 | ||
| 22:21 | RESERVED21 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
| 20:16 | DBRP | Data Bit Rate Prescaler. The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0b0 0000 | ||
| 15:13 | RESERVED13 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | ||
| 12:8 | DTSEG1 | Data Time Segment Before Sample Point. Valid values are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0b0 1010 | ||
| 7:4 | DTSEG2 | Data Time Segment After Sample Point. Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0x3 | ||
| 3:0 | DSJW | Data Resynchronization Jump Width. Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0x3 | ||
| Address Offset | 0x0000 0010 | ||
| Physical Address | 0x400D 0010 | Instance | 0x400D 0010 |
| Description | Write access to the Test Register has to be enabled by setting bit CCCR.TEST to '1'. All Test Register functions are set to their reset values when bit CCCR.TEST is reset. Loop Back Mode and software control of the internal CAN TX pin are hardware test modes. Programming of TX ? "00" may disturb the message transfer on the CAN bus. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7 | RX | Receive Pin. Monitors the actual value of the CAN receive pin. 0 The CAN bus is dominant (CAN RX pin = '0') 1 The CAN bus is recessive (CAN RX pin = '1') |
RO | 0 | ||
| 6:5 | TX | Control of Transmit Pin 00 CAN TX pin controlled by the CAN Core, updated at the end of the CAN bit time 01 Sample Point can be monitored at CAN TX pin 10 Dominant ('0') level at CAN TX pin 11 Recessive ('1') at CAN TX pin Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0b00 | ||
| 4 | LBCK | Loop Back Mode 0 Reset value, Loop Back Mode is disabled 1 Loop Back Mode is enabled Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0 | ||
| 3:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 | ||
| Address Offset | 0x0000 0014 | ||
| Physical Address | 0x400D 0014 | Instance | 0x400D 0014 |
| Description | MCAN RAM Watchdog | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
| 15:8 | WDV | Watchdog Value. Acutal Message RAM Watchdog Counter Value. The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access via the MCAN's Generic Master Interface starts the Message RAM Watchdog Counter with the value configured by the WDC field. The counter is reloaded with WDC when the Message RAM signals successful completion by activating its READY output. In case there is no response from the Message RAM until the counter has counted down to zero, the counter stops and interrupt flag MCAN_IR.WDI is set. The RAM Watchdog Counter is clocked by the host (system) clock. |
RO | 0x00 | ||
| 7:0 | WDC | Watchdog Configuration. Start value of the Message RAM Watchdog Counter. With the reset value of "00" the counter is disabled. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0x00 | ||
| Address Offset | 0x0000 0018 | ||
| Physical Address | 0x400D 0018 | Instance | 0x400D 0018 |
| Description | MCAN CC Control Register | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
| 15 | NISO | Non ISO Operation. If this bit is set, the MCAN uses the CAN FD frame format as specified by the Bosch CAN FD Specification V1.0. 0 CAN FD frame format according to ISO 11898-1:2015 1 CAN FD frame format according to Bosch CAN FD Specification V1.0 |
RW | 0 | ||
| 14 | TXP | Transmit Pause. If this bit is set, the MCAN pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame. 0 Transmit pause disabled 1 Transmit pause enabled Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0 | ||
| 13 | EFBI | Edge Filtering during Bus Integration 0 Edge filtering disabled 1 Two consecutive dominant tq required to detect an edge for hard synchronization Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0 | ||
| 12 | PXHD | Protocol Exception Handling Disable 0 Protocol exception handling enabled 1 Protocol exception handling disabled Note: When protocol exception handling is disabled, the MCAN will transmit an error frame when it detects a protocol exception condition. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0 | ||
| 11:10 | RESERVED10 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
| 9 | BRSE | Bit Rate Switch Enable 0 Bit rate switching for transmissions disabled 1 Bit rate switching for transmissions enabled Note: When CAN FD operation is disabled FDOE = '0', BRSE is not evaluated. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0 | ||
| 8 | FDOE | Flexible Datarate Operation Enable 0 FD operation disabled 1 FD operation enabled Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0 | ||
| 7 | TEST | Test Mode Enable 0 Normal operation, register TEST holds reset values 1 Test Mode, write access to register TEST enabled Qualified Write 1 to Set is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0 | ||
| 6 | DAR | Disable Automatic Retransmission 0 Automatic retransmission of messages not transmitted successfully enabled 1 Automatic retransmission disabled Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0 | ||
| 5 | MON | Bus Monitoring Mode. Bit MON can only be set by SW when both CCE and INIT are set to '1'. The bit can be reset by SW at any time. 0 Bus Monitoring Mode is disabled 1 Bus Monitoring Mode is enabled Qualified Write 1 to Set is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0 | ||
| 4 | CSR | Clock Stop Request 0 No clock stop is requested 1 Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pending transfer requests have been completed and the CAN bus reached idle. |
RW | 0 | ||
| 3 | CSA | Clock Stop Acknowledge 0 No clock stop acknowledged 1 MCAN may be set in power down by stopping the Host and CAN clocks |
RO | 0 | ||
| 2 | ASM | Restricted Operation Mode. Bit ASM can only be set by SW when both CCE and INIT are set to '1'. The bit can be reset by SW at any time. 0 Normal CAN operation 1 Restricted Operation Mode active Qualified Write 1 to Set is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0 | ||
| 1 | CCE | Configuration Change Enable 0 The CPU has no write access to the protected configuration registers 1 The CPU has write access to the protected configuration registers (while CCCR.INIT = '1') Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0 | ||
| 0 | INIT | Initialization 0 Normal Operation 1 Initialization is started Note: Due to the synchronization mechanism between the two clock domains, there may be a delay until the value written to INIT can be read back. Therefore the programmer has to assure that the previous value written to INIT has been accepted by reading INIT before setting INIT to a new value. |
RW | 1 | ||
| Address Offset | 0x0000 001C | ||
| Physical Address | 0x400D 001C | Instance | 0x400D 001C |
| Description | This register is only writable if bits CCCR.CCE and CCCR.INIT are set. The CAN bit time may be programed in the range of 4 to 385 time quanta. The CAN time quantum may be programmed in the range of 1 to 512 m_can_cclk periods. tq = (NBRP + 1) mtq. NTSEG1 is the sum of Prop_Seg and Phase_Seg1. NTSEG2 is Phase_Seg2. Therefore the length of the bit time is (programmed values) (NTSEG1 + NTSEG2 + 3) tq or (functional values) (Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2) tq. The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point. Note: With a CAN clock of 8 MHz, the reset value of 0x06000A03 configures the MCAN for a bit rate of 500 kBit/s. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:25 | NSJW | Nominal (Re)Synchronization Jump Width. Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0b000 0011 | ||
| 24:16 | NBRP | Nominal Bit Rate Prescaler. The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0b0 0000 0000 | ||
| 15:8 | NTSEG1 | Nominal Time Segment Before Sample Point. Valid values are 1 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0x0A | ||
| 7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| 6:0 | NTSEG2 | Nominal Time Segment After Sample Point. Valid values are 1 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0b000 0011 | ||
| Address Offset | 0x0000 0020 | ||
| Physical Address | 0x400D 0020 | Instance | 0x400D 0020 |
| Description | MCAN Timestamp Counter Configuration | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:20 | RESERVED20 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 | ||
| 19:16 | TCP | Timestamp Counter Prescaler. Configures the timestamp and timeout counters time unit in multiples of CAN bit times. Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. Note: With CAN FD an external counter is required for timestamp generation (TSS = "10"). Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0x0 | ||
| 15:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 | ||
| 1:0 | TSS | Timestamp Select 00 Timestamp counter value always 0x0000 01 Timestamp counter value incremented according to TCP 10 External timestamp counter value used 11 Same as "00" Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0b00 | ||
| Address Offset | 0x0000 0024 | ||
| Physical Address | 0x400D 0024 | Instance | 0x400D 0024 |
| Description | MCAN Timestamp Counter Value | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
| 15:0 | TSC | Timestamp Counter. The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When TSCC.TSS = "01", the Timestamp Counter is incremented in multiples of CAN bit times, (1...16), depending on the configuration of TSCC.TCP. A wrap around sets interrupt flag IR.TSW. Write access resets the counter to zero. When TSCC.TSS = "10", TSC reflects the External Timestamp Counter value, and a write access has no impact. Note: A "wrap around" is a change of the Timestamp Counter value from non-zero to zero not caused by write access to MCAN_TSCV. |
RW | 0x0000 | ||
| Address Offset | 0x0000 0028 | ||
| Physical Address | 0x400D 0028 | Instance | 0x400D 0028 |
| Description | MCAN Timeout Counter Configuration | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:16 | TOP | Timeout Period. Start value of the Timeout Counter (down-counter). Configures the Timeout Period. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0xFFFF | ||
| 15:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 | ||
| 2:1 | TOS | Timeout Select. When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting. When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting is started when the first FIFO element is stored. 00 Continuous operation 01 Timeout controlled by Tx Event FIFO 10 Timeout controlled by Rx FIFO 0 11 Timeout controlled by Rx FIFO 1 Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0b00 | ||
| 0 | ETOC | Enable Timeout Counter 0 Timeout Counter disabled 1 Timeout Counter enabled Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0 | ||
| Address Offset | 0x0000 002C | ||
| Physical Address | 0x400D 002C | Instance | 0x400D 002C |
| Description | MCAN Timeout Counter Value | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
| 15:0 | TOC | Timeout Counter. The Timeout Counter is decremented in multiples of CAN bit times, (1...16), depending on the configuration of TSCC.TCP. When decremented to zero, interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS. | RW | 0xFFFF | ||
| Address Offset | 0x0000 0040 | ||
| Physical Address | 0x400D 0040 | Instance | 0x400D 0040 |
| Description | MCAN Error Counter Register | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 | ||
| 23:16 | CEL | CAN Error Logging. The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR.ELO. Note: When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented. |
RO | 0x00 | ||
| 15 | RP | Receive Error Passive 0 The Receive Error Counter is below the error passive level of 128 1 The Receive Error Counter has reached the error passive level of 128 |
RO | 0 | ||
| 14:8 | REC | Receive Error Counter. Actual state of the Receive Error Counter, values between 0 and 127. Note: When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented. |
RO | 0b000 0000 | ||
| 7:0 | TEC | Transmit Error Counter. Actual state of the Transmit Error Counter, values between 0 and 255. Note: When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented. |
RO | 0x00 | ||
| Address Offset | 0x0000 0044 | ||
| Physical Address | 0x400D 0044 | Instance | 0x400D 0044 |
| Description | MCAN Protocol Status Register | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:23 | RESERVED23 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 | ||
| 22:16 | TDCV | Transmitter Delay Compensation Value. Position of the secondary sample point, defined by the sum of the measured delay from the internal CAN TX signal to the internal CAN RX signal and TDCR.TDCO. The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq. | RO | 0b000 0000 | ||
| 15 | RESERVED15 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| 14 | PXE | Protocol Exception Event 0 No protocol exception event occurred since last read access 1 Protocol exception event occurred |
RO | 0 | ||
| 13 | RFDF | Received a CAN FD Message. This bit is set independent of acceptance filtering. 0 Since this bit was reset by the CPU, no CAN FD message has been received 1 Message in CAN FD format with FDF flag set has been received |
RO | 0 | ||
| 12 | RBRS | BRS Flag of Last Received CAN FD Message. This bit is set together with RFDF, independent of acceptance filtering. 0 Last received CAN FD message did not have its BRS flag set 1 Last received CAN FD message had its BRS flag set |
RO | 0 | ||
| 11 | RESI | ESI Flag of Last Received CAN FD Message. This bit is set together with RFDF, independent of acceptance filtering. 0 Last received CAN FD message did not have its ESI flag set 1 Last received CAN FD message had its ESI flag set |
RO | 0 | ||
| 10:8 | DLEC | Data Phase Last Error Code. Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with its BRS flag set has been transferred (reception or transmission) without error. | RO | 0b111 | ||
| 7 | BO | Bus_Off Status 0 The M_CAN is not Bus_Off 1 The M_CAN is in Bus_Off state |
RO | 0 | ||
| 6 | EW | Warning Status 0 Both error counters are below the Error_Warning limit of 96 1 At least one of error counter has reached the Error_Warning limit of 96 |
RO | 0 | ||
| 5 | EP | Error Passive 0 The M_CAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 1 The M_CAN is in the Error_Passive state |
RO | 0 | ||
| 4:3 | ACT | Node Activity. Monitors the module's CAN communication state. 00 Synchronizing - node is synchronizing on CAN communication 01 Idle - node is neither receiver nor transmitter 10 Receiver - node is operating as receiver 11 Transmitter - node is operating as transmitter Note: ACT is set to "00" by a Protocol Exception Event. |
RO | 0b00 | ||
| 2:0 | LEC | Last Error Code. The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to '0' when a message has been transferred (reception or transmission) without error. 0 No Error: No error occurred since LEC has been reset by successful reception or transmission. 1 Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 2 Form Error: A fixed format part of a received frame has the wrong format. 3 AckError: The message transmitted by the MCAN was not acknowledged by another node. 4 Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant. 5 Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value '0'), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). 6 CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. 7 NoChange: Any read access to the Protocol Status Register re-initializes the LEC to '7'. When the LEC shows the value '7', no CAN bus event was detected since the last CPU read access to the Protocol Status Register. Note: When a frame in CAN FD format has reached the data phase with BRS flag set, the next CAN event (error or valid frame) will be shown in DLEC instead of LEC. An error in a fixed stuff bit of a CAN FD CRC sequence will be shown as a Form Error, not Stuff Error. Note: The Bus_Off recovery sequence (see ISO 11898-1:2015) cannot be shortened by setting or resetting CCCR.INIT. If the device goes Bus_Off, it will set CCCR.INIT of its own accord, stopping all bus activities. Once CCCR.INIT has been cleared by the CPU, the device will then wait for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal operation. At the end of the Bus_Off recovery sequence, the Error Management Counters will be reset. During the waiting time after the resetting of CCCR.INIT, each time a sequence of 11 recessive bits has been monitored, a Bit0Error code is written to PSR.LEC, enabling the CPU to readily check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the Bus_Off recovery sequence. ECR.REC is used to count these sequences. |
RO | 0b111 | ||
| Address Offset | 0x0000 0048 | ||
| Physical Address | 0x400D 0048 | Instance | 0x400D 0048 |
| Description | MCAN Transmitter Delay Compensation Register | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:15 | RESERVED15 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 | ||
| 14:8 | TDCO | Transmitter Delay Compensation Offset. Offset value defining the distance between the measured delay from the internal CAN TX signal to the internal CAN RX signal and the secondary sample point. Valid values are 0 to 127 mtq. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0b000 0000 | ||
| 7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| 6:0 | TDCF | Transmitter Delay Compensation Filter Window Length. Defines the minimum value for the SSP position, dominant edges on the internal CAN RX signal that would result in an earlier SSP position are ignored for transmitter delay measurement. The feature is enabled when TDCF is configured to a value greater than TDCO. Valid values are 0 to 127 mtq. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0b000 0000 | ||
| Address Offset | 0x0000 0050 | ||
| Physical Address | 0x400D 0050 | Instance | 0x400D 0050 |
| Description | The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. Aflag is cleared by writing a '1' to the corresponding bit position. Writing a '0' has no effect. Ahard reset will clear the register. The configuration of IE controls whether an interrupt is generated. The configuration of ILS controls on which interrupt line an interrupt is signalled. | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:30 | RESERVED30 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
| 29 | ARA | Access to Reserved Address 0 No access to reserved address occurred 1 Access to reserved address occurred |
RW | 0 | ||
| 28 | PED | Protocol Error in Data Phase (Data Bit Time is used) 0 No protocol error in data phase 1 Protocol error in data phase detected (PSR.DLEC ? 0,7) |
RW | 0 | ||
| 27 | PEA | Protocol Error in Arbitration Phase (Nominal Bit Time is used) 0 No protocol error in arbitration phase 1 Protocol error in arbitration phase detected (PSR.LEC ? 0,7) |
RW | 0 | ||
| 26 | WDI | Watchdog Interrupt 0 No Message RAM Watchdog event occurred 1 Message RAM Watchdog event due to missing READY |
RW | 0 | ||
| 25 | BO | Bus_Off Status 0 Bus_Off status unchanged 1 Bus_Off status changed |
RW | 0 | ||
| 24 | EW | Warning Status 0 Error_Warning status unchanged 1 Error_Warning status changed |
RW | 0 | ||
| 23 | EP | Error Passive 0 Error_Passive status unchanged 1 Error_Passive status changed |
RW | 0 | ||
| 22 | ELO | Error Logging Overflow 0 CAN Error Logging Counter did not overflow 1 Overflow of CAN Error Logging Counter occurred |
RW | 0 | ||
| 21 | BEU | Bit Error Uncorrected. Message RAM bit error detected, uncorrected. This bit is set when a double bit error is detected by the ECC aggregator attached to the Message RAM. An uncorrected Message RAM bit error sets CCCR.INIT to '1'. This is done to avoid transmission of corrupted data. 0 No bit error detected when reading from Message RAM 1 Bit error detected, uncorrected (e.g. parity logic) |
RW | 0 | ||
| 20 | RESERVED20 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| 19 | DRX | Message Stored to Dedicated Rx Buffer. The flag is set whenever a received message has been stored into a dedicated Rx Buffer. 0 No Rx Buffer updated 1 At least one received message stored into an Rx Buffer |
RW | 0 | ||
| 18 | TOO | Timeout Occurred 0 No timeout 1 Timeout reached |
RW | 0 | ||
| 17 | MRAF | Message RAM Access Failure. The flag is set, when the Rx Handler: - has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx Handler starts processing of the following message. - was not able to write a message to the Message RAM. In this case message storage is aborted. In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location. The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the MCAN is switched into Restricted Operation Mode. To leave Restricted Operation Mode, the Host CPU has to reset CCCR.ASM. 0 No Message RAM access failure occurred 1 Message RAM access failure occurred |
RW | 0 | ||
| 16 | TSW | Timestamp Wraparound 0 No timestamp counter wrap-around 1 Timestamp counter wrapped around |
RW | 0 | ||
| 15 | TEFL | Tx Event FIFO Element Lost 0 No Tx Event FIFO element lost 1 Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero |
RW | 0 | ||
| 14 | TEFF | Tx Event FIFO Full 0 Tx Event FIFO not full 1 Tx Event FIFO full |
RW | 0 | ||
| 13 | TEFW | Tx Event FIFO Watermark Reached 0 Tx Event FIFO fill level below watermark 1 Tx Event FIFO fill level reached watermark |
RW | 0 | ||
| 12 | TEFN | Tx Event FIFO New Entry 0 Tx Event FIFO unchanged 1 Tx Handler wrote Tx Event FIFO element |
RW | 0 | ||
| 11 | TFE | Tx FIFO Empty 0 Tx FIFO non-empty 1 Tx FIFO empty |
RW | 0 | ||
| 10 | TCF | Transmission Cancellation Finished 0 No transmission cancellation finished 1 Transmission cancellation finished |
RW | 0 | ||
| 9 | TC | Transmission Completed 0 No transmission completed 1 Transmission completed |
RW | 0 | ||
| 8 | HPM | High Priority Message 0 No high priority message received 1 High priority message received |
RW | 0 | ||
| 7 | RF1L | Rx FIFO 1 Message Lost 0 No Rx FIFO 1 message lost 1 Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero |
RW | 0 | ||
| 6 | RF1F | Rx FIFO 1 Full 0 Rx FIFO 1 not full 1 Rx FIFO 1 full |
RW | 0 | ||
| 5 | RF1W | Rx FIFO 1 Watermark Reached 0 Rx FIFO 1 fill level below watermark 1 Rx FIFO 1 fill level reached watermark |
RW | 0 | ||
| 4 | RF1N | Rx FIFO 1 New Message 0 No new message written to Rx FIFO 1 1 New message written to Rx FIFO 1 |
RW | 0 | ||
| 3 | RF0L | Rx FIFO 0 Message Lost 0 No Rx FIFO 0 message lost 1 Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero |
RW | 0 | ||
| 2 | RF0F | Rx FIFO 0 Full 0 Rx FIFO 0 not full 1 Rx FIFO 0 full |
RW | 0 | ||
| 1 | RF0W | Rx FIFO 0 Watermark Reached 0 Rx FIFO 0 fill level below watermark 1 Rx FIFO 0 fill level reached watermark |
RW | 0 | ||
| 0 | RF0N | Rx FIFO 0 New Message 0 No new message written to Rx FIFO 0 1 New message written to Rx FIFO 0 |
RW | 0 | ||
| Address Offset | 0x0000 0054 | ||
| Physical Address | 0x400D 0054 | Instance | 0x400D 0054 |
| Description | MCAN Interrupt Enable | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:30 | RESERVED30 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
| 29 | ARAE | Access to Reserved Address Enable | RW | 0 | ||
| 28 | PEDE | Protocol Error in Data Phase Enable | RW | 0 | ||
| 27 | PEAE | Protocol Error in Arbitration Phase Enable | RW | 0 | ||
| 26 | WDIE | Watchdog Interrupt Enable | RW | 0 | ||
| 25 | BOE | Bus_Off Status Enable | RW | 0 | ||
| 24 | EWE | Warning Status Enable | RW | 0 | ||
| 23 | EPE | Error Passive Enable | RW | 0 | ||
| 22 | ELOE | Error Logging Overflow Enable | RW | 0 | ||
| 21 | BEUE | Bit Error Uncorrected Enable | RW | 0 | ||
| 20 | RESERVED20 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| 19 | DRXE | Message Stored to Dedicated Rx Buffer Enable | RW | 0 | ||
| 18 | TOOE | Timeout Occurred Enable | RW | 0 | ||
| 17 | MRAFE | Message RAM Access Failure Enable | RW | 0 | ||
| 16 | TSWE | Timestamp Wraparound Enable | RW | 0 | ||
| 15 | TEFLE | Tx Event FIFO Element Lost Enable | RW | 0 | ||
| 14 | TEFFE | Tx Event FIFO Full Enable | RW | 0 | ||
| 13 | TEFWE | Tx Event FIFO Watermark Reached Enable | RW | 0 | ||
| 12 | TEFNE | Tx Event FIFO New Entry Enable | RW | 0 | ||
| 11 | TFEE | Tx FIFO Empty Enable | RW | 0 | ||
| 10 | TCFE | Transmission Cancellation Finished Enable | RW | 0 | ||
| 9 | TCE | Transmission Completed Enable | RW | 0 | ||
| 8 | HPME | High Priority Message Enable | RW | 0 | ||
| 7 | RF1LE | Rx FIFO 1 Message Lost Enable | RW | 0 | ||
| 6 | RF1FE | Rx FIFO 1 Full Enable | RW | 0 | ||
| 5 | RF1WE | Rx FIFO 1 Watermark Reached Enable | RW | 0 | ||
| 4 | RF1NE | Rx FIFO 1 New Message Enable | RW | 0 | ||
| 3 | RF0LE | Rx FIFO 0 Message Lost Enable | RW | 0 | ||
| 2 | RF0FE | Rx FIFO 0 Full Enable | RW | 0 | ||
| 1 | RF0WE | Rx FIFO 0 Watermark Reached Enable | RW | 0 | ||
| 0 | RF0NE | Rx FIFO 0 New Message Enable | RW | 0 | ||
| Address Offset | 0x0000 0058 | ||
| Physical Address | 0x400D 0058 | Instance | 0x400D 0058 |
| Description | The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt Register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via ILE.EINT0 and ILE.EINT1. | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:30 | RESERVED30 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
| 29 | ARAL | Access to Reserved Address Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 |
RW | 0 | ||
| 28 | PEDL | Protocol Error in Data Phase Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 |
RW | 0 | ||
| 27 | PEAL | Protocol Error in Arbitration Phase Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 |
RW | 0 | ||
| 26 | WDIL | Watchdog Interrupt Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 |
RW | 0 | ||
| 25 | BOL | Bus_Off Status Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 |
RW | 0 | ||
| 24 | EWL | Warning Status Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 |
RW | 0 | ||
| 23 | EPL | Error Passive Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 |
RW | 0 | ||
| 22 | ELOL | Error Logging Overflow Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 |
RW | 0 | ||
| 21 | BEUL | Bit Error Uncorrected Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 |
RW | 0 | ||
| 20 | RESERVED20 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| 19 | DRXL | Message Stored to Dedicated Rx Buffer Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 |
RW | 0 | ||
| 18 | TOOL | Timeout Occurred Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 |
RW | 0 | ||
| 17 | MRAFL | Message RAM Access Failure Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 |
RW | 0 | ||
| 16 | TSWL | Timestamp Wraparound Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 |
RW | 0 | ||
| 15 | TEFLL | Tx Event FIFO Element Lost Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 |
RW | 0 | ||
| 14 | TEFFL | Tx Event FIFO Full Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 |
RW | 0 | ||
| 13 | TEFWL | Tx Event FIFO Watermark Reached Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 |
RW | 0 | ||
| 12 | TEFNL | Tx Event FIFO New Entry Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 |
RW | 0 | ||
| 11 | TFEL | Tx FIFO Empty Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 |
RW | 0 | ||
| 10 | TCFL | Transmission Cancellation Finished Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 |
RW | 0 | ||
| 9 | TCL | Transmission Completed Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 |
RW | 0 | ||
| 8 | HPML | High Priority Message Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 |
RW | 0 | ||
| 7 | RF1LL | Rx FIFO 1 Message Lost Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 |
RW | 0 | ||
| 6 | RF1FL | Rx FIFO 1 Full Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 |
RW | 0 | ||
| 5 | RF1WL | Rx FIFO 1 Watermark Reached Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 |
RW | 0 | ||
| 4 | RF1NL | Rx FIFO 1 New Message Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 |
RW | 0 | ||
| 3 | RF0LL | Rx FIFO 0 Message Lost Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 |
RW | 0 | ||
| 2 | RF0FL | Rx FIFO 0 Full Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 |
RW | 0 | ||
| 1 | RF0WL | Rx FIFO 0 Watermark Reached Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 |
RW | 0 | ||
| 0 | RF0NL | Rx FIFO 0 New Message Line 0 Interrupt source is assigned to Interrupt Line 0 1 Interrupt source is assigned to Interrupt Line 1 |
RW | 0 | ||
| Address Offset | 0x0000 005C | ||
| Physical Address | 0x400D 005C | Instance | 0x400D 005C |
| Description | MCAN Interrupt Line Enable | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | EINT1 | Enable Interrupt Line 1 0 Interrupt Line 1 is disabled 1 Interrupt Line 1 is enabled |
RW | 0 | ||
| 0 | EINT0 | Enable Interrupt Line 0 0 Interrupt Line 0 is disabled 1 Interrupt Line 0 is enabled |
RW | 0 | ||
| Address Offset | 0x0000 0080 | ||
| Physical Address | 0x400D 0080 | Instance | 0x400D 0080 |
| Description | MCAN Global Filter Configuration | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 | ||
| 5:4 | ANFS | Accept Non-matching Frames Standard. Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 00 Accept in Rx FIFO 0 01 Accept in Rx FIFO 1 10 Reject 11 Reject Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0b00 | ||
| 3:2 | ANFE | Accept Non-matching Frames Extended. Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 00 Accept in Rx FIFO 0 01 Accept in Rx FIFO 1 10 Reject 11 Reject Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0b00 | ||
| 1 | RRFS | Reject Remote Frames Standard 0 Filter remote frames with 11-bit standard IDs 1 Reject all remote frames with 11-bit standard IDs Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0 | ||
| 0 | RRFE | Reject Remote Frames Extended 0 Filter remote frames with 29-bit extended IDs 1 Reject all remote frames with 29-bit extended IDs Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0 | ||
| Address Offset | 0x0000 0084 | ||
| Physical Address | 0x400D 0084 | Instance | 0x400D 0084 |
| Description | MCAN Standard ID Filter Configuration | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 | ||
| 23:16 | LSS | List Size Standard 0 No standard Message ID filter 1-128 Number of standard Message ID filter elements >128 Values greater than 128 are interpreted as 128 |
RW | 0x00 | ||
| 15:2 | FLSSA | Filter List Standard Start Address. Start address of standard Message ID filter list (32-bit word address). | RW | 0b00 0000 0000 0000 | ||
| 1:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
| Address Offset | 0x0000 0088 | ||
| Physical Address | 0x400D 0088 | Instance | 0x400D 0088 |
| Description | MCAN Extended ID Filter Configuration | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:23 | RESERVED23 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 | ||
| 22:16 | LSE | Filter List Extended Start Address. Start address of extended Message ID filter list (32-bit word address). Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0b000 0000 | ||
| 15:2 | FLESA | List Size Extended 0 No extended Message ID filter 1-64 Number of extended Message ID filter elements >64 Values greater than 64 are interpreted as 64 Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0b00 0000 0000 0000 | ||
| 1:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
| Address Offset | 0x0000 0090 | ||
| Physical Address | 0x400D 0090 | Instance | 0x400D 0090 |
| Description | MCAN Extended ID and Mask | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:29 | RESERVED29 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | ||
| 28:0 | EIDM | Extended ID Mask. For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0b1 1111 1111 1111 1111 1111 1111 1111 | ||
| Address Offset | 0x0000 0094 | ||
| Physical Address | 0x400D 0094 | Instance | 0x400D 0094 |
| Description | This register is updated every time a Message ID filter element configured to generate a priority event matches. This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages. | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
| 15 | FLST | Filter List. Indicates the filter list of the matching filter element. 0 Standard Filter List 1 Extended Filter List |
RO | 0 | ||
| 14:8 | FIDX | Filter Index. Index of matching filter element. Range is 0 to SIDFC.LSS - 1 resp. XIDFC.LSE - 1. | RO | 0b000 0000 | ||
| 7:6 | MSI | Message Storage Indicator 00 No FIFO selected 01 FIFO message lost 10 Message stored in FIFO 0 11 Message stored in FIFO 1 |
RO | 0b00 | ||
| 5:0 | BIDX | Buffer Index. Index of Rx FIFO element to which the message was stored. Only valid when MSI(1) = '1'. | RO | 0b00 0000 | ||
| Address Offset | 0x0000 0098 | ||
| Physical Address | 0x400D 0098 | Instance | 0x400D 0098 |
| Description | MCAN New Data 1 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31 | ND31 | New Data RX Buffer 31 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 30 | ND30 | New Data RX Buffer 30 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 29 | ND29 | New Data RX Buffer 29 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 28 | ND28 | New Data RX Buffer 28 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 27 | ND27 | New Data RX Buffer 27 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 26 | ND26 | New Data RX Buffer 26 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 25 | ND25 | New Data RX Buffer 25 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 24 | ND24 | New Data RX Buffer 24 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 23 | ND23 | New Data RX Buffer 23 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 22 | ND22 | New Data RX Buffer 22 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 21 | ND21 | New Data RX Buffer 21 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 20 | ND20 | New Data RX Buffer 20 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 19 | ND19 | New Data RX Buffer 19 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 18 | ND18 | New Data RX Buffer 18 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 17 | ND17 | New Data RX Buffer 17 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 16 | ND16 | New Data RX Buffer 16 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 15 | ND15 | New Data RX Buffer 15 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 14 | ND14 | New Data RX Buffer 14 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 13 | ND13 | New Data RX Buffer 13 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 12 | ND12 | New Data RX Buffer 12 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 11 | ND11 | New Data RX Buffer 11 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 10 | ND10 | New Data RX Buffer 10 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 9 | ND9 | New Data RX Buffer 9 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 8 | ND8 | New Data RX Buffer 8 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 7 | ND7 | New Data RX Buffer 7 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 6 | ND6 | New Data RX Buffer 6 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 5 | ND5 | New Data RX Buffer 5 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 4 | ND4 | New Data RX Buffer 4 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 3 | ND3 | New Data RX Buffer 3 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 2 | ND2 | New Data RX Buffer 2 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 1 | ND1 | New Data RX Buffer 1 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 0 | ND0 | New Data RX Buffer 0 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| Address Offset | 0x0000 009C | ||
| Physical Address | 0x400D 009C | Instance | 0x400D 009C |
| Description | MCAN New Data 2 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31 | ND63 | New Data RX Buffer 63 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 30 | ND62 | New Data RX Buffer 62 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 29 | ND61 | New Data RX Buffer 61 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 28 | ND60 | New Data RX Buffer 60 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 27 | ND59 | New Data RX Buffer 59 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 26 | ND58 | New Data RX Buffer 58 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 25 | ND57 | New Data RX Buffer 57 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 24 | ND56 | New Data RX Buffer 56 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 23 | ND55 | New Data RX Buffer 55 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 22 | ND54 | New Data RX Buffer 54 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 21 | ND53 | New Data RX Buffer 53 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 20 | ND52 | New Data RX Buffer 52 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 19 | ND51 | New Data RX Buffer 51 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 18 | ND50 | New Data RX Buffer 50 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 17 | ND49 | New Data RX Buffer 49 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 16 | ND48 | New Data RX Buffer 48 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 15 | ND47 | New Data RX Buffer 47 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 14 | ND46 | New Data RX Buffer 46 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 13 | ND45 | New Data RX Buffer 45 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 12 | ND44 | New Data RX Buffer 44 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 11 | ND43 | New Data RX Buffer 43 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 10 | ND42 | New Data RX Buffer 42 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 9 | ND41 | New Data RX Buffer 41 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 8 | ND40 | New Data RX Buffer 40 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 7 | ND39 | New Data RX Buffer 39 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 6 | ND38 | New Data RX Buffer 38 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 5 | ND37 | New Data RX Buffer 37 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 4 | ND36 | New Data RX Buffer 36 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 3 | ND35 | New Data RX Buffer 35 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 2 | ND34 | New Data RX Buffer 34 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 1 | ND33 | New Data RX Buffer 33 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| 0 | ND32 | New Data RX Buffer 32 0 Rx Buffer not updated 1 Rx Buffer updated from new message |
RW | 0 | ||
| Address Offset | 0x0000 00A0 | ||
| Physical Address | 0x400D 00A0 | Instance | 0x400D 00A0 |
| Description | MCAN Rx FIFO 0 Configuration | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31 | F0OM | FIFO 0 Operation Mode. FIFO 0 can be operated in blocking or in overwrite mode. 0 FIFO 0 blocking mode 1 FIFO 0 overwrite mode Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0 | ||
| 30:24 | F0WM | Rx FIFO 0 Watermark 0 Watermark interrupt disabled 1-64 Level for Rx FIFO 0 watermark interrupt (IR.RF0W) >64 Watermark interrupt disabled Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0b000 0000 | ||
| 23 | RESERVED23 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| 22:16 | F0S | Rx FIFO 0 Size. The Rx FIFO 0 elements are indexed from 0 to F0S-1. 0 No Rx FIFO 0 1-64 Number of Rx FIFO 0 elements >64 Values greater than 64 are interpreted as 64 Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0b000 0000 | ||
| 15:2 | F0SA | Rx FIFO 0 Start Address. Start address of Rx FIFO 0 in Message RAM (32-bit word address). Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0b00 0000 0000 0000 | ||
| 1:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
| Address Offset | 0x0000 00A4 | ||
| Physical Address | 0x400D 00A4 | Instance | 0x400D 00A4 |
| Description | MCAN Rx FIFO 0 Status | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:26 | RESERVED26 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 | ||
| 25 | RF0L | Rx FIFO 0 Message Lost. This bit is a copy of interrupt flag IR.RF0L. When IR.RF0L is reset, this bit is also reset. 0 No Rx FIFO 0 message lost 1 Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero Note: Overwriting the oldest message when RXF0C.F0OM = '1' will not set this flag. |
RO | 0 | ||
| 24 | F0F | Rx FIFO 0 Full 0 Rx FIFO 0 not full 1 Rx FIFO 0 full |
RO | 0 | ||
| 23:22 | RESERVED22 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
| 21:16 | F0PI | Rx FIFO 0 Put Index. Rx FIFO 0 write index pointer, range 0 to 63. | RO | 0b00 0000 | ||
| 15:14 | RESERVED14 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
| 13:8 | F0GI | Rx FIFO 0 Get Index. Rx FIFO 0 read index pointer, range 0 to 63. | RO | 0b00 0000 | ||
| 7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| 6:0 | F0FL | Rx FIFO 0 Fill Level. Number of elements stored in Rx FIFO 0, range 0 to 64. | RO | 0b000 0000 | ||
| Address Offset | 0x0000 00A8 | ||
| Physical Address | 0x400D 00A8 | Instance | 0x400D 00A8 |
| Description | MCAN Rx FIFO 0 Acknowledge | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 | ||
| 5:0 | F0AI | Rx FIFO 0 Acknowledge Index. After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL. | RW | 0b00 0000 | ||
| Address Offset | 0x0000 00AC | ||
| Physical Address | 0x400D 00AC | Instance | 0x400D 00AC |
| Description | MCAN Rx Buffer Configuration | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
| 15:2 | RBSA | Rx Buffer Start Address. Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address). +I466 |
RW | 0b00 0000 0000 0000 | ||
| 1:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
| Address Offset | 0x0000 00B0 | ||
| Physical Address | 0x400D 00B0 | Instance | 0x400D 00B0 |
| Description | MCAN Rx FIFO 1 Configuration | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31 | F1OM | FIFO 1 Operation Mode. FIFO 1 can be operated in blocking or in overwrite mode. 0 FIFO 1 blocking mode 1 FIFO 1 overwrite mode Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0 | ||
| 30:24 | F1WM | Rx FIFO 1 Watermark 0 Watermark interrupt disabled 1-64 Level for Rx FIFO 1 watermark interrupt (IR.RF1W) >64 Watermark interrupt disabled Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0b000 0000 | ||
| 23 | RESERVED23 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| 22:16 | F1S | Rx FIFO 1 Size. The Rx FIFO 1 elements are indexed from 0 to F1S - 1. 0 No Rx FIFO 1 1-64 Number of Rx FIFO 1 elements >64 Values greater than 64 are interpreted as 64 Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0b000 0000 | ||
| 15:2 | F1SA | Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address). | RW | 0b00 0000 0000 0000 | ||
| 1:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
| Address Offset | 0x0000 00B4 | ||
| Physical Address | 0x400D 00B4 | Instance | 0x400D 00B4 |
| Description | MCAN Rx FIFO 1 Status | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:30 | DMS | Debug Message Status 00 Idle state, wait for reception of debug messages, DMA request is cleared 01 Debug message A received 10 Debug messages A, B received 11 Debug messages A, B, C received, DMA request is set |
RO | 0b00 | ||
| 29:26 | RESERVED26 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 | ||
| 25 | RF1L | Rx FIFO 1 Message Lost. This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is reset, this bit is also reset. 0 No Rx FIFO 1 message lost 1 Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero Note: Overwriting the oldest message when RXF1C.F1OM = '1' will not set this flag. |
RO | 0 | ||
| 24 | F1F | Rx FIFO 1 Full 0 Rx FIFO 1 not full 1 Rx FIFO 1 full |
RO | 0 | ||
| 23:22 | RESERVED22 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
| 21:16 | F1PI | Rx FIFO 1 Put Index. Rx FIFO 1 write index pointer, range 0 to 63. | RO | 0b00 0000 | ||
| 15:14 | RESERVED14 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
| 13:8 | F1GI | Rx FIFO 1 Get Index. Rx FIFO 1 read index pointer, range 0 to 63. | RO | 0b00 0000 | ||
| 7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| 6:0 | F1FL | Rx FIFO 1 Fill Level. Number of elements stored in Rx FIFO 1, range 0 to 64. | RO | 0b000 0000 | ||
| Address Offset | 0x0000 00B8 | ||
| Physical Address | 0x400D 00B8 | Instance | 0x400D 00B8 |
| Description | MCAN Rx FIFO 1 Acknowledge | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 | ||
| 5:0 | F1AI | Rx FIFO 1 Acknowledge Index. After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL. | RW | 0b00 0000 | ||
| Address Offset | 0x0000 00BC | ||
| Physical Address | 0x400D 00BC | Instance | 0x400D 00BC |
| Description | Configures the number of data bytes belonging to an Rx Buffer / Rx FIFO element. Data field sizes >8 bytes are intended for CAN FD operation only. | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:11 | RESERVED11 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 | ||
| 10:8 | RBDS | Rx Buffer Data Field Size 000 8 byte data field 001 12 byte data field 010 16 byte data field 011 20 byte data field 100 24 byte data field 101 32 byte data field 110 48 byte data field 111 64 byte data field Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame's data field is ignored. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0b000 | ||
| 7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| 6:4 | F1DS | Rx FIFO 1 Data Field Size 000 8 byte data field 001 12 byte data field 010 16 byte data field 011 20 byte data field 100 24 byte data field 101 32 byte data field 110 48 byte data field 111 64 byte data field Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame's data field is ignored. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0b000 | ||
| 3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| 2:0 | F0DS | Rx FIFO 0 Data Field Size 000 8 byte data field 001 12 byte data field 010 16 byte data field 011 20 byte data field 100 24 byte data field 101 32 byte data field 110 48 byte data field 111 64 byte data field Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame's data field is ignored. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0b000 | ||
| Address Offset | 0x0000 00C0 | ||
| Physical Address | 0x400D 00C0 | Instance | 0x400D 00C0 |
| Description | MCAN Tx Buffer Configuration | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31 | RESERVED31 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| 30 | TFQM | Tx FIFO/Queue Mode 0 Tx FIFO operation 1 Tx Queue operation Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0 | ||
| 29:24 | TFQS | Transmit FIFO/Queue Size 0 No Tx FIFO/Queue 1-32 Number of Tx Buffers used for Tx FIFO/Queue >32 Values greater than 32 are interpreted as 32 Note: Be aware that the sum of TFQS and NDTB may be not greater than 32. There is no check for erroneous configurations. The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0b00 0000 | ||
| 23:22 | RESERVED22 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
| 21:16 | NDTB | Number of Dedicated Transmit Buffers 0 No Dedicated Tx Buffers 1-32 Number of Dedicated Tx Buffers >32 Values greater than 32 are interpreted as 32 Note: Be aware that the sum of TFQS and NDTB may be not greater than 32. There is no check for erroneous configurations. The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0b00 0000 | ||
| 15:2 | TBSA | Tx Buffers Start Address. Start address of Tx Buffers section in Message RAM (32-bit word address). Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0b00 0000 0000 0000 | ||
| 1:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
| Address Offset | 0x0000 00C4 | ||
| Physical Address | 0x400D 00C4 | Instance | 0x400D 00C4 |
| Description | The Tx FIFO/Queue status is related to the pending Tx requests listed in register TXBRP. Therefore the effect of Add/Cancellation requests may be delayed due to a running Tx scan (TXBRP not yet updated). | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:22 | RESERVED22 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 | ||
| 21 | TFQF | Tx FIFO/Queue Full 0 Tx FIFO/Queue not full 1 Tx FIFO/Queue full |
RO | 0 | ||
| 20:16 | TFQP | Tx FIFO/Queue Put Index. Tx FIFO/Queue write index pointer, range 0 to 31. Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indices indicate the number of the Tx Buffer starting with the first dedicated Tx Buffers. Example: For a configuration of 12 dedicated Tx Buffers and a Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO. |
RO | 0b0 0000 | ||
| 15:13 | RESERVED13 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | ||
| 12:8 | TFGI | Tx FIFO Get Index. Tx FIFO read index pointer, range 0 to 31. Read as zero when Tx Queue operation is configured (TXBC.TFQM = '1'). Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indices indicate the number of the Tx Buffer starting with the first dedicated Tx Buffers. Example: For a configuration of 12 dedicated Tx Buffers and a Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO. |
RO | 0b0 0000 | ||
| 7:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
| 5:0 | TFFL | Tx FIFO Free Level. Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 32. Read as zero when Tx Queue operation is configured (TXBC.TFQM = '1'). | RO | 0b00 0000 | ||
| Address Offset | 0x0000 00C8 | ||
| Physical Address | 0x400D 00C8 | Instance | 0x400D 00C8 |
| Description | Configures the number of data bytes belonging to a Tx Buffer element. Data field sizes > 8 bytes are intended for CAN FD operation only. | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 0000 | ||
| 2:0 | TBDS | Tx Buffer Data Field Size 000 8 byte data field 001 12 byte data field 010 16 byte data field 011 20 byte data field 100 24 byte data field 101 32 byte data field 110 48 byte data field 111 64 byte data field Note: In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size TXESC.TBDS, the bytes not defined by the Tx Buffer are transmitted as "0xCC" (padding bytes). Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'. |
RW | 0b000 | ||
| Address Offset | 0x0000 00CC | ||
| Physical Address | 0x400D 00CC | Instance | 0x400D 00CC |
| Description | MCAN Tx Buffer Request Pending | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31 | TRP31 | Transmission Request Pending 31. See description for bit 0. | RO | 0 | ||
| 30 | TRP30 | Transmission Request Pending 30. See description for bit 0. | RO | 0 | ||
| 29 | TRP29 | Transmission Request Pending 29. See description for bit 0. | RO | 0 | ||
| 28 | TRP28 | Transmission Request Pending 28. See description for bit 0. | RO | 0 | ||
| 27 | TRP27 | Transmission Request Pending 27. See description for bit 0. | RO | 0 | ||
| 26 | TRP26 | Transmission Request Pending 26. See description for bit 0. | RO | 0 | ||
| 25 | TRP25 | Transmission Request Pending 25. See description for bit 0. | RO | 0 | ||
| 24 | TRP24 | Transmission Request Pending 24. See description for bit 0. | RO | 0 | ||
| 23 | TRP23 | Transmission Request Pending 23. See description for bit 0. | RO | 0 | ||
| 22 | TRP22 | Transmission Request Pending 22. See description for bit 0. | RO | 0 | ||
| 21 | TRP21 | Transmission Request Pending 21. See description for bit 0. | RO | 0 | ||
| 20 | TRP20 | Transmission Request Pending 20. See description for bit 0. | RO | 0 | ||
| 19 | TRP19 | Transmission Request Pending 19. See description for bit 0. | RO | 0 | ||
| 18 | TRP18 | Transmission Request Pending 18. See description for bit 0. | RO | 0 | ||
| 17 | TRP17 | Transmission Request Pending 17. See description for bit 0. | RO | 0 | ||
| 16 | TRP16 | Transmission Request Pending 16. See description for bit 0. | RO | 0 | ||
| 15 | TRP15 | Transmission Request Pending 15. See description for bit 0. | RO | 0 | ||
| 14 | TRP14 | Transmission Request Pending 14. See description for bit 0. | RO | 0 | ||
| 13 | TRP13 | Transmission Request Pending 13. See description for bit 0. | RO | 0 | ||
| 12 | TRP12 | Transmission Request Pending 12. See description for bit 0. | RO | 0 | ||
| 11 | TRP11 | Transmission Request Pending 11. See description for bit 0. | RO | 0 | ||
| 10 | TRP10 | Transmission Request Pending 10. See description for bit 0. | RO | 0 | ||
| 9 | TRP9 | Transmission Request Pending 9. See description for bit 0. | RO | 0 | ||
| 8 | TRP8 | Transmission Request Pending 8. See description for bit 0. | RO | 0 | ||
| 7 | TRP7 | Transmission Request Pending 7. See description for bit 0. | RO | 0 | ||
| 6 | TRP6 | Transmission Request Pending 6. See description for bit 0. | RO | 0 | ||
| 5 | TRP5 | Transmission Request Pending 5. See description for bit 0. | RO | 0 | ||
| 4 | TRP4 | Transmission Request Pending 4. See description for bit 0. | RO | 0 | ||
| 3 | TRP3 | Transmission Request Pending 3. See description for bit 0. | RO | 0 | ||
| 2 | TRP2 | Transmission Request Pending 2. See description for bit 0. | RO | 0 | ||
| 1 | TRP1 | Transmission Request Pending 1. See description for bit 0. | RO | 0 | ||
| 0 | TRP0 | Transmission Request Pending 0. Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via register TXBAR. The bits are reset after a requested transmission has completed or has been cancelled via register TXBCR. TXBRP bits are set only for those Tx Buffers configured via TXBC. After a TXBRP bit has been set, a Tx scan is started to check for the pending Tx request with the highest priority (Tx Buffer with lowest Message ID). A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. After a cancellation has been requested, a finished cancellation is signalled via TXBCF - after successful transmission together with the corresponding TXBTO bit - when the transmission has not yet been started at the point of cancellation - when the transmission has been aborted due to lost arbitration - when an error occurred during frame transmission In DAR mode all transmissions are automatically cancelled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions. 0 No transmission request pending 1 Transmission request pending Note: TXBRP bits which are set while a Tx scan is in progress are not considered during this particular Tx scan. In case a cancellation is requested for such a Tx Buffer, this Add Request is cancelled immediately, the corresponding TXBRP bit is reset. |
RO | 0 | ||
| Address Offset | 0x0000 00D0 | ||
| Physical Address | 0x400D 00D0 | Instance | 0x400D 00D0 |
| Description | MCAN Tx Buffer Add Request | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31 | AR31 | Add Request 31. See description for bit 0. | RW | 0 | ||
| 30 | AR30 | Add Request 30. See description for bit 0. | RW | 0 | ||
| 29 | AR29 | Add Request 29. See description for bit 0. | RW | 0 | ||
| 28 | AR28 | Add Request 28. See description for bit 0. | RW | 0 | ||
| 27 | AR27 | Add Request 27. See description for bit 0. | RW | 0 | ||
| 26 | AR26 | Add Request 26. See description for bit 0. | RW | 0 | ||
| 25 | AR25 | Add Request 25. See description for bit 0. | RW | 0 | ||
| 24 | AR24 | Add Request 24. See description for bit 0. | RW | 0 | ||
| 23 | AR23 | Add Request 23. See description for bit 0. | RW | 0 | ||
| 22 | AR22 | Add Request 22. See description for bit 0. | RW | 0 | ||
| 21 | AR21 | Add Request 21. See description for bit 0. | RW | 0 | ||
| 20 | AR20 | Add Request 20. See description for bit 0. | RW | 0 | ||
| 19 | AR19 | Add Request 19. See description for bit 0. | RW | 0 | ||
| 18 | AR18 | Add Request 18. See description for bit 0. | RW | 0 | ||
| 17 | AR17 | Add Request 17. See description for bit 0. | RW | 0 | ||
| 16 | AR16 | Add Request 16. See description for bit 0. | RW | 0 | ||
| 15 | AR15 | Add Request 15. See description for bit 0. | RW | 0 | ||
| 14 | AR14 | Add Request 14. See description for bit 0. | RW | 0 | ||
| 13 | AR13 | Add Request 13. See description for bit 0. | RW | 0 | ||
| 12 | AR12 | Add Request 12. See description for bit 0. | RW | 0 | ||
| 11 | AR11 | Add Request 11. See description for bit 0. | RW | 0 | ||
| 10 | AR10 | Add Request 10. See description for bit 0. | RW | 0 | ||
| 9 | AR9 | Add Request 9. See description for bit 0. | RW | 0 | ||
| 8 | AR8 | Add Request 8. See description for bit 0. | RW | 0 | ||
| 7 | AR7 | Add Request 7. See description for bit 0. | RW | 0 | ||
| 6 | AR6 | Add Request 6. See description for bit 0. | RW | 0 | ||
| 5 | AR5 | Add Request 5. See description for bit 0. | RW | 0 | ||
| 4 | AR4 | Add Request 4. See description for bit 0. | RW | 0 | ||
| 3 | AR3 | Add Request 3. See description for bit 0. | RW | 0 | ||
| 2 | AR2 | Add Request 2. See description for bit 0. | RW | 0 | ||
| 1 | AR1 | Add Request 1. See description for bit 0. | RW | 0 | ||
| 0 | AR0 | Add Request 0. Each Tx Buffer has its own Add Request bit. Writing a '1' will set the corresponding Add Request bit; writing a '0' has no impact. This enables the Host to set transmission requests for multiple Tx Buffers with one write to TXBAR. TXBAR bits are set only for those Tx Buffers configured via TXBC. When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed. 0 No transmission request added 1 Transmission requested added Note: If an add request is applied for a Tx Buffer with pending transmission request (corresponding TXBRP bit already set), this add request is ignored. Qualified Write is possible only with CCCR.CCE='0' |
RW | 0 | ||
| Address Offset | 0x0000 00D4 | ||
| Physical Address | 0x400D 00D4 | Instance | 0x400D 00D4 |
| Description | MCAN Tx Buffer Cancellation Request | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31 | CR31 | Cancellation Request 31. See description for bit 0. | RW | 0 | ||
| 30 | CR30 | Cancellation Request 30. See description for bit 0. | RW | 0 | ||
| 29 | CR29 | Cancellation Request 29. See description for bit 0. | RW | 0 | ||
| 28 | CR28 | Cancellation Request 28. See description for bit 0. | RW | 0 | ||
| 27 | CR27 | Cancellation Request 27. See description for bit 0. | RW | 0 | ||
| 26 | CR26 | Cancellation Request 26. See description for bit 0. | RW | 0 | ||
| 25 | CR25 | Cancellation Request 25. See description for bit 0. | RW | 0 | ||
| 24 | CR24 | Cancellation Request 24. See description for bit 0. | RW | 0 | ||
| 23 | CR23 | Cancellation Request 23. See description for bit 0. | RW | 0 | ||
| 22 | CR22 | Cancellation Request 22. See description for bit 0. | RW | 0 | ||
| 21 | CR21 | Cancellation Request 21. See description for bit 0. | RW | 0 | ||
| 20 | CR20 | Cancellation Request 20. See description for bit 0. | RW | 0 | ||
| 19 | CR19 | Cancellation Request 19. See description for bit 0. | RW | 0 | ||
| 18 | CR18 | Cancellation Request 18. See description for bit 0. | RW | 0 | ||
| 17 | CR17 | Cancellation Request 17. See description for bit 0. | RW | 0 | ||
| 16 | CR16 | Cancellation Request 16. See description for bit 0. | RW | 0 | ||
| 15 | CR15 | Cancellation Request 15. See description for bit 0. | RW | 0 | ||
| 14 | CR14 | Cancellation Request 14. See description for bit 0. | RW | 0 | ||
| 13 | CR13 | Cancellation Request 13. See description for bit 0. | RW | 0 | ||
| 12 | CR12 | Cancellation Request 12. See description for bit 0. | RW | 0 | ||
| 11 | CR11 | Cancellation Request 11. See description for bit 0. | RW | 0 | ||
| 10 | CR10 | Cancellation Request 10. See description for bit 0. | RW | 0 | ||
| 9 | CR9 | Cancellation Request 9. See description for bit 0. | RW | 0 | ||
| 8 | CR8 | Cancellation Request 8. See description for bit 0. | RW | 0 | ||
| 7 | CR7 | Cancellation Request 7. See description for bit 0. | RW | 0 | ||
| 6 | CR6 | Cancellation Request 6. See description for bit 0. | RW | 0 | ||
| 5 | CR5 | Cancellation Request 5. See description for bit 0. | RW | 0 | ||
| 4 | CR4 | Cancellation Request 4. See description for bit 0. | RW | 0 | ||
| 3 | CR3 | Cancellation Request 3. See description for bit 0. | RW | 0 | ||
| 2 | CR2 | Cancellation Request 2. See description for bit 0. | RW | 0 | ||
| 1 | CR1 | Cancellation Request 1. See description for bit 0. | RW | 0 | ||
| 0 | CR0 | Cancellation Request 0. Each Tx Buffer has its own Cancellation Request bit. Writing a '1' will set the corresponding Cancellation Request bit; writing a '0' has no impact. This enables the Host to set cancellation requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset. 0 No cancellation pending 1 Cancellation pending Qualified Write is possible only with CCCR.CCE='0' |
RW | 0 | ||
| Address Offset | 0x0000 00D8 | ||
| Physical Address | 0x400D 00D8 | Instance | 0x400D 00D8 |
| Description | MCAN Tx Buffer Transmission Occurred | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31 | TO31 | Transmission Occurred 31. See description for bit 0. | RO | 0 | ||
| 30 | TO30 | Transmission Occurred 30. See description for bit 0. | RO | 0 | ||
| 29 | TO29 | Transmission Occurred 29. See description for bit 0. | RO | 0 | ||
| 28 | TO28 | Transmission Occurred 28. See description for bit 0. | RO | 0 | ||
| 27 | TO27 | Transmission Occurred 27. See description for bit 0. | RO | 0 | ||
| 26 | TO26 | Transmission Occurred 26. See description for bit 0. | RO | 0 | ||
| 25 | TO25 | Transmission Occurred 25. See description for bit 0. | RO | 0 | ||
| 24 | TO24 | Transmission Occurred 24. See description for bit 0. | RO | 0 | ||
| 23 | TO23 | Transmission Occurred 23. See description for bit 0. | RO | 0 | ||
| 22 | TO22 | Transmission Occurred 22. See description for bit 0. | RO | 0 | ||
| 21 | TO21 | Transmission Occurred 21. See description for bit 0. | RO | 0 | ||
| 20 | TO20 | Transmission Occurred 20. See description for bit 0. | RO | 0 | ||
| 19 | TO19 | Transmission Occurred 19. See description for bit 0. | RO | 0 | ||
| 18 | TO18 | Transmission Occurred 18. See description for bit 0. | RO | 0 | ||
| 17 | TO17 | Transmission Occurred 17. See description for bit 0. | RO | 0 | ||
| 16 | TO16 | Transmission Occurred 16. See description for bit 0. | RO | 0 | ||
| 15 | TO15 | Transmission Occurred 15. See description for bit 0. | RO | 0 | ||
| 14 | TO14 | Transmission Occurred 14. See description for bit 0. | RO | 0 | ||
| 13 | TO13 | Transmission Occurred 13. See description for bit 0. | RO | 0 | ||
| 12 | TO12 | Transmission Occurred 12. See description for bit 0. | RO | 0 | ||
| 11 | TO11 | Transmission Occurred 11. See description for bit 0. | RO | 0 | ||
| 10 | TO10 | Transmission Occurred 10. See description for bit 0. | RO | 0 | ||
| 9 | TO9 | Transmission Occurred 9. See description for bit 0. | RO | 0 | ||
| 8 | TO8 | Transmission Occurred 8. See description for bit 0. | RO | 0 | ||
| 7 | TO7 | Transmission Occurred 7. See description for bit 0. | RO | 0 | ||
| 6 | TO6 | Transmission Occurred 6. See description for bit 0. | RO | 0 | ||
| 5 | TO5 | Transmission Occurred 5. See description for bit 0. | RO | 0 | ||
| 4 | TO4 | Transmission Occurred 4. See description for bit 0. | RO | 0 | ||
| 3 | TO3 | Transmission Occurred 3. See description for bit 0. | RO | 0 | ||
| 2 | TO2 | Transmission Occurred 2. See description for bit 0. | RO | 0 | ||
| 1 | TO1 | Transmission Occurred 1. See description for bit 0. | RO | 0 | ||
| 0 | TO0 | Transmission Occurred 0. Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a '1' to the corresponding bit of register TXBAR. 0 No transmission occurred 1 Transmission occurred |
RO | 0 | ||
| Address Offset | 0x0000 00DC | ||
| Physical Address | 0x400D 00DC | Instance | 0x400D 00DC |
| Description | MCAN Tx Buffer Cancellation Finished | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31 | CF31 | Cancellation Finished 31. See description for bit 0. | RO | 0 | ||
| 30 | CF30 | Cancellation Finished 30. See description for bit 0. | RO | 0 | ||
| 29 | CF29 | Cancellation Finished 29. See description for bit 0. | RO | 0 | ||
| 28 | CF28 | Cancellation Finished 28. See description for bit 0. | RO | 0 | ||
| 27 | CF27 | Cancellation Finished 27. See description for bit 0. | RO | 0 | ||
| 26 | CF26 | Cancellation Finished 26. See description for bit 0. | RO | 0 | ||
| 25 | CF25 | Cancellation Finished 25. See description for bit 0. | RO | 0 | ||
| 24 | CF24 | Cancellation Finished 24. See description for bit 0. | RO | 0 | ||
| 23 | CF23 | Cancellation Finished 23. See description for bit 0. | RO | 0 | ||
| 22 | CF22 | Cancellation Finished 22. See description for bit 0. | RO | 0 | ||
| 21 | CF21 | Cancellation Finished 21. See description for bit 0. | RO | 0 | ||
| 20 | CF20 | Cancellation Finished 20. See description for bit 0. | RO | 0 | ||
| 19 | CF19 | Cancellation Finished 19. See description for bit 0. | RO | 0 | ||
| 18 | CF18 | Cancellation Finished 18. See description for bit 0. | RO | 0 | ||
| 17 | CF17 | Cancellation Finished 17. See description for bit 0. | RO | 0 | ||
| 16 | CF16 | Cancellation Finished 16. See description for bit 0. | RO | 0 | ||
| 15 | CF15 | Cancellation Finished 15. See description for bit 0. | RO | 0 | ||
| 14 | CF14 | Cancellation Finished 14. See description for bit 0. | RO | 0 | ||
| 13 | CF13 | Cancellation Finished 13. See description for bit 0. | RO | 0 | ||
| 12 | CF12 | Cancellation Finished 12. See description for bit 0. | RO | 0 | ||
| 11 | CF11 | Cancellation Finished 11. See description for bit 0. | RO | 0 | ||
| 10 | CF10 | Cancellation Finished 10. See description for bit 0. | RO | 0 | ||
| 9 | CF9 | Cancellation Finished 9. See description for bit 0. | RO | 0 | ||
| 8 | CF8 | Cancellation Finished 8. See description for bit 0. | RO | 0 | ||
| 7 | CF7 | Cancellation Finished 7. See description for bit 0. | RO | 0 | ||
| 6 | CF6 | Cancellation Finished 6. See description for bit 0. | RO | 0 | ||
| 5 | CF5 | Cancellation Finished 5. See description for bit 0. | RO | 0 | ||
| 4 | CF4 | Cancellation Finished 4. See description for bit 0. | RO | 0 | ||
| 3 | CF3 | Cancellation Finished 3. See description for bit 0. | RO | 0 | ||
| 2 | CF2 | Cancellation Finished 2. See description for bit 0. | RO | 0 | ||
| 1 | CF1 | Cancellation Finished 1. See description for bit 0. | RO | 0 | ||
| 0 | CF0 | Cancellation Finished 0. Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a '1' to the corresponding bit of register TXBAR. 0 No transmit buffer cancellation 1 Transmit buffer cancellation finished |
RO | 0 | ||
| Address Offset | 0x0000 00E0 | ||
| Physical Address | 0x400D 00E0 | Instance | 0x400D 00E0 |
| Description | MCAN Tx Buffer Transmission Interrupt Enable | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31 | TIE31 | Transmission Interrupt Enable 31. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable |
RW | 0 | ||
| 30 | TIE30 | Transmission Interrupt Enable 30. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable |
RW | 0 | ||
| 29 | TIE29 | Transmission Interrupt Enable 29. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable |
RW | 0 | ||
| 28 | TIE28 | Transmission Interrupt Enable 28. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable |
RW | 0 | ||
| 27 | TIE27 | Transmission Interrupt Enable 27. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable |
RW | 0 | ||
| 26 | TIE26 | Transmission Interrupt Enable 26. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable |
RW | 0 | ||
| 25 | TIE25 | Transmission Interrupt Enable 25. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable |
RW | 0 | ||
| 24 | TIE24 | Transmission Interrupt Enable 24. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable |
RW | 0 | ||
| 23 | TIE23 | Transmission Interrupt Enable 23. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable |
RW | 0 | ||
| 22 | TIE22 | Transmission Interrupt Enable 22. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable |
RW | 0 | ||
| 21 | TIE21 | Transmission Interrupt Enable 21. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable |
RW | 0 | ||
| 20 | TIE20 | Transmission Interrupt Enable 20. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable |
RW | 0 | ||
| 19 | TIE19 | Transmission Interrupt Enable 19. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable |
RW | 0 | ||
| 18 | TIE18 | Transmission Interrupt Enable 18. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable |
RW | 0 | ||
| 17 | TIE17 | Transmission Interrupt Enable 17. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable |
RW | 0 | ||
| 16 | TIE16 | Transmission Interrupt Enable 16. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable |
RW | 0 | ||
| 15 | TIE15 | Transmission Interrupt Enable 15. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable |
RW | 0 | ||
| 14 | TIE14 | Transmission Interrupt Enable 14. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable |
RW | 0 | ||
| 13 | TIE13 | Transmission Interrupt Enable 13. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable |
RW | 0 | ||
| 12 | TIE12 | Transmission Interrupt Enable 12. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable |
RW | 0 | ||
| 11 | TIE11 | Transmission Interrupt Enable 11. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable |
RW | 0 | ||
| 10 | TIE10 | Transmission Interrupt Enable 10. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable |
RW | 0 | ||
| 9 | TIE9 | Transmission Interrupt Enable 9. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable |
RW | 0 | ||
| 8 | TIE8 | Transmission Interrupt Enable 8. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable |
RW | 0 | ||
| 7 | TIE7 | Transmission Interrupt Enable 7. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable |
RW | 0 | ||
| 6 | TIE6 | Transmission Interrupt Enable 6. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable |
RW | 0 | ||
| 5 | TIE5 | Transmission Interrupt Enable 5. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable |
RW | 0 | ||
| 4 | TIE4 | Transmission Interrupt Enable 4. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable |
RW | 0 | ||
| 3 | TIE3 | Transmission Interrupt Enable 3. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable |
RW | 0 | ||
| 2 | TIE2 | Transmission Interrupt Enable 2. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable |
RW | 0 | ||
| 1 | TIE1 | Transmission Interrupt Enable 1. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable |
RW | 0 | ||
| 0 | TIE0 | Transmission Interrupt Enable 0. Each Tx Buffer has its own Transmission Interrupt Enable bit. 0 Transmission interrupt disabled 1 Transmission interrupt enable |
RW | 0 | ||
| Address Offset | 0x0000 00E4 | ||
| Physical Address | 0x400D 00E4 | Instance | 0x400D 00E4 |
| Description | MCAN Tx Buffer Cancellation Finished Interrupt Enable | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31 | CFIE31 | Cancellation Finished Interrupt Enable 31. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled |
RW | 0 | ||
| 30 | CFIE30 | Cancellation Finished Interrupt Enable 30. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled |
RW | 0 | ||
| 29 | CFIE29 | Cancellation Finished Interrupt Enable 29. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled |
RW | 0 | ||
| 28 | CFIE28 | Cancellation Finished Interrupt Enable 28. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled |
RW | 0 | ||
| 27 | CFIE27 | Cancellation Finished Interrupt Enable 27. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled |
RW | 0 | ||
| 26 | CFIE26 | Cancellation Finished Interrupt Enable 26. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled |
RW | 0 | ||
| 25 | CFIE25 | Cancellation Finished Interrupt Enable 25. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled |
RW | 0 | ||
| 24 | CFIE24 | Cancellation Finished Interrupt Enable 24. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled |
RW | 0 | ||
| 23 | CFIE23 | Cancellation Finished Interrupt Enable 23. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled |
RW | 0 | ||
| 22 | CFIE22 | Cancellation Finished Interrupt Enable 22. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled |
RW | 0 | ||
| 21 | CFIE21 | Cancellation Finished Interrupt Enable 21. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled |
RW | 0 | ||
| 20 | CFIE20 | Cancellation Finished Interrupt Enable 20. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled |
RW | 0 | ||
| 19 | CFIE19 | Cancellation Finished Interrupt Enable 19. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled |
RW | 0 | ||
| 18 | CFIE18 | Cancellation Finished Interrupt Enable 18. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled |
RW | 0 | ||
| 17 | CFIE17 | Cancellation Finished Interrupt Enable 17. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled |
RW | 0 | ||
| 16 | CFIE16 | Cancellation Finished Interrupt Enable 16. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled |
RW | 0 | ||
| 15 | CFIE15 | Cancellation Finished Interrupt Enable 15. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled |
RW | 0 | ||
| 14 | CFIE14 | Cancellation Finished Interrupt Enable 14. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled |
RW | 0 | ||
| 13 | CFIE13 | Cancellation Finished Interrupt Enable 13. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled |
RW | 0 | ||
| 12 | CFIE12 | Cancellation Finished Interrupt Enable 12. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled |
RW | 0 | ||
| 11 | CFIE11 | Cancellation Finished Interrupt Enable 11. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled |
RW | 0 | ||
| 10 | CFIE10 | Cancellation Finished Interrupt Enable 10. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled |
RW | 0 | ||
| 9 | CFIE9 | Cancellation Finished Interrupt Enable 9. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled |
RW | 0 | ||
| 8 | CFIE8 | Cancellation Finished Interrupt Enable 8. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled |
RW | 0 | ||
| 7 | CFIE7 | Cancellation Finished Interrupt Enable 7. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled |
RW | 0 | ||
| 6 | CFIE6 | Cancellation Finished Interrupt Enable 6. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled |
RW | 0 | ||
| 5 | CFIE5 | Cancellation Finished Interrupt Enable 5. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled |
RW | 0 | ||
| 4 | CFIE4 | Cancellation Finished Interrupt Enable 4. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled |
RW | 0 | ||
| 3 | CFIE3 | Cancellation Finished Interrupt Enable 3. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled |
RW | 0 | ||
| 2 | CFIE2 | Cancellation Finished Interrupt Enable 2. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled |
RW | 0 | ||
| 1 | CFIE1 | Cancellation Finished Interrupt Enable 1. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled |
RW | 0 | ||
| 0 | CFIE0 | Cancellation Finished Interrupt Enable 0. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0 Cancellation finished interrupt disabled 1 Cancellation finished interrupt enabled |
RW | 0 | ||
| Address Offset | 0x0000 00F0 | ||
| Physical Address | 0x400D 00F0 | Instance | 0x400D 00F0 |
| Description | MCAN Tx Event FIFO Configuration | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:30 | RESERVED30 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
| 29:24 | EFWM | Event FIFO Watermark 0 Watermark interrupt disabled 1-32 Level for Tx Event FIFO watermark interrupt (IR.TEFW) >32 Watermark interrupt disabled |
RW | 0b00 0000 | ||
| 23:22 | RESERVED22 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
| 21:16 | EFS | Event FIFO Size. The Tx Event FIFO elements are indexed from 0 to EFS - 1. 0 Tx Event FIFO disabled 1-32 Number of Tx Event FIFO elements >32 Values greater than 32 are interpreted as 32 |
RW | 0b00 0000 | ||
| 15:2 | EFSA | Event FIFO Start Address. Start address of Tx Event FIFO in Message RAM (32-bit word address). | RW | 0b00 0000 0000 0000 | ||
| 1:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
| Address Offset | 0x0000 00F4 | ||
| Physical Address | 0x400D 00F4 | Instance | 0x400D 00F4 |
| Description | MCAN Tx Event FIFO Status | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:26 | RESERVED26 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 | ||
| 25 | TEFL | Tx Event FIFO Element Lost. This bit is a copy of interrupt flag IR.TEFL. When IR.TEFL is reset, this bit is also reset. 0 No Tx Event FIFO element lost 1 Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero. |
RO | 0 | ||
| 24 | EFF | Event FIFO Full 0 Tx Event FIFO not full 1 Tx Event FIFO full |
RO | 0 | ||
| 23:21 | RESERVED21 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | ||
| 20:16 | EFPI | Event FIFO Put Index.Tx Event FIFO write index pointer, range 0 to 31. | RO | 0b0 0000 | ||
| 15:13 | RESERVED13 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | ||
| 12:8 | EFGI | Event FIFO Get Index. Tx Event FIFO read index pointer, range 0 to 31. | RO | 0b0 0000 | ||
| 7:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
| 5:0 | EFFL | Event FIFO Fill Level. Number of elements stored in Tx Event FIFO, range 0 to 32. | RO | 0b00 0000 | ||
| Address Offset | 0x0000 00F8 | ||
| Physical Address | 0x400D 00F8 | Instance | 0x400D 00F8 |
| Description | MCAN Tx Event FIFO Acknowledge | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 | ||
| 4:0 | EFAI | Event FIFO Acknowledge Index. After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get Index TXEFS.EFGI to EFAI + 1 and update the Event FIFO Fill Level TXEFS.EFFL. | RW | 0b0 0000 | ||
| Address Offset | 0x0000 0200 | ||
| Physical Address | 0x400D 0200 | Instance | 0x400D 0200 |
| Description | MCAN Subsystem Revision Register | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:30 | SCHEME | PID Register Scheme | RO | 0b01 | ||
| 29:28 | BU | Business Unit: 0x2 = Processors | RO | 0b10 | ||
| 27:16 | MODULE_ID | Module Identification Number | RO | 0x8E0 | ||
| 15:11 | RTL | RTL revision. Will vary depending on release | RO | 0b0 1001 | ||
| 10:8 | MAJOR | Major Revision of the MCAN Subsystem | RO | 0b001 | ||
| 7:6 | CUSTOM | Custom Value | RO | 0b00 | ||
| 5:0 | MINOR | Minor Revision of the MCAN Subsystem | RO | 0b00 0001 | ||
| Address Offset | 0x0000 0204 | ||
| Physical Address | 0x400D 0204 | Instance | 0x400D 0204 |
| Description | MCAN Subsystem Control Register | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||
| 6 | EXT_TS_CNTR_EN | External Timestamp Counter Enable. 0 External timestamp counter disabled 1 External timestamp counter enabled |
RW | 0 | ||
| 5 | AUTOWAKEUP | Automatic Wakeup Enable. Enables the MCANSS to automatically clear the MCAN CCCR.INIT bit, fully waking the MCAN up, on an enabled wakeup request. 0 Disable the automatic write to CCCR.INIT 1 Enable the automatic write to CCCR.INIT |
RW | 0 | ||
| 4 | WAKEUPREQEN | Wakeup Request Enable. Enables the MCANSS to wakeup on CAN RXD activity. 0 Disable wakeup request 1 Enables wakeup request |
RW | 0 | ||
| 3 | DBGSUSP_FREE | Debug Suspend Free Bit. Enables debug suspend. 0 Disable debug suspend 1 Enable debug suspend |
RW | 1 | ||
| 2:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | ||
| Address Offset | 0x0000 0208 | ||
| Physical Address | 0x400D 0208 | Instance | 0x400D 0208 |
| Description | MCAN Subsystem Status Register | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 0000 | ||
| 2 | ENABLE_FDOE | Flexible Datarate Operation Enable. Determines whether CAN FD operation can be enabled via the MCAN core CCCR.FDOE bit (bit 8) or if only standard CAN operation is possible with this instance of the MCAN. 0 MCAN is only capable of standard CAN communication 1 MCAN may be configured to perform CAN FD communication |
RO | 0 | ||
| 1 | MEM_INIT_DONE | Memory Initialization Done. 0 Message RAM initialization is in progress 1 Message RAM is initialized for use |
RO | 0 | ||
| 0 | RESET | Soft Reset Status. 0 Not in reset 1 Reset is in progress |
RO | 0 | ||
| Address Offset | 0x0000 020C | ||
| Physical Address | 0x400D 020C | Instance | 0x400D 020C |
| Description | MCAN Subsystem Interrupt Clear Shadow Register | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
| 0 | EXT_TS_CNTR_OVFL | External Timestamp Counter Overflow Interrupt Status Clear. Reads always return a 0. 0 Write of '0' has no effect 1 Write of '1' clears the MCANSS_IRS.EXT_TS_CNTR_OVFL bit |
RW | 0 | ||
| Address Offset | 0x0000 0210 | ||
| Physical Address | 0x400D 0210 | Instance | 0x400D 0210 |
| Description | MCAN Subsystem Interrupt Raw Satus Register | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
| 0 | EXT_TS_CNTR_OVFL | External Timestamp Counter Overflow Interrupt Status. This bit is set by HW or by a SW write of '1'. To clear, use the MCANSS_ICS.EXT_TS_CNTR_OVFL bit. 0 External timestamp counter has not overflowed 1 External timestamp counter has overflowed When this bit is set to '1' by HW or SW, the MCANSS_EXT_TS_UNSERVICED_INTR_CNTR.EXT_TS_INTR_CNTR bit field will increment by 1. |
RW | 0 | ||
| Address Offset | 0x0000 0214 | ||
| Physical Address | 0x400D 0214 | Instance | 0x400D 0214 |
| Description | MCAN Subsystem Interrupt Enable Clear Shadow Register | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
| 0 | EXT_TS_CNTR_OVFL | External Timestamp Counter Overflow Interrupt Enable Clear. Reads always return a 0. 0 Write of '0' has no effect 1 Write of '1' clears the MCANSS_IES.EXT_TS_CNTR_OVFL bit |
RW | 0 | ||
| Address Offset | 0x0000 0218 | ||
| Physical Address | 0x400D 0218 | Instance | 0x400D 0218 |
| Description | MCAN Subsystem Interrupt Enable Register | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
| 0 | EXT_TS_CNTR_OVFL | External Timestamp Counter Overflow Interrupt Enable. A write of '0' has no effect. A write of '1' sets the MCANSS_IES.EXT_TS_CNTR_OVFL bit. | RW | 0 | ||
| Address Offset | 0x0000 021C | ||
| Physical Address | 0x400D 021C | Instance | 0x400D 021C |
| Description | MCAN Subsystem Masked Interrupt Status. It is the logical AND of IRS and IE for the respecitve bits. | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
| 0 | EXT_TS_CNTR_OVFL | External Timestamp Counter Overflow masked interrupt status. 0 External timestamp counter overflow interrupt is cleared 1 External timestamp counter overflow interrupt is set |
RO | 0 | ||
| Address Offset | 0x0000 0220 | ||
| Physical Address | 0x400D 0220 | Instance | 0x400D 0220 |
| Description | MCAN Subsystem End of Interrupt | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:0 | EOI | End of Interrupt. A write to this register will clear the associated interrupt. If the unserviced interrupt counter is > 1, another interrupt is generated. 0x00 External TS Interrupt is cleared 0x01 MCAN(0) interrupt is cleared 0x02 MCAN(1) interrupt is cleared Other writes are ignored. |
RW | 0x00 | ||
| Address Offset | 0x0000 0224 | ||
| Physical Address | 0x400D 0224 | Instance | 0x400D 0224 |
| Description | MCAN Subsystem External Timestamp Prescaler 0 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 | ||
| 23:0 | PRESCALER | External Timestamp Prescaler Reload Value. The external timestamp count rate is the host (system) clock rate divided by this value, except in the case of 0. A zero value in this bit field will act identically to a value of 0x000001. | RW | 0x00 0000 | ||
| Address Offset | 0x0000 0228 | ||
| Physical Address | 0x400D 0228 | Instance | 0x400D 0228 |
| Description | MCAN Subsystem External Timestamp Unserviced Interrupts Counter | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 | ||
| 4:0 | EXT_TS_INTR_CNTR | External Timestamp Counter Unserviced Rollover Interrupts. If this value is > 1, an MCANSS_EOI write of '1' to bit 0 will issue another interrupt. The status of this bit field is affected by the MCANSS_IRS.EXT_TS_CNTR_OVFL bit field. |
RO | 0b0 0000 | ||
| Address Offset | 0x0000 0400 | ||
| Physical Address | 0x400D 0400 | Instance | 0x400D 0400 |
| Description | MCAN Error Aggregator Revision Register | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:30 | SCHEME | PID Register Scheme | RO | 0b01 | ||
| 29:28 | BU | Business Unit: 0x2 = Processors | RO | 0b10 | ||
| 27:16 | MODULE_ID | Module Identification Number | RO | 0x6A0 | ||
| 15:11 | REVRTL | RTL revision. Will vary depending on release | RO | 0b1 1101 | ||
| 10:8 | REVMAJ | Major Revision of the Error Aggregator | RO | 0b010 | ||
| 7:6 | REVCUSTOM | Custom Revision of the Error Aggregator | RO | 0b00 | ||
| 5:0 | REVMIN | Minor Revision of the Error Aggregator | RO | 0b00 0000 | ||
| Address Offset | 0x0000 0408 | ||
| Physical Address | 0x400D 0408 | Instance | 0x400D 0408 |
| Description | Each error detection and correction (EDC) controller has a bank of error registers (offsets 0x10 - 0x3B) associated with it. These registers are accessed via an internal serial bus (SVBUS). To access them through the ECC aggregator the controller ID desired must be written to the ECC_VECTOR field, together with the RD_SVBUS trigger and RD_SVBUS_ADDRESS bit field. This initiates the serial read which consummates by setting the RD_SVBUS_DONE bit. At this point the addressed register may be read by a normal CPU read of the appropriate offset address. | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:25 | RESERVED25 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 | ||
| 24 | RD_SVBUS_DONE | Read Completion Flag | RO | 0 | ||
| 23:16 | RD_SVBUS_ADDRESS | Read Address Offset | RW | 0x00 | ||
| 15 | RD_SVBUS | Read Trigger | RW | 0 | ||
| 14:11 | RESERVED11 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 | ||
| 10:0 | ECC_VECTOR | ECC RAM ID. Each error detection and correction (EDC) controller has a bank of error registers (offsets 0x10 - 0x3B) associated with it. These registers are accessed via an internal serial bus (SVBUS). To access them through the ECC aggregator the controller ID desired must be written to the ECC_VECTOR field, together with the RD_SVBUS trigger and RD_SVBUS_ADDRESS bit field. This initiates the serial read which consummates by setting the RD_SVBUS_DONE bit. At this point the addressed register may be read by a normal CPU read of the appropriate offset address. 0x000 Message RAM ECC controller is selected Others Reserved (do not use) Subsequent writes through the SVBUS (offsets 0x10 - 0x3B) have a delayed completion. To avoid conflicts, perform a read back of a register within this range after writing. |
RW | 0b000 0000 0000 | ||
| Address Offset | 0x0000 040C | ||
| Physical Address | 0x400D 040C | Instance | 0x400D 040C |
| Description | MCAN Error Misc Status | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:11 | RESERVED11 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 | ||
| 10:0 | NUM_RAMS | Number of RAMs. Number of ECC RAMs serviced by the aggregator. | RO | 0b000 0000 0010 | ||
| Address Offset | 0x0000 0410 | ||
| Physical Address | 0x400D 0410 | Instance | 0x400D 0410 |
| Description | This register is accessed through the ECC aggregator via an internal serial bus. To access, the appropriate procedure must be first followed in the MCAN ECC Vector Register. | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:30 | SCHEME | PID Register Scheme | RO | 0b01 | ||
| 29:28 | BU | Business Unit: 0x2 = Processors | RO | 0b10 | ||
| 27:16 | MODULE_ID | Module Identification Number | RO | 0x6A4 | ||
| 15:11 | REVRTL | RTL revision. Will vary depending on release | RO | 0b0 1101 | ||
| 10:8 | REVMAJ | Major Revision of the Error Aggregator | RO | 0b010 | ||
| 7:6 | REVCUSTOM | Custom Revision of the Error Aggregator | RO | 0b00 | ||
| 5:0 | REVMIN | Minor Revision of the Error Aggregator | RO | 0b00 0010 | ||
| Address Offset | 0x0000 0414 | ||
| Physical Address | 0x400D 0414 | Instance | 0x400D 0414 |
| Description | This register is accessed through the ECC aggregator via an internal serial bus. To access, the appropriate procedure must be first followed in the MCAN ECC Vector Register. | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 | ||
| 8 | CHECK_SVBUS_TIMEOUT | Enables Serial VBUS timeout mechanism | RW | 1 | ||
| 7 | CHECK_PARITY | Enables parity checking on internal data | RW | 1 | ||
| 6 | ERROR_ONCE | If this bit is set, the FORCE_SEC/FORCE_DED will inject an error to the specified row only once. The FORCE_SEC bit will be cleared once a writeback happens. If writeback is not enabled, this error will be cleared the cycle following the read when the data is corrected. For double-bit errors, the FORCE_DED bit will be cleared the cycle following the double-bit error. Any subsequent reads will not force an error. | RW | 0 | ||
| 5 | FORCE_N_ROW | Enable single/double-bit error on the next RAM read, regardless of the MCANERR_ERR_CTRL1.ECC_ROW setting. For write through mode, this applies to writes as well as reads. | RW | 0 | ||
| 4 | FORCE_DED | Force double-bit error. Cleared the cycle following the error if ERROR_ONCE is asserted. For write through mode, this applies to writes as well as reads. MCANERR_ERR_CTRL1 and MCANERR_ERR_CTRL2 should be configured prior to setting this bit. | RW | 0 | ||
| 3 | FORCE_SEC | Force single-bit error. Cleared on a writeback or the cycle following the error if ERROR_ONCE is asserted. For write through mode, this applies to writes as well as reads. MCANERR_ERR_CTRL1 and MCANERR_ERR_CTRL2 should be configured prior to setting this bit. | RW | 0 | ||
| 2 | ENABLE_RMW | Enable read-modify-write on partial word writes | RW | 1 | ||
| 1 | ECC_CHECK | Enable ECC Check. ECC is completely bypassed if both ECC_ENABLE and ECC_CHECK are '0'. | RW | 1 | ||
| 0 | ECC_ENABLE | Enable ECC Generation | RW | 1 | ||
| Address Offset | 0x0000 0418 | ||
| Physical Address | 0x400D 0418 | Instance | 0x400D 0418 |
| Description | This register is accessed through the ECC aggregator via an internal serial bus. To access, the appropriate procedure must be first followed in the MCAN ECC Vector Register. | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | ECC_ROW | Row address where FORCE_SEC or FORCE_DED needs to be applied. This is ignored if FORCE_N_ROW is set. | RW | 0x0000 0000 | ||
| Address Offset | 0x0000 041C | ||
| Physical Address | 0x400D 041C | Instance | 0x400D 041C |
| Description | This register is accessed through the ECC aggregator via an internal serial bus. To access, the appropriate procedure must be first followed in the MCAN ECC Vector Register. | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:16 | ECC_BIT2 | Second column/data bit that needs to be flipped when FORCE_DED is set | RW | 0x0000 | ||
| 15:0 | ECC_BIT1 | Column/Data bit that needs to be flipped when FORCE_SEC or FORCE_DED is set | RW | 0x0000 | ||
| Address Offset | 0x0000 0420 | ||
| Physical Address | 0x400D 0420 | Instance | 0x400D 0420 |
| Description | This register is accessed through the ECC aggregator via an internal serial bus. To access, the appropriate procedure must be first followed in the MCAN ECC Vector Register. | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:16 | ECC_BIT1 | ECC Error Bit Position. Indicates the bit position in the RAM data that is in error on an SEC error. Only valid on an SEC error. 0 Bit 0 is in error 1 Bit 1 is in error 2 Bit 2 is in error 3 Bit 3 is in error ... 31 Bit 31 is in error >32 Invalid |
RO | 0x0000 | ||
| 15 | CLR_CTRL_REG_ERROR | Writing a '1' clears the CTRL_REG_ERROR bit | RW | 0 | ||
| 14:13 | CLR_PARITY_ERROR | Clear Parity Error. A write of a non-zero value to this bit field decrements the PARITY_ERROR bit field by the value provided. | RW | 0b00 | ||
| 12 | CLR_ECC_OTHER | Writing a '1' clears the ECC_OTHER bit. | RW | 0 | ||
| 11:10 | CLR_ECC_DED | Clear ECC_DED. A write of a non-zero value to this bit field decrements the ECC_DED bit field by the value provided. | RW | 0b00 | ||
| 9:8 | CLR_ECC_SEC | Clear ECC_SEC. A write of a non-zero value to this bit field decrements the ECC_SEC bit field by the value provided. | RW | 0b00 | ||
| 7 | CTRL_REG_ERROR | Control Register Error. A bit field in the control register is in an ambiguous state. This means that the redundancy registers have detected a state where not all values are the same and has defaulted to the reset state. S/W needs to re-write these registers to a known state. A write of 1 will set this interrupt flag. | RW | 0 | ||
| 6:5 | PARITY_ERROR | Parity Error Status. A 2-bit saturating counter of the number of parity errors that have occurred since last cleared. 0 No parity error detected 1 One parity error was detected 2 Two parity errors were detected 3 Three parity errors were detected A write of a non-zero value to this bit field increments it by the value provided. |
RW | 0b00 | ||
| 4 | ECC_OTHER | SEC While Writeback Error Status 0 No SEC error while writeback pending 1 Indicates that successive single-bit errors have occurred while a writeback is still pending |
RW | 0 | ||
| 3:2 | ECC_DED | Double Bit Error Detected Status. A 2-bit saturating counter of the number of DED errors that have occurred since last cleared. 0 No double-bit error detected 1 One double-bit error was detected 2 Two double-bit errors were detected 3 Three double-bit errors were detected A write of a non-zero value to this bit field increments it by the value provided. |
RW | 0b00 | ||
| 1:0 | ECC_SEC | Single Bit Error Corrected Status. A 2-bit saturating counter of the number of SEC errors that have occurred since last cleared. 0 No single-bit error detected 1 One single-bit error was detected and corrected 2 Two single-bit errors were detected and corrected 3 Three single-bit errors were detected and corrected A write of a non-zero value to this bit field increments it by the value provided. |
RW | 0b00 | ||
| Address Offset | 0x0000 0424 | ||
| Physical Address | 0x400D 0424 | Instance | 0x400D 0424 |
| Description | This register is accessed through the ECC aggregator via an internal serial bus. To access, the appropriate procedure must be first followed in the MCAN ECC Vector Register. | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | ECC_ROW | Indicates the row address where the single or double-bit error occurred. This value is address offset/4. | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0428 | ||
| Physical Address | 0x400D 0428 | Instance | 0x400D 0428 |
| Description | This register is accessed through the ECC aggregator via an internal serial bus. To access, the appropriate procedure must be first followed in the MCAN ECC Vector Register. | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:10 | RESERVED10 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 | ||
| 9 | CLR_SVBUS_TIMEOUT | Write 1 to clear the Serial VBUS Timeout Flag | RW | 0 | ||
| 8:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 | ||
| 1 | SVBUS_TIMEOUT | Serial VBUS Timeout Flag. Write 1 to set. | RW | 0 | ||
| 0 | WB_PEND | Delayed Write Back Pending Status 0 No write back pending 1 An ECC data correction write back is pending |
RO | 0 | ||
| Address Offset | 0x0000 043C | ||
| Physical Address | 0x400D 043C | Instance | 0x400D 043C |
| Description | MCAN Single Error Corrected End of Interrupt Register | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
| 0 | EOI_WR | Write to this register indicates that software has acknowledged the pending interrupt and the next interrupt can be sent to the host. Note that a write to the MCANERR_ERR_STAT1.CLR_ECC_SEC goes through the SVBUS and has a delayed completion. To avoid an additional interrupt, read the MCANERR_ERR_STAT1 register back prior to writing to this bit field. |
RW | 0 | ||
| Address Offset | 0x0000 0440 | ||
| Physical Address | 0x400D 0440 | Instance | 0x400D 0440 |
| Description | MCAN Single Error Corrected Interrupt Status Register | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
| 0 | MSGMEM_PEND | Message RAM SEC Interrupt Pending 0 No SEC interrupt is pending 1 SEC interrupt is pending |
RW | 0 | ||
| Address Offset | 0x0000 0480 | ||
| Physical Address | 0x400D 0480 | Instance | 0x400D 0480 |
| Description | MCAN Single Error Corrected Interrupt Enable Set Register | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
| 0 | MSGMEM_ENABLE_SET | Message RAM SEC Interrupt Pending Enable Set. Writing a 1 to this bit enables the Message RAM SEC error interrupts. Writing a 0 has no effect. Reads return the corresponding enable bit's current value. | RW | 0 | ||
| Address Offset | 0x0000 04C0 | ||
| Physical Address | 0x400D 04C0 | Instance | 0x400D 04C0 |
| Description | MCAN Single Error Corrected Interrupt Enable Clear Register | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
| 0 | MSGMEM_ENABLE_CLR | Message RAM SEC Interrupt Pending Enable Clear. Writing a 1 to this bit disables the Message RAM SEC error interrupts. Writing a 0 has no effect. Reads return the corresponding enable bit's current value. | RW | 0 | ||
| Address Offset | 0x0000 053C | ||
| Physical Address | 0x400D 053C | Instance | 0x400D 053C |
| Description | MCAN Double Error Detected End of Interrupt Register | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
| 0 | EOI_WR | Write to this register indicates that software has acknowledged the pending interrupt and the next interrupt can be sent to the host. Note that a write to the MCANERR_ERR_STAT1.CLR_ECC_DED goes through the SVBUS and has a delayed completion. To avoid an additional interrupt, read the MCANERR_ERR_STAT1 register back prior to writing to this bit field. |
RW | 0 | ||
| Address Offset | 0x0000 0540 | ||
| Physical Address | 0x400D 0540 | Instance | 0x400D 0540 |
| Description | MCAN Double Error Detected Interrupt Status Register | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
| 0 | MSGMEM_PEND | Message RAM DED Interrupt Pending 0 No DED interrupt is pending 1 DED interrupt is pending |
RW | 0 | ||
| Address Offset | 0x0000 0580 | ||
| Physical Address | 0x400D 0580 | Instance | 0x400D 0580 |
| Description | MCAN Double Error Detected Interrupt Enable Set Register | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
| 0 | MSGMEM_ENABLE_SET | Message RAM DED Interrupt Pending Enable Set. Writing a 1 to this bit enables the Message RAM DED error interrupts. Writing a 0 has no effect. Reads return the corresponding enable bit's current value. | RW | 0 | ||
| Address Offset | 0x0000 05C0 | ||
| Physical Address | 0x400D 05C0 | Instance | 0x400D 05C0 |
| Description | MCAN Double Error Detected Interrupt Enable Clear Register | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
| 0 | MSGMEM_ENABLE_CLR | Message RAM DED Interrupt Pending Enable Clear. Writing a 1 to this bit disables the Message RAM DED error interrupts. Writing a 0 has no effect. Reads return the corresponding enable bit's current value. | RW | 0 | ||
| Address Offset | 0x0000 0600 | ||
| Physical Address | 0x400D 0600 | Instance | 0x400D 0600 |
| Description | MCAN Error Aggregator Enable Set Register | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | ENABLE_TIMEOUT_SET | Write 1 to enable timeout errors. Reads return the corresponding enable bit's current value. | RW | 0 | ||
| 0 | ENABLE_PARITY_SET | Write 1 to enable parity errors. Reads return the corresponding enable bit's current value. | RW | 0 | ||
| Address Offset | 0x0000 0604 | ||
| Physical Address | 0x400D 0604 | Instance | 0x400D 0604 |
| Description | MCAN Error Aggregator Enable Clear Register | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | ENABLE_TIMEOUT_CLR | Write 1 to disable timeout errors. Reads return the corresponding enable bit's current value. | RW | 0 | ||
| 0 | ENABLE_PARITY_CLR | Write 1 to disable parity errors. Reads return the corresponding enable bit's current value. | RW | 0 | ||
| Address Offset | 0x0000 0608 | ||
| Physical Address | 0x400D 0608 | Instance | 0x400D 0608 |
| Description | MCAN Error Aggregator Status Set Register | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | ||
| 3:2 | SVBUS_TIMEOUT | Aggregator Serial VBUS Timeout Error Status 2-bit saturating counter of the number of SVBUS timeout errors that have occurred since last cleared. 0 No timeout errors have occurred 1 One timeout error has occurred 2 Two timeout errors have occurred 3 Three timeout errors have occurred A write of a non-zero value to this bit field increments it by the value provided. |
RW | 0b00 | ||
| 1:0 | AGGR_PARITY_ERR | Aggregator Parity Error Status 2-bit saturating counter of the number of parity errors that have occurred since last cleared. 0 No parity errors have occurred 1 One parity error has occurred 2 Two parity errors have occurred 3 Three parity errors have occurred A write of a non-zero value to this bit field increments it by the value provided. |
RW | 0b00 | ||
| Address Offset | 0x0000 060C | ||
| Physical Address | 0x400D 060C | Instance | 0x400D 060C |
| Description | MCAN Error Aggregator Status Clear Register | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | ||
| 3:2 | SVBUS_TIMEOUT | Aggregator Serial VBUS Timeout Error Status 2-bit saturating counter of the number of SVBUS timeout errors that have occurred since last cleared. 0 No timeout errors have occurred 1 One timeout error has occurred 2 Two timeout errors have occurred 3 Three timeout errors have occurred A write of a non-zero value to this bit field decrements it by the value provided. |
RW | 0b00 | ||
| 1:0 | AGGR_PARITY_ERR | Aggregator Parity Error Status 2-bit saturating counter of the number of parity errors that have occurred since last cleared. 0 No parity errors have occurred 1 One parity error has occurred 2 Two parity errors have occurred 3 Three parity errors have occurred A write of a non-zero value to this bit field decrements it by the value provided. |
RW | 0b00 | ||
| Address Offset | 0x0000 0800 | ||
| Physical Address | 0x400D 0800 | Instance | 0x400D 0800 |
| Description | Description Shows module version and module ID |
||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:16 | MODID | Module identifier MODID[15:0]. Used to uniquely identify this IP. | RO | 0xC64F | ||
| 15:12 | STDIPOFF | 64 B standard IP MMR block (beginning with aggregated IRQ registers) 0: STDIP MMRs do not exist 1:15: These MMRs begin at offset 64*STDIPOFF from IP base address |
RO | 0x0 | ||
| 11:8 | INSTIDX | If multiple instances of IP exists in SOC, this field can identify the instance number 0-15 | RO | 0x0 | ||
| 7:4 | MAJREV | Major revision of IP 0-15 | RO | 0x0 | ||
| 3:0 | MINREV | Minor revision of IP 0-15 (typically revision is 1.0 for a verified new IP) | RO | 0x0 | ||
| Address Offset | 0x0000 0844 | ||
| Physical Address | 0x400D 0844 | Instance | 0x400D 0844 |
| Description | Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS. | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | |||||||||||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | |||||||||||
| 7 | DMA_DONE1 | Mask Channel1 Event.
|
RW | 0 | |||||||||||
| 6 | DMA_DONE0 | Mask Channel1 Event.
|
RW | 0 | |||||||||||
| 5 | FE2 | Mask Channel1 Event.
|
RW | 0 | |||||||||||
| 4 | EXT_TS_OR_WAKE | Mask Channel1 Event.
|
RW | 0 | |||||||||||
| 3 | DED | Mask Channel1 Event.
|
RW | 0 | |||||||||||
| 2 | SEC | Mask Channel1 Event.
|
RW | 0 | |||||||||||
| 1 | INTL1 | Mask Channel1 Event.
|
RW | 0 | |||||||||||
| 0 | INTL0 | Mask channel0 Event
|
RW | 0 | |||||||||||
| Address Offset | 0x0000 0848 | ||
| Physical Address | 0x400D 0848 | Instance | 0x400D 0848 |
| Description | Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS0 register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled. | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | |||||||||||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | |||||||||||
| 7 | DMA_DONE1 | Raw interrupt status for EVENT0. This bit is set to 1 when an event is received on EVENT0 channel. when the corresponding bit in ICLR is set to 1, this bit will be cleared. This bit is also cleared when a new compare value is written in CH0CMP register
|
RO | 0 | |||||||||||
| 6 | DMA_DONE0 | Raw interrupt status for EVENT0. This bit is set to 1 when an event is received on EVENT0 channel. when the corresponding bit in ICLR is set to 1, this bit will be cleared. This bit is also cleared when a new compare value is written in CH0CMP register
|
RO | 0 | |||||||||||
| 5 | FE2 | Raw interrupt status for EVENT0. This bit is set to 1 when an event is received on EVENT0 channel. when the corresponding bit in ICLR is set to 1, this bit will be cleared. This bit is also cleared when a new compare value is written in CH0CMP register
|
RO | 0 | |||||||||||
| 4 | EXT_TS_OR_WAKE | Raw interrupt status for EVENT0. This bit is set to 1 when an event is received on EVENT0 channel. when the corresponding bit in ICLR is set to 1, this bit will be cleared. This bit is also cleared when a new compare value is written in CH0CMP register
|
RO | 0 | |||||||||||
| 3 | DED | Raw interrupt status for EVENT0. This bit is set to 1 when an event is received on EVENT0 channel. when the corresponding bit in ICLR is set to 1, this bit will be cleared. This bit is also cleared when a new compare value is written in CH0CMP register
|
RO | 0 | |||||||||||
| 2 | SEC | Raw interrupt status for EVENT0. This bit is set to 1 when an event is received on EVENT0 channel. when the corresponding bit in ICLR is set to 1, this bit will be cleared. This bit is also cleared when a new compare value is written in CH0CMP register
|
RO | 0 | |||||||||||
| 1 | INTL1 | Raw interrupt status for EVENT1. This bit is set to 1 when an event is received on EVENT1 channel. when the corresponding bit in ICLR is set to 1, this bit will be cleared. This bit is also cleared when the captured time value is read from the CH1CAPT register.
|
RO | 0 | |||||||||||
| 0 | INTL0 | Raw interrupt status for EVENT0. This bit is set to 1 when an event is received on EVENT0 channel. when the corresponding bit in ICLR is set to 1, this bit will be cleared. This bit is also cleared when a new compare value is written in CH0CMP register
|
RO | 0 | |||||||||||
| Address Offset | 0x0000 084C | ||
| Physical Address | 0x400D 084C | Instance | 0x400D 084C |
| Description | Masked interrupt status. This is an AND of the IMASK and RIS registers. | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | |||||||||||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | |||||||||||
| 7 | DMA_DONE1 | Mask interrupt status for EVENT0
|
RO | 0 | |||||||||||
| 6 | DMA_DONE0 | Mask interrupt status for EVENT0
|
RO | 0 | |||||||||||
| 5 | FE2 | Mask interrupt status for EVENT0
|
RO | 0 | |||||||||||
| 4 | EXT_TS_OR_WAKE | Mask interrupt status for EVENT0
|
RO | 0 | |||||||||||
| 3 | DED | Mask interrupt status for EVENT0
|
RO | 0 | |||||||||||
| 2 | SEC | Mask interrupt status for EVENT0
|
RO | 0 | |||||||||||
| 1 | INTL1 | Mask interrupt status for EVENT1
|
RO | 0 | |||||||||||
| 0 | INTL0 | Mask interrupt status for EVENT0
|
RO | 0 | |||||||||||
| Address Offset | 0x0000 0850 | ||
| Physical Address | 0x400D 0850 | Instance | 0x400D 0850 |
| Description | Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET0 will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set. | ||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | |||||||||||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | |||||||||||
| 7 | DMA_DONE1 | Sets EVENT0 in RIS
|
WO | 0 | |||||||||||
| 6 | DMA_DONE0 | Sets EVENT0 in RIS
|
WO | 0 | |||||||||||
| 5 | FE2 | Sets EVENT0 in RIS
|
WO | 0 | |||||||||||
| 4 | EXT_TS_OR_WAKE | Sets EVENT0 in RIS
|
WO | 0 | |||||||||||
| 3 | DED | Sets EVENT0 in RIS
|
WO | 0 | |||||||||||
| 2 | SEC | Sets EVENT0 in RIS
|
WO | 0 | |||||||||||
| 1 | INTL1 | Sets EVENT1 in RIS
|
WO | 0 | |||||||||||
| 0 | INTL0 | Sets EVENT0 in RIS
|
WO | 0 | |||||||||||
| Address Offset | 0x0000 0854 | ||
| Physical Address | 0x400D 0854 | Instance | 0x400D 0854 |
| Description | Interrupt clear. Write a 1 to clear corresponding Interrupt. | ||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | |||||||||||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | |||||||||||
| 7 | DMA_DONE1 | Clears EVENT0 in RIS
|
WO | 0 | |||||||||||
| 6 | DMA_DONE0 | Clears EVENT0 in RIS
|
WO | 0 | |||||||||||
| 5 | FE2 | Clears EVENT0 in RIS
|
WO | 0 | |||||||||||
| 4 | EXT_TS_OR_WAKE | Clears EVENT0 in RIS
|
WO | 0 | |||||||||||
| 3 | DED | Clears EVENT0 in RIS
|
WO | 0 | |||||||||||
| 2 | SEC | Clears EVENT0 in RIS
|
WO | 0 | |||||||||||
| 1 | INTL1 | Clears EVENT1 in RIS
|
WO | 0 | |||||||||||
| 0 | INTL0 | Clears EVENT0 in RIS
|
WO | 0 | |||||||||||
| Address Offset | 0x0000 0864 | ||
| Physical Address | 0x400D 0864 | Instance | 0x400D 0864 |
| Description | Digital Test Bus. This register is used to bring out some internal signals of the peripheral on digital test bus (DTB). | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||
| 31:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 0000 | |||||||||||||||||||||||||||||
| 2:0 | SEL | This bit field is used to select DTB mux digital output signals.
|
RW | 0b000 | |||||||||||||||||||||||||||||
| Address Offset | 0x0000 0868 | ||
| Physical Address | 0x400D 0868 | Instance | 0x400D 0868 |
| Description | Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS. | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | |||||||||||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | |||||||||||
| 7 | DMA_DONE1 | Mask Channel1 Event.
|
RW | 0 | |||||||||||
| 6 | DMA_DONE0 | Mask Channel1 Event.
|
RW | 0 | |||||||||||
| 5 | FE2 | Mask Channel1 Event.
|
RW | 0 | |||||||||||
| 4 | EXT_TS_OR_WAKE | Mask Channel1 Event.
|
RW | 0 | |||||||||||
| 3 | DED | Mask Channel1 Event.
|
RW | 0 | |||||||||||
| 2 | SEC | Mask Channel1 Event.
|
RW | 0 | |||||||||||
| 1 | INTL1 | Mask Channel1 Event.
|
RW | 0 | |||||||||||
| 0 | INTL0 | Mask channel0 Event
|
RW | 0 | |||||||||||
| Address Offset | 0x0000 086C | ||
| Physical Address | 0x400D 086C | Instance | 0x400D 086C |
| Description | Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS0 register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled. | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | |||||||||||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | |||||||||||
| 7 | DMA_DONE1 | Raw interrupt status for EVENT0. This bit is set to 1 when an event is received on EVENT0 channel. when the corresponding bit in ICLR is set to 1, this bit will be cleared. This bit is also cleared when a new compare value is written in CH0CMP register
|
RO | 0 | |||||||||||
| 6 | DMA_DONE0 | Raw interrupt status for EVENT0. This bit is set to 1 when an event is received on EVENT0 channel. when the corresponding bit in ICLR is set to 1, this bit will be cleared. This bit is also cleared when a new compare value is written in CH0CMP register
|
RO | 0 | |||||||||||
| 5 | FE2 | Raw interrupt status for EVENT0. This bit is set to 1 when an event is received on EVENT0 channel. when the corresponding bit in ICLR is set to 1, this bit will be cleared. This bit is also cleared when a new compare value is written in CH0CMP register
|
RO | 0 | |||||||||||
| 4 | EXT_TS_OR_WAKE | Raw interrupt status for EVENT0. This bit is set to 1 when an event is received on EVENT0 channel. when the corresponding bit in ICLR is set to 1, this bit will be cleared. This bit is also cleared when a new compare value is written in CH0CMP register
|
RO | 0 | |||||||||||
| 3 | DED | Raw interrupt status for EVENT0. This bit is set to 1 when an event is received on EVENT0 channel. when the corresponding bit in ICLR is set to 1, this bit will be cleared. This bit is also cleared when a new compare value is written in CH0CMP register
|
RO | 0 | |||||||||||
| 2 | SEC | Raw interrupt status for EVENT0. This bit is set to 1 when an event is received on EVENT0 channel. when the corresponding bit in ICLR is set to 1, this bit will be cleared. This bit is also cleared when a new compare value is written in CH0CMP register
|
RO | 0 | |||||||||||
| 1 | INTL1 | Raw interrupt status for EVENT1. This bit is set to 1 when an event is received on EVENT1 channel. when the corresponding bit in ICLR is set to 1, this bit will be cleared. This bit is also cleared when the captured time value is read from the CH1CAPT register.
|
RO | 0 | |||||||||||
| 0 | INTL0 | Raw interrupt status for EVENT0. This bit is set to 1 when an event is received on EVENT0 channel. when the corresponding bit in ICLR is set to 1, this bit will be cleared. This bit is also cleared when a new compare value is written in CH0CMP register
|
RO | 0 | |||||||||||
| Address Offset | 0x0000 0870 | ||
| Physical Address | 0x400D 0870 | Instance | 0x400D 0870 |
| Description | Masked interrupt status. This is an AND of the IMASK and RIS registers. | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | |||||||||||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | |||||||||||
| 7 | DMA_DONE1 | Mask interrupt status for EVENT0
|
RO | 0 | |||||||||||
| 6 | DMA_DONE0 | Mask interrupt status for EVENT0
|
RO | 0 | |||||||||||
| 5 | FE2 | Mask interrupt status for EVENT0
|
RO | 0 | |||||||||||
| 4 | EXT_TS_OR_WAKE | Mask interrupt status for EVENT0
|
RO | 0 | |||||||||||
| 3 | DED | Mask interrupt status for EVENT0
|
RO | 0 | |||||||||||
| 2 | SEC | Mask interrupt status for EVENT0
|
RO | 0 | |||||||||||
| 1 | INTL1 | Mask interrupt status for EVENT1
|
RO | 0 | |||||||||||
| 0 | INTL0 | Mask interrupt status for EVENT0
|
RO | 0 | |||||||||||
| Address Offset | 0x0000 0874 | ||
| Physical Address | 0x400D 0874 | Instance | 0x400D 0874 |
| Description | Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET0 will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set. | ||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | |||||||||||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | |||||||||||
| 7 | DMA_DONE1 | Sets EVENT0 in RIS
|
WO | 0 | |||||||||||
| 6 | DMA_DONE0 | Sets EVENT0 in RIS
|
WO | 0 | |||||||||||
| 5 | FE2 | Sets EVENT0 in RIS
|
WO | 0 | |||||||||||
| 4 | EXT_TS_OR_WAKE | Sets EVENT0 in RIS
|
WO | 0 | |||||||||||
| 3 | DED | Sets EVENT0 in RIS
|
WO | 0 | |||||||||||
| 2 | SEC | Sets EVENT0 in RIS
|
WO | 0 | |||||||||||
| 1 | INTL1 | Sets EVENT1 in RIS
|
WO | 0 | |||||||||||
| 0 | INTL0 | Sets EVENT0 in RIS
|
WO | 0 | |||||||||||
| Address Offset | 0x0000 0878 | ||
| Physical Address | 0x400D 0878 | Instance | 0x400D 0878 |
| Description | Interrupt clear. Write a 1 to clear corresponding Interrupt. | ||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | |||||||||||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | |||||||||||
| 7 | DMA_DONE1 | Clears EVENT0 in RIS
|
WO | 0 | |||||||||||
| 6 | DMA_DONE0 | Clears EVENT0 in RIS
|
WO | 0 | |||||||||||
| 5 | FE2 | Clears EVENT0 in RIS
|
WO | 0 | |||||||||||
| 4 | EXT_TS_OR_WAKE | Clears EVENT0 in RIS
|
WO | 0 | |||||||||||
| 3 | DED | Clears EVENT0 in RIS
|
WO | 0 | |||||||||||
| 2 | SEC | Clears EVENT0 in RIS
|
WO | 0 | |||||||||||
| 1 | INTL1 | Clears EVENT1 in RIS
|
WO | 0 | |||||||||||
| 0 | INTL0 | Clears EVENT0 in RIS
|
WO | 0 | |||||||||||
| Address Offset | 0x0000 0904 | ||
| Physical Address | 0x400D 0904 | Instance | 0x400D 0904 |
| Description | Needs to go to the Management apperture once available | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||||||||||||||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||||||||||||||
| 1:0 | RATIO | Clock divide ratio specification. Enables configuring clock divide settings for the MCAN functional clock input to the MCAN-SS.
|
RW | 0b00 | ||||||||||||||
| Address Offset | 0x0000 0908 | ||
| Physical Address | 0x400D 0908 | Instance | 0x400D 0908 |
| Description | MCANSS clock stop control MMR. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | |||||||||||
| 31:9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 | |||||||||||
| 8 | WKUP_GLTFLT_EN | Setting this bit enables the glitch filter on MCAN RXD input, which wakes up the MCAN controller to exit clock gating.
|
RW | 0 | |||||||||||
| 7:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||
| 4 | WAKEUP_INT_EN | This bit contols enabling or disabling the MCAN IP clock stop wakeup interrupt (when MCANSS_CTRL.WAKEUPREQEN wakeup request is enabled to wakeup MCAN IP upon CAN RXD activity)
|
RW | 0 | |||||||||||
| 3:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||
| 0 | STOPREQ | This bit is used to enable/disable MCAN clock (both host clock and functional clock) gating request. Note: This bit can be reset by HW by Clock-Stop Wake-up via CAN RX Activity. See spec for more details.
|
RW | 0 | |||||||||||
| Address Offset | 0x0000 090C | ||
| Physical Address | 0x400D 090C | Instance | 0x400D 090C |
| Description | MCANSS clock stop status register to indicate status of clock stop mechanism | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | |||||||||||
| 31:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 | |||||||||||
| 4 | STOPREQ_HW_OVR | MCANSS clock stop HW override status bit. This bit indicates when the MCANSS_CLKCTL.STOPREQ bit has been cleared by HW when a clock-stop wake-up event via CAN RX activity is trigged.
|
RO | 0 | |||||||||||
| 3:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||
| 0 | CLKSTOP_ACKSTS | Clock stop acknowledge status from MCAN IP
|
RO | 0 | |||||||||||
| Address Offset | 0x0000 0924 | ||
| Physical Address | 0x400D 0924 | Instance | 0x400D 0924 |
| Description | MCANSS fixed DMA0 control and configuration register | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 31:27 | RX_BUF_TTO_OFFST | Indicates the Rx-buffer (index x) to be mapped to FE_0 (FE001) and automatically maps and Rx buffer (index x+1) to FE_1 (FE010) Valid range: Rxbuffer (0) to Rxbuffer (30)
|
RW | 0b0 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 26:25 | RESERVED25 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 24 | RX_FE_OTO_SEL | RX_FE_OTO_SEL is used to select the MCAN RX buffer filter event signal mapped to trigger fixed MCANSS DMA channel trigger
|
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 23:22 | RESERVED22 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 21:16 | TX_BRP_MTO_NUM | Number of TX buffer request pending (BRP) signals for multi-to-one DMA trigger mapping sequence, starting from the buffer offset number selected by TX_BRP_MTO_OFFST bits
|
RW | 0b00 0010 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 15 | RESERVED15 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 14:10 | TX_BRP_MTO_OFFST | TX_BRP_MTO_OFFST selects the Tx buffer offset number for the multi-to-one round robin DMA trigger mode.
|
RW | 0b0 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 8:4 | TX_BRP_OTO_SEL | TX_BRP_OTO_SEL is used to select the MCAN TX buffer request pending (BRP) signal mapped to trigger fixed MCANSS DMA channel trigger
|
RW | 0b0 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 3:2 | DMA_TRIG_SEL | DMA trigger select bits used to select between MCAN TX one-to-one mapping, MCAN TX multi-to-one round robin mapping and MCAN Rx one-to-one mapping options
|
RW | 0b00 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 0 | DMA_TRIG_EN | DMA_TRIG_EN is used to enable/disable MCAN RX, TX triggers to MCANSS fixed DMA channel.
|
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Address Offset | 0x0000 092C | ||
| Physical Address | 0x400D 092C | Instance | 0x400D 092C |
| Description | MCANSS fixed DMA1 control and configuration register | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 31:27 | RX_BUF_TTO_OFFST | Indicates the Rx-buffer (index x) to be mapped to FE_0 (FE001) and automatically maps and Rx buffer (index x+1) to FE_1 (FE010) Valid range: Rxbuffer (0) to Rxbuffer (30)
|
RW | 0b0 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 26:25 | RESERVED25 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 24 | RX_FE_OTO_SEL | RX_FE_OTO_SEL is used to select the MCAN RX buffer filter event signal mapped to trigger fixed MCANSS DMA channel trigger
|
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 23:22 | RESERVED22 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 21:16 | TX_BRP_MTO_NUM | Number of TX buffer request pending (BRP) signals for multi-to-one DMA trigger mapping sequence, starting from the buffer offset number selected by TX_BRP_MTO_OFFST bits
|
RW | 0b00 0010 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 15 | RESERVED15 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 14:10 | TX_BRP_MTO_OFFST | TX_BRP_MTO_OFFST selects the Tx buffer offset number for the multi-to-one round robin DMA trigger mode.
|
RW | 0b0 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 8:4 | TX_BRP_OTO_SEL | TX_BRP_OTO_SEL is used to select the MCAN TX buffer request pending (BRP) signal mapped to trigger fixed MCANSS DMA channel trigger
|
RW | 0b0 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 3:2 | DMA_TRIG_SEL | DMA trigger select bits used to select between MCAN TX one-to-one mapping, MCAN TX multi-to-one round robin mapping and MCAN Rx one-to-one mapping options
|
RW | 0b00 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 0 | DMA_TRIG_EN | DMA_TRIG_EN is used to enable/disable MCAN RX, TX triggers to MCANSS fixed DMA channel.
|
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Address Offset | 0x0000 0938 | ||
| Physical Address | 0x400D 0938 | Instance | 0x400D 0938 |
| Description | Rx buffer (index x) base address. Applicable to Rx buffer DMA two-to-one mode mapped to FE001 trigger: >> LS bits 0:1 in this MMR are reserved and read as '0' as the MCAN SRAM is 4 byte data addressable. >> Index x is selected using MCANSS_DMAn_CTL.RX_FE_TTO_SEL bits. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | |||||||||||
| 31:15 | RESERVED15 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 | |||||||||||
| 14:2 | BASE_ADDR | FE0 Rx Buf x Base adddress (14:2). Address should be compited based on the 14-bit RBSA (Rx buffer start address) + offset (depending on Rx buffer element index value and data length code (DLC) for all the buffer elements before the Rx buffer element (x))
|
RW | 0b0 0000 0000 0000 | |||||||||||
| 1:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | |||||||||||
| Address Offset | 0x0000 0948 | ||
| Physical Address | 0x400D 0948 | Instance | 0x400D 0948 |
| Description | Rx buffer (index x+1) base address Applicable to Rx buffer DMA two-to-one mode mapped to FE010 trigger: >> LS bits 0:1 in this MMR are reserved and read as '0' as the MCAN SRAM is 4 byte data addressable. >> Index x is selected using MCANSS_DMAn_CTL.RX_FE_TTO_SEL bits. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | |||||||||||
| 31:15 | RESERVED15 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 | |||||||||||
| 14:2 | BASE_ADDR | FE010 Rx Buf x Base adddress (14:2). Address should be compited based on the 14-bit RBSA (Rx buffer start address) + offset (depending on Rx buffer element index value and data length code (DLC) for all the buffer elements before the Rx buffer element (x+1))
|
RW | 0b0 0000 0000 0000 | |||||||||||
| 1:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | |||||||||||
| Address Offset | 0x0000 0950 | ||
| Physical Address | 0x400D 0950 | Instance | 0x400D 0950 |
| Description | Rx Buffer two-to-one DMA mode, hardware NDAT1 value register. The address of this register is programmed as the DMA source address register for moving NDAT1 value during DMA operation. This register is automatically updated on the fly depending on FE001/FE010 (Rxbuf(x)/Rxbuf(x+1)) ongoing transfer. |
||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | |||||||||||
| 31:0 | NDAT1_VAL | NDAT1 value to be programmed onto MCAN.NDAT1 MMR. Automatically updated by HW.
|
RW | 0x0000 0000 | |||||||||||
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