Instance: LGPT3
Component: LGPT3
Base address: 0x40063000
This component is a general purpose timer.
The timer offers
- generation of waveforms and events.
- capture of signal period and duty cycle.
- generation of IR signals.
- decoding of quadrature encoded signals.
- motor control features.
It consists of a
- 16-bit counter.
- 8-bit prescaler
- 3 capture compare channels.
- 3 event outputs.
- 3 capture inputs.
Each channel subscribes to the synchronous event bus. They can control one or more event outputs in both capture and compare modes. PRECFG.TICKSRC selects tick source for the timer.
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RO |
32 |
0xDE49 1010 |
0x0000 0000 |
0x4006 3000 |
|
RO |
32 |
0x0002 18D3 |
0x0000 0004 |
0x4006 3004 |
|
RW |
32 |
0x0000 0000 |
0x0000 0008 |
0x4006 3008 |
|
RW |
32 |
0x0000 0000 |
0x0000 000C |
0x4006 300C |
|
RW |
32 |
0x0000 0000 |
0x0000 0010 |
0x4006 3010 |
|
RW |
32 |
0x0000 0000 |
0x0000 0014 |
0x4006 3014 |
|
RW |
32 |
0x0000 0000 |
0x0000 0018 |
0x4006 3018 |
|
RW |
32 |
0x0000 0000 |
0x0000 001C |
0x4006 301C |
|
RW |
32 |
0x0000 0000 |
0x0000 0020 |
0x4006 3020 |
|
RW |
32 |
0x0000 0000 |
0x0000 003C |
0x4006 303C |
|
RW |
32 |
0x0000 0000 |
0x0000 0040 |
0x4006 3040 |
|
RW |
32 |
0x0000 0000 |
0x0000 0044 |
0x4006 3044 |
|
RW |
32 |
0x0000 0000 |
0x0000 0048 |
0x4006 3048 |
|
RW |
32 |
0x0000 0000 |
0x0000 0068 |
0x4006 3068 |
|
RO |
32 |
0x0000 0000 |
0x0000 006C |
0x4006 306C |
|
RO |
32 |
0x0000 0000 |
0x0000 0070 |
0x4006 3070 |
|
WO |
32 |
0x0000 0000 |
0x0000 0074 |
0x4006 3074 |
|
WO |
32 |
0x0000 0000 |
0x0000 0078 |
0x4006 3078 |
|
WO |
32 |
0x0000 0000 |
0x0000 007C |
0x4006 307C |
|
WO |
32 |
0x0000 0000 |
0x0000 0080 |
0x4006 3080 |
|
RW |
32 |
0x0000 0000 |
0x0000 0084 |
0x4006 3084 |
|
RW |
32 |
0x0000 0000 |
0x0000 00C0 |
0x4006 30C0 |
|
RW |
32 |
0x0000 0000 |
0x0000 00C4 |
0x4006 30C4 |
|
RW |
32 |
0x0000 0000 |
0x0000 00C8 |
0x4006 30C8 |
|
RW |
32 |
0x0000 0000 |
0x0000 00FC |
0x4006 30FC |
|
RW |
32 |
0x0000 0000 |
0x0000 0100 |
0x4006 3100 |
|
RW |
32 |
0x0000 0000 |
0x0000 0104 |
0x4006 3104 |
|
RW |
32 |
0x0000 0000 |
0x0000 0108 |
0x4006 3108 |
|
RW |
32 |
0x00FF FFFF |
0x0000 013C |
0x4006 313C |
|
RW |
32 |
0x0000 0000 |
0x0000 0140 |
0x4006 3140 |
|
RW |
32 |
0x0000 0000 |
0x0000 0144 |
0x4006 3144 |
|
RW |
32 |
0x0000 0000 |
0x0000 0148 |
0x4006 3148 |
|
RW |
32 |
0x0000 0000 |
0x0000 017C |
0x4006 317C |
|
RW |
32 |
0x0000 0000 |
0x0000 0180 |
0x4006 3180 |
|
RW |
32 |
0x0000 0000 |
0x0000 0184 |
0x4006 3184 |
|
RW |
32 |
0x0000 0000 |
0x0000 0188 |
0x4006 3188 |
|
RW |
32 |
0x00FF FFFF |
0x0000 01BC |
0x4006 31BC |
|
RW |
32 |
0x0000 0000 |
0x0000 01C0 |
0x4006 31C0 |
|
RW |
32 |
0x0000 0000 |
0x0000 01C4 |
0x4006 31C4 |
|
RW |
32 |
0x0000 0000 |
0x0000 01C8 |
0x4006 31C8 |
Address Offset | 0x0000 0000 | ||
Physical Address | 0x4006 3000 | Instance | 0x4006 3000 |
Description | Description Register. This register provides IP module ID, revision information, instance index and standard MMR registers offset. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:16 | MODID | Module identifier used to uniquely identify this IP. | RO | 0xDE49 | ||
15:12 | STDIPOFF | Standard IP MMR block offset. Standard IP MMRs are the set of from aggregated IRQ registers till DTB. 0: Standard IP MMRs do not exist 0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP address) |
RO | 0x1 | ||
11:8 | INSTIDX | IP Instance ID number. If multiple instances of IP exist in the device, this field can identify the instance number. | RO | 0x0 | ||
7:4 | MAJREV | Major revision of IP. | RO | 0x1 | ||
3:0 | MINREV | Minor revision of IP. | RO | 0x0 |
Address Offset | 0x0000 0004 | ||
Physical Address | 0x4006 3004 | Instance | 0x4006 3004 |
Description | Description Extended This register describes the parameters of the LGPT. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||
31:20 | RESERVED20 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 | |||||||||||||||||
19 | HIR | Has IR logic. | RO | 0 | |||||||||||||||||
18 | HDBF | Has Dead-Band, Fault, and Park logic. | RO | 0 | |||||||||||||||||
17:14 | PREW | Prescale width. The prescaler can maximum be configured to 2^PREW-1. | RO | 0x8 | |||||||||||||||||
13 | HQDEC | Has Quadrature Decoder. | RO | 0 | |||||||||||||||||
12 | HCIF | Has channel input filter. | RO | 1 | |||||||||||||||||
11:8 | CIFS | Channel input filter size. The prevailing state filter can maximum be configured to 2^CIFS-1. | RO | 0x8 | |||||||||||||||||
7 | HDMA | Has uDMA output and logic. | RO | 1 | |||||||||||||||||
6 | HINT | Has interrupt output and logic. | RO | 1 | |||||||||||||||||
5:4 | CNTRW | Counter bit-width. The maximum counter value is equal to 2^CNTRW-1.
|
RO | 0b01 | |||||||||||||||||
3:0 | NCH | Number of channels. | RO | 0x3 |
Address Offset | 0x0000 0008 | ||
Physical Address | 0x4006 3008 | Instance | 0x4006 3008 |
Description | Start Configuration This register is only for when CTL.MODE is configured to one of the SYNC modes. This register defines when this LGPT starts. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||
31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||||||||
1:0 | LGPT0 | LGPT start
|
RW | 0b00 |
Address Offset | 0x0000 000C | ||
Physical Address | 0x4006 300C | Instance | 0x4006 300C |
Description | Timer Control | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||
31:11 | RESERVED11 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 | |||||||||||||||||||||||||||||
10 | C2RST | Channel 2 reset.
|
WO | 0 | |||||||||||||||||||||||||||||
9 | C1RST | Channel 1 reset.
|
WO | 0 | |||||||||||||||||||||||||||||
8 | C0RST | Channel 0 reset.
|
WO | 0 | |||||||||||||||||||||||||||||
7:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | |||||||||||||||||||||||||||||
5 | INTP | Interrupt Phase. This bit field controls when the RIS.TGT and RIS.ZERO interrupts are set.
|
RW | 0 | |||||||||||||||||||||||||||||
4:3 | CMPDIR | Compare direction. This bit field controls the direction the counter must have in order to set the [RIS.CnCC] channel interrupts. This bitfield is only relevant if [CnCFG.CCACT] is configured to a compare action.
|
RW | 0b00 | |||||||||||||||||||||||||||||
2:0 | MODE | Timer mode control The CNTR restarts from 0 when MODE is written to UP_ONCE, UP_PER, UPDWN_PER, QDEC, SYNC_UP_ONCE, SYNC_UP_PER or SYNC_UPDWN_PER. When writing MODE all internally queued updates to the channels and TGT is cleared. When configuring the timer, MODE should be the last thing to configure. If changing timer configuration after MODE has been set is necessary, instructions, if any, given in the configuration registers should be followed. See for example C0CFG.
|
RW | 0b000 |
Address Offset | 0x0000 0010 | ||
Physical Address | 0x4006 3010 | Instance | 0x4006 3010 |
Description | Output Control Set and clear individual outputs manually. Manual update of an output takes priority over automatic channel updates to the same output. It is not possible to set and clear an output at the same time, such requests will be neglected. An output can be automatically cleared, set, toggled, or pulsed by each channel, listed in decreasing order of priority. The action with highest priority happens when multiple channels want to update an output at the same time. All outputs are connected to the event fabric and the IO controller. The outputs going to the IO controller have an aditional complementary output, this output is the inverted IO output. Both the IO and the IO complementary outputs are passed through an IO Controller, see IOCTL. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 | ||
5 | SETOUT2 | Set output 2. Write 1 to set output 2. |
WO | 0 | ||
4 | CLROUT2 | Clear output 2. Write 1 to clear output 2. |
WO | 0 | ||
3 | SETOUT1 | Set output 1. Write 1 to set output 1. |
WO | 0 | ||
2 | CLROUT1 | Clear output 1. Write 1 to clear output 1. |
WO | 0 | ||
1 | SETOUT0 | Set output 0. Write 1 to set output 0. |
WO | 0 | ||
0 | CLROUT0 | Clear output 0. Write 1 to clear output 0. |
WO | 0 |
Address Offset | 0x0000 0014 | ||
Physical Address | 0x4006 3014 | Instance | 0x4006 3014 |
Description | Counter The counter of this timer. After CTL.MODE is set the counter updates at the rate specified in PRECFG. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 | ||
23:0 | VAL | Current counter value. If CTL.MODE = QDEC this can be used to set the initial counter value during QDEC. Writing to CNTR in other modes than QDEC is possible, but may result in unpredictable behavior. |
RW | 0x00 0000 |
Address Offset | 0x0000 0018 | ||
Physical Address | 0x4006 3018 | Instance | 0x4006 3018 |
Description | Clock Prescaler Configuration This register is used to set the timer clock period. The prescaler is a counter which counts down from the value TICKDIV. When the prescaler counter reaches zero, CNTR is updated. The field TICKDIV effectively divides the prescaler tick source. The timer clock frequency can be calculated as TICKSRC/(TICKDIV+1). |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | |||||||||||||||||
15:8 | TICKDIV | Tick division. TICKDIV determines the timer clock frequency for the counter, and timer output updates. The timer clock frequency is the clock selected by TICKSRC divided by (TICKDIV + 1). This inverse is the timer clock period. 0x00: Divide by 1. 0x01: Divide by 2. ... 0xFF: Divide by 256. |
RW | 0x00 | |||||||||||||||||
7:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 | |||||||||||||||||
1:0 | TICKSRC | Prescaler tick source. TICKSRC determines the source which decrements the prescaler.
|
RW | 0b00 |
Address Offset | 0x0000 001C | ||
Physical Address | 0x4006 301C | Instance | 0x4006 301C |
Description | Prescaler Event This register is used to output a logic high signal before the zero crossing of the prescaler counter. The output is routed to the IOC. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
7:0 | VAL | Sets the HIGH time of the prescaler event output. Event goes high when the prescaler counter equals VAL. Event goes low when prescaler counter is 0. Note: - Can be used to precharge or turn an external component on for a short time before sampling, like in QDEC. - If there is a requirement to create such events that have very short periods compared to timer clock period, use two timers. One timer acts as prescaler and event generator for another timer. |
RW | 0x00 |
Address Offset | 0x0000 0020 | ||
Physical Address | 0x4006 3020 | Instance | 0x4006 3020 |
Description | Channel Input Filter This register is used to configure the filter on the channel inputs. The configuration is for all inputs. The filter is enabled when a channel is in capture mode. The input to the filter is passed to the edge detection logic if LOAD + 1 consecutive input samples are equal. The filter functions as a down counter, counting down every input sample. If two consecutive samples are unequal, the filter counter restarts from LOAD. If the filter counter reaches zero, the input signal is valid and passed to the edge detection logic. The channel filter should only be configured while the CTL.MODE = DIS. Configuring the filter while the timer is running can result in unexpected behavior. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | |||||||||||||||||
15:8 | LOAD | The input of the channel filter is passed to the edge detection logic after LOAD + 1 consecutive equal samples. | RW | 0x00 | |||||||||||||||||
7:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 | |||||||||||||||||
1:0 | MODE | Channel filter mode
|
RW | 0b00 |
Address Offset | 0x0000 003C | ||
Physical Address | 0x4006 303C | Instance | 0x4006 303C |
Description | Direct Memory Accsess This register is used to enable DMA requests from the timer and set the register addresses which the DMA will access (read/write). Choose DMA request source by setting the REQ field. The setting of the corresponding interrupt in the RIS registers also sets the DMA request. Upon a DMA request defined by REQ an internal address pointer is set to RWADDR*4. Every access to DMARW will increment the internal pointer by 4 such that the next DMA access will be to the next register. The internal pointer will stop after RWCNTR increments. Further access will be ignored. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||||||||||||||||||||
31:20 | RESERVED20 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
19:16 | RWCNTR | The read/write counter. RWCNTR+1 is the number of times the DMA can access (read/write) the DMARW register. For each DMA access to DMARW an internal counter is incremented, writing to the next address field. RWADDR + 4*RWCNTR is the final register address which can be accessed by the DMA. | RW | 0x0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
15 | RESERVED15 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
14:8 | RWADDR | The base address which the DMA access when reading/writing DMARW. The base address is set by taking the 9 LSB of the physical address and divide by 4. For example, if you wanted the RWADDR to point to the PTGT register you should set RWADDR = 0x0FC/4. |
RW | 0b000 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
7:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
3:0 | REQ |
|
RW | 0x0 |
Address Offset | 0x0000 0040 | ||
Physical Address | 0x4006 3040 | Instance | 0x4006 3040 |
Description | Direct Memory Access This register is used by the DMA to access (read/write) register inside this LGPT module. Each access to this register will increment the internal DMA address counter. See DMA for description. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 | ||
23:0 | VAL | DMA read write value. The value that is read/written from/to the registers. |
RW | 0x00 0000 |
Address Offset | 0x0000 0044 | ||
Physical Address | 0x4006 3044 | Instance | 0x4006 3044 |
Description | ADC Trigger This register is used to enable ADC trigger from the timer. Choose ADC trigger source by setting the SRC field. The setting of the corresponding interrupt in the RIS registers also sets the ADC trigger. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||||||||||||||||||||
31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
3:0 | SRC |
|
RW | 0x0 |
Address Offset | 0x0000 0048 | ||
Physical Address | 0x4006 3048 | Instance | 0x4006 3048 |
Description | IO Controller This register overrides the IO outputs. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||
31:12 | RESERVED12 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 0000 | |||||||||||||||||
11:10 | COUT2 | IO complementary output 2 control This bit field controls IO complementary output 2.
|
RW | 0b00 | |||||||||||||||||
9:8 | OUT2 | IO output 2 control This bit field controls IO output 2.
|
RW | 0b00 | |||||||||||||||||
7:6 | COUT1 | IO complementary output 1 control This bit field controls IO complementary output 1.
|
RW | 0b00 | |||||||||||||||||
5:4 | OUT1 | IO output 1 control This bit field controls IO output 1.
|
RW | 0b00 | |||||||||||||||||
3:2 | COUT0 | IO complementary output 0 control This bit field controls IO complementary output 0.
|
RW | 0b00 | |||||||||||||||||
1:0 | OUT0 | IO output 0 control This bit field controls IO output 0.
|
RW | 0b00 |
Address Offset | 0x0000 0068 | ||
Physical Address | 0x4006 3068 | Instance | 0x4006 3068 |
Description | Interrupt mask. This register selects interrupt sources which are allowed to pass from RIS to MIS when the corresponding bit-fields are set to 1. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:11 | RESERVED11 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 | |||||||||||
10 | C2CC | Enable RIS.C2CC interrupt.
|
RW | 0 | |||||||||||
9 | C1CC | Enable RIS.C1CC interrupt.
|
RW | 0 | |||||||||||
8 | C0CC | Enable RIS.C0CC interrupt.
|
RW | 0 | |||||||||||
7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||
6 | FAULT | Enable RIS.FAULT interrupt.
|
RW | 0 | |||||||||||
5 | IDX | Enable RIS.IDX interrupt.
|
RW | 0 | |||||||||||
4 | DIRCHNG | Enable RIS.DIRCHNG interrupt.
|
RW | 0 | |||||||||||
3 | CNTRCHNG | Enable RIS.CNTRCHNG interrupt.
|
RW | 0 | |||||||||||
2 | DBLTRANS | Enable RIS.DBLTRANS interrupt.
|
RW | 0 | |||||||||||
1 | ZERO | Enable RIS.ZERO interrupt.
|
RW | 0 | |||||||||||
0 | TGT | Enable RIS.TGT interrupt.
|
RW | 0 |
Address Offset | 0x0000 006C | ||
Physical Address | 0x4006 306C | Instance | 0x4006 306C |
Description | Raw interrupt status. This register reflects the state of all pending interrupts, regardless of masking. This register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the corresponding ICLR register bit. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:11 | RESERVED11 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 | |||||||||||
10 | C2CC | Status of the C2CC interrupt. The interrupt is set when C2CC has capture or compare event.
|
RO | 0 | |||||||||||
9 | C1CC | Status of the C1CC interrupt. The interrupt is set when C1CC has capture or compare event.
|
RO | 0 | |||||||||||
8 | C0CC | Status of the C0CC interrupt. The interrupt is set when C0CC has capture or compare event.
|
RO | 0 | |||||||||||
7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||
6 | FAULT | Status of the FAULT interrupt. The interrupt is set immediately on active fault input.
|
RO | 0 | |||||||||||
5 | IDX | Status of the IDX interrupt. The interrupt is set when IDX is active.
|
RO | 0 | |||||||||||
4 | DIRCHNG | Status of the DIRCHNG interrupt. The interrupt is set when the direction of the counter changes.
|
RO | 0 | |||||||||||
3 | CNTRCHNG | Status of the CNTRCHNG interrupt. The interrupt is set when the counter increments or decrements.
|
RO | 0 | |||||||||||
2 | DBLTRANS | Status of the DBLTRANS interrupt. The interrupt is set when a double transition has happened during QDEC mode.
|
RO | 0 | |||||||||||
1 | ZERO | Status of the ZERO interrupt. The interrupt is set when CNTR = 0.
|
RO | 0 | |||||||||||
0 | TGT | Status of the TGT interrupt. The interrupt is set when CNTR = TGT.
|
RO | 0 |
Address Offset | 0x0000 0070 | ||
Physical Address | 0x4006 3070 | Instance | 0x4006 3070 |
Description | Masked interrupt status. This register is simply a bitwise AND of the contents of IMASK and RIS.*] registers. A flag set in this register can be cleared by writing 1 to the corresponding ICLR register bit. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:11 | RESERVED11 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 | |||||||||||
10 | C2CC | Masked status of the RIS.C2CC interrupt.
|
RO | 0 | |||||||||||
9 | C1CC | Masked status of the RIS.C1CC interrupt.
|
RO | 0 | |||||||||||
8 | C0CC | Masked status of the RIS.C0CC interrupt.
|
RO | 0 | |||||||||||
7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||
6 | FAULT | Masked status of the RIS.FAULT interrupt.
|
RO | 0 | |||||||||||
5 | IDX | Masked status of the RIS.IDX interrupt.
|
RO | 0 | |||||||||||
4 | DIRCHNG | Masked status of the RIS.DIRCHNG interrupt.
|
RO | 0 | |||||||||||
3 | CNTRCHNG | Masked status of the RIS.CNTRCHNG interrupt.
|
RO | 0 | |||||||||||
2 | DBLTRANS | Masked status of the RIS.DBLTRANS interrupt.
|
RO | 0 | |||||||||||
1 | ZERO | Masked status of the RIS.ZERO interrupt.
|
RO | 0 | |||||||||||
0 | TGT | Masked status of the RIS.TGT interrupt.
|
RO | 0 |
Address Offset | 0x0000 0074 | ||
Physical Address | 0x4006 3074 | Instance | 0x4006 3074 |
Description | Interrupt set register. This register can used by software for diagnostics and safety checking purposes. Writing a 1 to a bit in this register will set the event and the corresponding RIS bit also gets set. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets set. |
||
Type | WO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:11 | RESERVED11 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 | |||||||||||
10 | C2CC | Set the RIS.C2CC interrupt.
|
WO | 0 | |||||||||||
9 | C1CC | Set the RIS.C1CC interrupt.
|
WO | 0 | |||||||||||
8 | C0CC | Set the RIS.C0CC interrupt.
|
WO | 0 | |||||||||||
7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||
6 | FAULT | Set the RIS.FAULT interrupt.
|
WO | 0 | |||||||||||
5 | IDX | Set the RIS.IDX interrupt.
|
WO | 0 | |||||||||||
4 | DIRCHNG | Set the RIS.DIRCHNG interrupt.
|
WO | 0 | |||||||||||
3 | CNTRCHNG | Set the RIS.CNTRCHNG interrupt.
|
WO | 0 | |||||||||||
2 | DBLTRANS | Set the RIS.DBLTRANS interrupt.
|
WO | 0 | |||||||||||
1 | ZERO | Set the RIS.ZERO interrupt.
|
WO | 0 | |||||||||||
0 | TGT | Set the RIS.TGT interrupt.
|
WO | 0 |
Address Offset | 0x0000 0078 | ||
Physical Address | 0x4006 3078 | Instance | 0x4006 3078 |
Description | Interrupt clear register. This register allows software to clear interrupts. Writing a 1 to a bit in this register will clear the event and the corresponding RIS bit also gets cleared. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets cleared. |
||
Type | WO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:11 | RESERVED11 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 | |||||||||||
10 | C2CC | Clear the RIS.C2CC interrupt.
|
WO | 0 | |||||||||||
9 | C1CC | Clear the RIS.C1CC interrupt.
|
WO | 0 | |||||||||||
8 | C0CC | Clear the RIS.C0CC interrupt.
|
WO | 0 | |||||||||||
7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||
6 | FAULT | Clear the RIS.FAULT interrupt.
|
WO | 0 | |||||||||||
5 | IDX | Clear the RIS.IDX interrupt.
|
WO | 0 | |||||||||||
4 | DIRCHNG | Clear the RIS.DIRCHNG interrupt.
|
WO | 0 | |||||||||||
3 | CNTRCHNG | Clear the RIS.CNTRCHNG interrupt.
|
WO | 0 | |||||||||||
2 | DBLTRANS | Clear the RIS.DBLTRANS interrupt.
|
WO | 0 | |||||||||||
1 | ZERO | Clear the RIS.ZERO interrupt.
|
WO | 0 | |||||||||||
0 | TGT | Clear the RIS.TGT interrupt.
|
WO | 0 |
Address Offset | 0x0000 007C | ||
Physical Address | 0x4006 307C | Instance | 0x4006 307C |
Description | Interrupt mask set register. Writing a 1 to a bit in this register will set the corresponding IMASK bit. |
||
Type | WO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:11 | RESERVED11 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 | |||||||||||
10 | C2CC | Set the MIS.C2CC mask.
|
WO | 0 | |||||||||||
9 | C1CC | Set the MIS.C1CC mask.
|
WO | 0 | |||||||||||
8 | C0CC | Set the MIS.C0CC mask.
|
WO | 0 | |||||||||||
7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||
6 | FAULT | Set the MIS.FAULT mask.
|
WO | 0 | |||||||||||
5 | IDX | Set the MIS.IDX mask.
|
WO | 0 | |||||||||||
4 | DIRCHNG | Set the MIS.DIRCHNG mask.
|
WO | 0 | |||||||||||
3 | CNTRCHNG | Set the MIS.CNTRCHNG mask.
|
WO | 0 | |||||||||||
2 | DBLTRANS | Set the MIS.DBLTRANS mask.
|
WO | 0 | |||||||||||
1 | ZERO | Set the MIS.ZERO mask.
|
WO | 0 | |||||||||||
0 | TGT | Set the MIS.TGT mask.
|
WO | 0 |
Address Offset | 0x0000 0080 | ||
Physical Address | 0x4006 3080 | Instance | 0x4006 3080 |
Description | Interrupt mask clear register. Writing a 1 to a bit in this register will clear the corresponding IMASK bit. |
||
Type | WO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:11 | RESERVED11 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 | |||||||||||
10 | C2CC | Clear the MIS.C2CC mask.
|
WO | 0 | |||||||||||
9 | C1CC | Clear the MIS.C1CC mask.
|
WO | 0 | |||||||||||
8 | C0CC | Clear the MIS.C0CC mask.
|
WO | 0 | |||||||||||
7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||
6 | FAULT | Clear the MIS.FAULT mask.
|
WO | 0 | |||||||||||
5 | IDX | Clear the MIS.IDX mask.
|
WO | 0 | |||||||||||
4 | DIRCHNG | Clear the MIS.DIRCHNG mask.
|
WO | 0 | |||||||||||
3 | CNTRCHNG | Clear the MIS.CNTRCHNG mask.
|
WO | 0 | |||||||||||
2 | DBLTRANS | Clear the MIS.DBLTRANS mask.
|
WO | 0 | |||||||||||
1 | ZERO | Clear the MIS.ZERO mask.
|
WO | 0 | |||||||||||
0 | TGT | Clear the MIS.TGT mask.
|
WO | 0 |
Address Offset | 0x0000 0084 | ||
Physical Address | 0x4006 3084 | Instance | 0x4006 3084 |
Description | Debug control This register can be used to freeze the timer when CPU halts when HALT is set to 1. When HALT is set to 0, or when the CPU releases debug halt, the filters and edge detection logic is flushed and the timer starts. For setting a predefined output value during a CPU debug halt, PARK, if the timer has this register, should be configured additionally. If this timer does not have the PARK register a predefined output value during CPU halt is not possible. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
1 | CTL | Halt control. Configure when the counter shall stop upon CPU halt. This bitfield only applies if HALT = 1.
|
RW | 0 | |||||||||||
0 | HALT | Halt LGPT when CPU is halted in debug.
|
RW | 0 |
Address Offset | 0x0000 00C0 | ||
Physical Address | 0x4006 30C0 | Instance | 0x4006 30C0 |
Description | Channel 0 Configuration This register configures channel function and enables outputs. Each channel has an edge-detection circuit. The the edge-detection circuit is: - enabled while CCACT selects a capture function and CTL.MODE is different from DIS. - flushed while CCACT selects a capture function and CTL.MODE is changed from DIS to another mode. The flush action uses two system clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit. The channel input signal enters the edge-detection circuit. False capture events can occur when: - the edge-detection circuit contains expired signal samples and the circuit is enabled without flush as described above. - the CCACT field is reconfigured while CTL.MODE is different from DIS. Primary use scenario is to select CCACT before starting the timer. Follow these steps to configure CCACT to a capture action while CTL.MODE is different from DIS: - Set EDGE to NONE. - Configure CCACT. - Wait for three system clock periods before setting EDGE different from NONE. These steps prevent capture events caused by expired signal values in edge-detection circuit. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||||||||||||||||||||
31:11 | RESERVED11 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
10 | OUT2 | Output 2 enable. When 0 < CCACT < 8, OUT2 becomes zero after a capture or compare event.
|
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
9 | OUT1 | Output 1 enable. When 0 < CCACT < 8, OUT1 becomes zero after a capture or compare event.
|
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
8 | OUT0 | Output 0 enable. When 0 < CCACT < 8, OUT0 becomes zero after a capture or compare event.
|
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
6 | INPUT | Select channel input.
|
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
5:4 | EDGE | Determines the edge that triggers the channel input event. This happens post filter.
|
RW | 0b00 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
3:0 | CCACT | Capture-Compare action. Capture-Compare action defines 15 different channel functions that utilize capture, compare, and zero events. In every compare event the timer looks at the current value of CNTR. The corresponding output event will be set 1 timer period after CNTR = C0CC.
|
RW | 0x0 |
Address Offset | 0x0000 00C4 | ||
Physical Address | 0x4006 30C4 | Instance | 0x4006 30C4 |
Description | Channel 1 Configuration This register configures channel function and enables outputs. Each channel has an edge-detection circuit. The the edge-detection circuit is: - enabled while CCACT selects a capture function and CTL.MODE is different from DIS. - flushed while CCACT selects a capture function and CTL.MODE is changed from DIS to another mode. The flush action uses two system clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit. The channel input signal enters the edge-detection circuit. False capture events can occur when: - the edge-detection circuit contains expired signal samples and the circuit is enabled without flush as described above. - the CCACT field is reconfigured while CTL.MODE is different from DIS. Primary use scenario is to select CCACT before starting the timer. Follow these steps to configure CCACT to a capture action while CTL.MODE is different from DIS: - Set EDGE to NONE. - Configure CCACT. - Wait for three system clock periods before setting EDGE different from NONE. These steps prevent capture events caused by expired signal values in edge-detection circuit. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||||||||||||||||||||
31:11 | RESERVED11 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
10 | OUT2 | Output 2 enable. When 0 < CCACT < 8, OUT2 becomes zero after a capture or compare event.
|
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
9 | OUT1 | Output 1 enable. When 0 < CCACT < 8, OUT1 becomes zero after a capture or compare event.
|
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
8 | OUT0 | Output 0 enable. When 0 < CCACT < 8, OUT0 becomes zero after a capture or compare event.
|
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
6 | INPUT | Select channel input.
|
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
5:4 | EDGE | Determines the edge that triggers the channel input event. This happens post filter.
|
RW | 0b00 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
3:0 | CCACT | Capture-Compare action. Capture-Compare action defines 15 different channel functions that utilize capture, compare, and zero events. In every compare event the timer looks at the current value of CNTR. The corresponding output event will be set 1 timer period after CNTR = C1CC.
|
RW | 0x0 |
Address Offset | 0x0000 00C8 | ||
Physical Address | 0x4006 30C8 | Instance | 0x4006 30C8 |
Description | Channel 2 Configuration This register configures channel function and enables outputs. Each channel has an edge-detection circuit. The the edge-detection circuit is: - enabled while CCACT selects a capture function and CTL.MODE is different from DIS. - flushed while CCACT selects a capture function and CTL.MODE is changed from DIS to another mode. The flush action uses two system clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit. The channel input signal enters the edge-detection circuit. False capture events can occur when: - the edge-detection circuit contains expired signal samples and the circuit is enabled without flush as described above. - the CCACT field is reconfigured while CTL.MODE is different from DIS. Primary use scenario is to select CCACT before starting the timer. Follow these steps to configure CCACT to a capture action while CTL.MODE is different from DIS: - Set EDGE to NONE. - Configure CCACT. - Wait for three system clock periods before setting EDGE different from NONE. These steps prevent capture events caused by expired signal values in edge-detection circuit. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||||||||||||||||||||
31:11 | RESERVED11 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
10 | OUT2 | Output 2 enable. When 0 < CCACT < 8, OUT2 becomes zero after a capture or compare event.
|
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
9 | OUT1 | Output 1 enable. When 0 < CCACT < 8, OUT1 becomes zero after a capture or compare event.
|
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
8 | OUT0 | Output 0 enable. When 0 < CCACT < 8, OUT0 becomes zero after a capture or compare event.
|
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
6 | INPUT | Select channel input.
|
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
5:4 | EDGE | Determines the edge that triggers the channel input event. This happens post filter.
|
RW | 0b00 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
3:0 | CCACT | Capture-Compare action. Capture-Compare action defines 15 different channel functions that utilize capture, compare, and zero events. In every compare event the timer looks at the current value of CNTR. The corresponding output event will be set 1 timer period after CNTR = C2CC.
|
RW | 0x0 |
Address Offset | 0x0000 00FC | ||
Physical Address | 0x4006 30FC | Instance | 0x4006 30FC |
Description | Pipeline Target A read or write to this register will clear the RIS.ZERO and RIS.TGT interrupt. If CTL.MODE != QDEC. Target value for next counter period. The timer will copy PTGT.VAL to TGT.VAL on the upcoming CNTR zero crossing only if PTGT.VAL has been written. The copy does not happen when restarting the timer. This is useful to avoid period jitter in PWM applications with time-varying period, sometimes referenced as phase corrected PWM. If CTL.MODE = QDEC The CNTR value is updated with VALUE on IDX if the counter is counting down. If the counter is counting up, CNTR is loaded with zero on IDX. In this mode the VALUE is not loaded into TGT on zero crossing. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 | ||
23:0 | VAL | The pipleline target value. | RW | 0x00 0000 |
Address Offset | 0x0000 0100 | ||
Physical Address | 0x4006 3100 | Instance | 0x4006 3100 |
Description | Pipeline Channel 0 Capture Compare | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 | ||
23:0 | VAL | Pipeline Capture Compare value. User defined pipeline compare value or channel-updated capture value. A read or write to this register will clear the RIS.C0CC interrupt. Compare mode: An update of VAL will be transferred to C0CC.VAL when the next CNTR.VAL is zero and CTL.MODE is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal. Capture mode: When C0CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of the low or high phase of the selected signal. This is specified by C0CFG.EDGE. |
RW | 0x00 0000 |
Address Offset | 0x0000 0104 | ||
Physical Address | 0x4006 3104 | Instance | 0x4006 3104 |
Description | Pipeline Channel 1 Capture Compare | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 | ||
23:0 | VAL | Pipeline Capture Compare value. User defined pipeline compare value or channel-updated capture value. A read or write to this register will clear the RIS.C1CC interrupt. Compare mode: An update of VAL will be transferred to C1CC.VAL when the next CNTR.VAL is zero and CTL.MODE is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal. Capture mode: When C1CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of the low or high phase of the selected signal. This is specified by C1CFG.EDGE. |
RW | 0x00 0000 |
Address Offset | 0x0000 0108 | ||
Physical Address | 0x4006 3108 | Instance | 0x4006 3108 |
Description | Pipeline Channel 2 Capture Compare | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 | ||
23:0 | VAL | Pipeline Capture Compare value. User defined pipeline compare value or channel-updated capture value. A read or write to this register will clear the RIS.C2CC interrupt. Compare mode: An update of VAL will be transferred to C2CC.VAL when the next CNTR.VAL is zero and CTL.MODE is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal. Capture mode: When C2CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of the low or high phase of the selected signal. This is specified by C2CFG.EDGE. |
RW | 0x00 0000 |
Address Offset | 0x0000 013C | ||
Physical Address | 0x4006 313C | Instance | 0x4006 313C |
Description | Target User defined counter target. A read or write to this register will clear the RIS.ZERO and RIS.TGT interrupt. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 | ||
23:0 | VAL | User defined counter target value. | RW | 0xFF FFFF |
Address Offset | 0x0000 0140 | ||
Physical Address | 0x4006 3140 | Instance | 0x4006 3140 |
Description | Channel 0 Capture Compare | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 | ||
23:0 | VAL | Capture Compare value. User defined compare value or channel-updated capture value. A read or write to this register will clear the RIS.C0CC interrupt. Compare mode: VAL is compared against CNTR.VAL and an event is generated as specified by C0CFG.CCACT when these are equal. Capture mode: The current counter value is stored in VAL when a capture event occurs. C0CFG.CCACT determines if VAL is a signal period or a regular capture value. |
RW | 0x00 0000 |
Address Offset | 0x0000 0144 | ||
Physical Address | 0x4006 3144 | Instance | 0x4006 3144 |
Description | Channel 1 Capture Compare | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 | ||
23:0 | VAL | Capture Compare value. User defined compare value or channel-updated capture value. A read or write to this register will clear the RIS.C1CC interrupt. Compare mode: VAL is compared against CNTR.VAL and an event is generated as specified by C1CFG.CCACT when these are equal. Capture mode: The current counter value is stored in VAL when a capture event occurs. C1CFG.CCACT determines if VAL is a signal period or a regular capture value. |
RW | 0x00 0000 |
Address Offset | 0x0000 0148 | ||
Physical Address | 0x4006 3148 | Instance | 0x4006 3148 |
Description | Channel 2 Capture Compare | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 | ||
23:0 | VAL | Capture Compare value. User defined compare value or channel-updated capture value. A read or write to this register will clear the RIS.C2CC interrupt. Compare mode: VAL is compared against CNTR.VAL and an event is generated as specified by C2CFG.CCACT when these are equal. Capture mode: The current counter value is stored in VAL when a capture event occurs. C2CFG.CCACT determines if VAL is a signal period or a regular capture value. |
RW | 0x00 0000 |
Address Offset | 0x0000 017C | ||
Physical Address | 0x4006 317C | Instance | 0x4006 317C |
Description | Pipeline Target No Clear Use this register to read or write to PTGT without clearing the RIS.ZERO and RIS.TGT interrupt. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 | ||
23:0 | VAL | A read or write to this register will not clear the RIS.TGT interrupt. If CTL.MODE != QDEC. Target value for next counter period. The timer copies VAL to TGT.VAL when CNTR.VAL becomes 0. The copy does not happen when restarting the timer. This is useful to avoid period jitter in PWM applications with time-varying period, sometimes referenced as phase corrected PWM. If CTL.MODE = QDEC. The CNTR.VAL is updated with VAL on IDX. VAL is not loaded into TGT.VAL when CNTR.VAL becomes 0. |
RW | 0x00 0000 |
Address Offset | 0x0000 0180 | ||
Physical Address | 0x4006 3180 | Instance | 0x4006 3180 |
Description | Pipeline Channel 0 Capture Compare No Clear | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 | ||
23:0 | VAL | Pipeline Capture Compare value. User defined pipeline compare value or channel-updated capture value. A read or write to this register will not clear the RIS.C0CC interrupt. Compare mode: An update of VAL will be transferred to C0CC.VAL when the next CNTR.VAL is zero and CTL.MODE is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal. Capture mode: When C0CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of the low or high phase of the selected signal. This is specified by C0CFG.EDGE. |
RW | 0x00 0000 |
Address Offset | 0x0000 0184 | ||
Physical Address | 0x4006 3184 | Instance | 0x4006 3184 |
Description | Pipeline Channel 1 Capture Compare No Clear | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 | ||
23:0 | VAL | Pipeline Capture Compare value. User defined pipeline compare value or channel-updated capture value. A read or write to this register will not clear the RIS.C1CC interrupt. Compare mode: An update of VAL will be transferred to C1CC.VAL when the next CNTR.VAL is zero and CTL.MODE is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal. Capture mode: When C1CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of the low or high phase of the selected signal. This is specified by C1CFG.EDGE. |
RW | 0x00 0000 |
Address Offset | 0x0000 0188 | ||
Physical Address | 0x4006 3188 | Instance | 0x4006 3188 |
Description | Pipeline Channel 2 Capture Compare No Clear | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 | ||
23:0 | VAL | Pipeline Capture Compare value. User defined pipeline compare value or channel-updated capture value. A read or write to this register will not clear the RIS.C2CC interrupt. Compare mode: An update of VAL will be transferred to C2CC.VAL when the next CNTR.VAL is zero and CTL.MODE is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal. Capture mode: When C2CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of the low or high phase of the selected signal. This is specified by C2CFG.EDGE. |
RW | 0x00 0000 |
Address Offset | 0x0000 01BC | ||
Physical Address | 0x4006 31BC | Instance | 0x4006 31BC |
Description | Target No Clear Use this register to read or write to TGT without clearing the RIS.ZERO and RIS.TGT interrupt. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 | ||
23:0 | VAL | User defined counter target value. | RW | 0xFF FFFF |
Address Offset | 0x0000 01C0 | ||
Physical Address | 0x4006 31C0 | Instance | 0x4006 31C0 |
Description | Channel 0 Capture Compare No Clear | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 | ||
23:0 | VAL | Capture Compare value. User defined compare value or channel-updated capture value. A read or write to this register will not clear the RIS.C0CC interrupt. Compare mode: VAL is compared against CNTR.VAL and an event is generated as specified by C0CFG.CCACT when these are equal. Capture mode: The current counter value is stored in VAL when a capture event occurs. C0CFG.CCACT determines if VAL is a signal period or a regular capture value. |
RW | 0x00 0000 |
Address Offset | 0x0000 01C4 | ||
Physical Address | 0x4006 31C4 | Instance | 0x4006 31C4 |
Description | Channel 1 Capture Compare No Clear | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 | ||
23:0 | VAL | Capture Compare value. User defined compare value or channel-updated capture value. A read or write to this register will not clear the RIS.C1CC interrupt. Compare mode: VAL is compared against CNTR.VAL and an event is generated as specified by C1CFG.CCACT when these are equal. Capture mode: The current counter value is stored in VAL when a capture event occurs. C1CFG.CCACT determines if VAL is a signal period or a regular capture value. |
RW | 0x00 0000 |
Address Offset | 0x0000 01C8 | ||
Physical Address | 0x4006 31C8 | Instance | 0x4006 31C8 |
Description | Channel 2 Capture Compare No Clear | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 | ||
23:0 | VAL | Capture Compare value. User defined compare value or channel-updated capture value. A read or write to this register will not clear the RIS.C2CC interrupt. Compare mode: VAL is compared against CNTR.VAL and an event is generated as specified by C2CFG.CCACT when these are equal. Capture mode: The current counter value is stored in VAL when a capture event occurs. C2CFG.CCACT determines if VAL is a signal period or a regular capture value. |
RW | 0x00 0000 |
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