IAR Cortex-M4 Timing Benchmarks

Target Platform: ti.platforms.simplelink:CC3200:1

Tool Chain Version: 8.20.2.58

BIOS Version: bios_6_55_00_05_eng

XDCTools Version: xdctools_3_50_05_11_core_eng

Benchmark	Cycles
Interrupt Latency	145
Hwi_restore()	14
Hwi_disable()	16
Hwi dispatcher prolog	121
Hwi dispatcher epilog	251
Hwi dispatcher	363
Hardware Interrupt to Blocked Task	650
Hardware Interrupt to Software Interrupt	397
Swi_enable()	73
Swi_disable()	20
Post Software Interrupt Again	24
Post Software Interrupt without Context Switch	105
Post Software Interrupt with Context Switch	210
Create a New Task without Context Switch	2581
Set a Task Priority without a Context Switch	196
Task_yield()	272
Post Semaphore No Waiting Task	79
Post Semaphore No Task Switch	238
Post Semaphore with Task Switch	339
Pend on Semaphore No Context Switch	76
Pend on Semaphore with Task Switch	347
Clock_getTicks()	14
POSIX Create a New Task without Context Switch	4605
POSIX Set a Task Priority without a Context Switch	255
POSIX Post Semaphore No Waiting Task	100
POSIX Post Semaphore No Task Switch	257
POSIX Post Semaphore with Task Switch	346
POSIX Pend on Semaphore No Context Switch	61
POSIX Pend on Semaphore with Task Switch	345

The M4 target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi CDOCs for details.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.