IAR Cortex-M3 Timing Benchmarks
Target Platform: ti.platforms.simplelink:CC1350:1
Tool Chain Version: 8.20.2.58
BIOS Version: bios_6_55_00_05_eng
XDCTools Version: xdctools_3_50_05_12_core
Benchmark | Cycles |
---|---|
Interrupt Latency | 156 |
Hwi_restore() | 14 |
Hwi_disable() | 17 |
Hwi dispatcher prolog | 120 |
Hwi dispatcher epilog | 205 |
Hwi dispatcher | 314 |
Hardware Interrupt to Blocked Task | 539 |
Hardware Interrupt to Software Interrupt | 387 |
Swi_enable() | 76 |
Swi_disable() | 17 |
Post Software Interrupt Again | 36 |
Post Software Interrupt without Context Switch | 101 |
Post Software Interrupt with Context Switch | 212 |
Create a New Task without Context Switch | 4637 |
Set a Task Priority without a Context Switch | 202 |
Task_yield() | 212 |
Post Semaphore No Waiting Task | 60 |
Post Semaphore No Task Switch | 202 |
Post Semaphore with Task Switch | 266 |
Pend on Semaphore No Context Switch | 71 |
Pend on Semaphore with Task Switch | 300 |
Clock_getTicks() | 197 |
POSIX Create a New Task without Context Switch | 7520 |
POSIX Set a Task Priority without a Context Switch | 281 |
POSIX Post Semaphore No Waiting Task | 75 |
POSIX Post Semaphore No Task Switch | 215 |
POSIX Post Semaphore with Task Switch | 277 |
POSIX Pend on Semaphore No Context Switch | 85 |
POSIX Pend on Semaphore with Task Switch | 313 |
The M3 target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi cdocs for details.
See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.