111 #ifndef ti_drivers_UDMACC26XX__include 112 #define ti_drivers_UDMACC26XX__include 124 #include <ti/devices/DeviceFamily.h> 125 #include DeviceFamily_constructPath(inc/hw_types.h) 126 #include DeviceFamily_constructPath(driverlib/udma.h) 157 #ifndef UDMACC26XX_CONFIG_BASE 158 #define UDMACC26XX_CONFIG_BASE 0x20000400 162 #if(UDMACC26XX_CONFIG_BASE & 0x3FF) 163 #error "Base address for DMA control table 'UDMACC26XX_CONFIG_BASE' must be 1024 bytes aligned." 167 #if defined(__IAR_SYSTEMS_ICC__) 168 #define ALLOCATE_CONTROL_TABLE_ENTRY(ENTRY_NAME, CHANNEL_INDEX) \ 169 __no_init static volatile tDMAControlTable ENTRY_NAME @ UDMACC26XX_CONFIG_BASE + CHANNEL_INDEX * sizeof(tDMAControlTable) 170 #elif defined(__TI_COMPILER_VERSION__) 171 #define ALLOCATE_CONTROL_TABLE_ENTRY(ENTRY_NAME, CHANNEL_INDEX) \ 172 PRAGMA(LOCATION( ENTRY_NAME , UDMACC26XX_CONFIG_BASE + CHANNEL_INDEX * sizeof(tDMAControlTable) );)\ 173 static volatile tDMAControlTable ENTRY_NAME 174 #define PRAGMA(x) _Pragma(#x) 175 #elif defined(__GNUC__) 176 #define ALLOCATE_CONTROL_TABLE_ENTRY(ENTRY_NAME, CHANNEL_INDEX) \ 177 extern int UDMACC26XX_ ## ENTRY_NAME ## _is_placed; __attribute__ ((section("."#ENTRY_NAME))) static volatile tDMAControlTable ENTRY_NAME = {&UDMACC26XX_ ## ENTRY_NAME ## _is_placed} 179 #error "don't know how to define ALLOCATE_CONTROL_TABLE_ENTRY for this toolchain" 183 #define UDMACC26XX_SET_TRANSFER_SIZE(SIZE) (((SIZE - 1) << UDMA_XFER_SIZE_S) & UDMA_XFER_SIZE_M) 185 #define UDMACC26XX_GET_TRANSFER_SIZE(CONTROL) (((CONTROL & UDMA_XFER_SIZE_M) >> UDMA_XFER_SIZE_S) + 1) 262 object->isOpen =
false;
303 HWREG(hwAttrs->
baseAddr + UDMA_O_SETCHANNELEN) = channelBitMask;
332 return (uDMAIntStatus(hwAttrs->
baseAddr) & channelBitMask) ?
true :
false;
360 uDMAIntClear(hwAttrs->
baseAddr, channelBitMask);
388 uDMAChannelDisable(hwAttrs->
baseAddr, channelBitMask);
bool isOpen
Definition: UDMACC26XX.h:191
HwiP_Struct hwi
Definition: UDMACC26XX.h:192
void UDMACC26XX_hwiIntFxn(uintptr_t callbacks)
PowerCC26XX_Resource powerMngrId
Definition: UDMACC26XX.h:200
void UDMACC26XX_close(UDMACC26XX_Handle handle)
Function to close the DMA driver.
__STATIC_INLINE void UDMACC26XX_clearInterrupt(UDMACC26XX_Handle handle, uint32_t channelBitMask)
Definition: UDMACC26XX.h:352
__STATIC_INLINE void UDMACC26XX_channelEnable(UDMACC26XX_Handle handle, uint32_t channelBitMask)
Definition: UDMACC26XX.h:295
uint8_t intNum
Definition: UDMACC26XX.h:201
__STATIC_INLINE void UDMACC26XX_init(UDMACC26XX_Handle handle)
Function to initialize the CC26XX DMA driver.
Definition: UDMACC26XX.h:254
UDMACC26XX Global configuration.
Definition: UDMACC26XX.h:229
Power manager interface for CC26XX/CC13XX.
struct UDMACC26XX_Object UDMACC26XX_Object
UDMACC26XX object.
UDMACC26XX_Handle UDMACC26XX_open()
Function to initialize the CC26XX DMA peripheral.
struct UDMACC26XX_Config UDMACC26XX_Config
UDMACC26XX Global configuration.
UDMACC26XX hardware attributes.
Definition: UDMACC26XX.h:198
void * object
Definition: UDMACC26XX.h:230
uint8_t intPriority
UDMACC26XX error interrupt priority. intPriority is the DMA peripheral's interrupt priority...
Definition: UDMACC26XX.h:223
__STATIC_INLINE void UDMACC26XX_channelDisable(UDMACC26XX_Handle handle, uint32_t channelBitMask)
Definition: UDMACC26XX.h:380
__STATIC_INLINE bool UDMACC26XX_channelDone(UDMACC26XX_Handle handle, uint32_t channelBitMask)
Definition: UDMACC26XX.h:324
uint32_t baseAddr
Definition: UDMACC26XX.h:199
UDMACC26XX object.
Definition: UDMACC26XX.h:190
struct UDMACC26XX_Config * UDMACC26XX_Handle
A handle that is returned from a UDMACC26XX_open() call.
Definition: UDMACC26XX.h:237
void const * hwAttrs
Definition: UDMACC26XX.h:231
struct UDMACC26XX_HWAttrs UDMACC26XX_HWAttrs
UDMACC26XX hardware attributes.