Instance: CPU_SCB
Component: CPU_SCS
Base address: 0xE000ED00
Cortex-M's System Control Block (SCB)
|
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
|
RO |
32 |
0x410F D214 |
0x0000 0000 |
0xE000 ED00 |
|
|
RW |
32 |
0b0000 X0X0 0000 0000 0000 0000 0000 0000 |
0x0000 0004 |
0xE000 ED04 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0008 |
0xE000 ED08 |
|
|
RW |
32 |
0xFA05 0000 |
0x0000 000C |
0xE000 ED0C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0010 |
0xE000 ED10 |
|
|
RW |
32 |
0x0000 0001 |
0x0000 0014 |
0xE000 ED14 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0018 |
0xE000 ED18 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 001C |
0xE000 ED1C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0020 |
0xE000 ED20 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0024 |
0xE000 ED24 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0028 |
0xE000 ED28 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 002C |
0xE000 ED2C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0030 |
0xE000 ED30 |
|
|
RW |
32 |
0xXXXX XXXX |
0x0000 0034 |
0xE000 ED34 |
|
|
RW |
32 |
0xXXXX XXXX |
0x0000 0038 |
0xE000 ED38 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 003C |
0xE000 ED3C |
|
|
RO |
32 |
0x0000 0030 |
0x0000 0040 |
0xE000 ED40 |
|
|
RO |
32 |
0x0000 0210 |
0x0000 0044 |
0xE000 ED44 |
|
|
RO |
32 |
0x0010 0000 |
0x0000 0048 |
0xE000 ED48 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 004C |
0xE000 ED4C |
|
|
RO |
32 |
0x0010 0030 |
0x0000 0050 |
0xE000 ED50 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 0054 |
0xE000 ED54 |
|
|
RO |
32 |
0x0100 0000 |
0x0000 0058 |
0xE000 ED58 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 005C |
0xE000 ED5C |
|
|
RO |
32 |
0x0110 1110 |
0x0000 0060 |
0xE000 ED60 |
|
|
RO |
32 |
0x0211 2000 |
0x0000 0064 |
0xE000 ED64 |
|
|
RO |
32 |
0x2123 2231 |
0x0000 0068 |
0xE000 ED68 |
|
|
RO |
32 |
0x0111 1131 |
0x0000 006C |
0xE000 ED6C |
|
|
RO |
32 |
0x0131 0132 |
0x0000 0070 |
0xE000 ED70 |
| Address Offset | 0x0000 0000 | ||
| Physical Address | 0xE000 ED00 | Instance | 0xE000 ED00 |
| Description | CPUID Base This register determines the ID number of the processor core, the version number of the processor core and the implementation details of the processor core. |
||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | IMPLEMENTER | Implementor code. | RO | 0x41 | ||
| 23:20 | VARIANT | Implementation defined variant number. | RO | 0x0 | ||
| 19:16 | CONSTANT | Reads as 0xF | RO | 0xF | ||
| 15:4 | PARTNO | Number of processor within family. | RO | 0xD21 | ||
| 3:0 | REVISION | Implementation defined revision number. | RO | 0x4 | ||
| Address Offset | 0x0000 0004 | ||
| Physical Address | 0xE000 ED04 | Instance | 0xE000 ED04 |
| Description | Interrupt Control State This register is used to set a pending Non-Maskable Interrupt (NMI), set or clear a pending SVC, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, and check the vector number of the active exception. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31 | NMIPENDSET | Set pending NMI bit. Setting this bit pends and activates an NMI. Because NMI is the highest-priority interrupt, it takes effect as soon as it registers. 0: No action 1: Set pending NMI |
RW | 0 | ||
| 30 | PENDNMICLR | Pend NMI clear. Allows the NMI exception pending state to be cleared. 0x0 No effect. 0x1 Clear pending status. |
RW | 0 | ||
| 29 | RESERVED29 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0 | ||
| 28 | PENDSVSET | Set pending pendSV bit. 0: No action 1: Set pending PendSV |
RW | 0 | ||
| 27 | PENDSVCLR | Clear pending pendSV bit 0: No action 1: Clear pending pendSV |
WO | X | ||
| 26 | PENDSTSET | Set a pending SysTick bit. 0: No action 1: Set pending SysTick |
RW | 0 | ||
| 25 | PENDSTCLR | Clear pending SysTick bit 0: No action 1: Clear pending SysTick |
WO | X | ||
| 24 | STTNS | SysTick Targets Non-secure. Controls whether in a single SysTick implementation, the SysTick is Secure or Non-secure. 0x0 SysTick is Secure. 0x1 SysTick is Non-secure. |
RO | 0 | ||
| 23 | ISRPREEMPT | This field can only be used at debug time. It indicates that a pending interrupt is to be taken in the next running cycle. If DHCSR.C_MASKINTS= 0, the interrupt is serviced. 0: A pending exception is not serviced. 1: A pending exception is serviced on exit from the debug halt state |
RO | 0 | ||
| 22 | ISRPENDING | Interrupt pending flag. Excludes NMI and faults. 0x0: Interrupt not pending 0x1: Interrupt pending |
RO | 0 | ||
| 21 | RESERVED21 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| 20:12 | VECTPENDING | Pending ISR number field. This field contains the interrupt number of the highest priority pending ISR. | RO | 0b0 0000 0000 | ||
| 11 | RETTOBASE | Indicates whether there are preempted active exceptions: 0: There are preempted active exceptions to execute 1: There are no active exceptions, or the currently-executing exception is the only active exception. |
RO | 0 | ||
| 10:9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
| 8:0 | VECTACTIVE | Active ISR number field. Reset clears this field. | RO | 0b0 0000 0000 | ||
| Address Offset | 0x0000 0008 | ||
| Physical Address | 0xE000 ED08 | Instance | 0xE000 ED08 |
| Description | Vector Table Offset This register is used to relocated the vector table base address. The vector table base offset determines the offset from the bottom of the memory map. The two most significant bits and the seven least significant bits of the vector table base offset must be 0. The portion of vector table base offset that is allowed to change is TBLOFF. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:7 | TBLOFF | Bits 31 down to 7 of the vector table base offset. | RW | 0b0 0000 0000 0000 0000 0000 0000 | ||
| 6:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0b000 0000 | ||
| Address Offset | 0x0000 000C | ||
| Physical Address | 0xE000 ED0C | Instance | 0xE000 ED0C |
| Description | Application Interrupt/Reset Control This register is used to determine data endianness, clear all active state information for debug or to recover from a hard failure, execute a system reset, alter the priority grouping position (binary point). |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | |||||||||||
| 31:16 | VECTKEY | Register key. Writing to this register (AIRCR) requires 0x05FA in VECTKEY. Otherwise the write value is ignored. Read always returns 0xFA05. | RW | 0xFA05 | |||||||||||
| 15 | ENDIANESS | Data endianness bit
|
RO | 0 | |||||||||||
| 14 | PRIS | Prioritize Secure exceptions. The value of this bit defines whether Secure exception priority boosting is enabled. |
RO | 0 | |||||||||||
| 13 | BFHFNMINS | BusFault, HardFault, and NMI Non-secure enable. The value of this bit defines whether BusFault and NMI exceptions are Non-secure, and whether exceptions target the Non-secure HardFault exception 0x0 BusFault, HardFault, and NMI are Secure. 0x1 BusFault and NMI are Non-secure and exceptions can target Non-secure HardFault. |
RW | 0 | |||||||||||
| 12:11 | RESERVED11 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | |||||||||||
| 10:8 | PRIGROUP | Interrupt priority grouping field. This field is a binary point position indicator for creating subpriorities for exceptions that share the same pre-emption level. It divides the PRI_n field in the Interrupt Priority Registers (NVIC_IPR0, NVIC_IPR1,..., and NVIC_IPR8) into a pre-emption level and a subpriority level. The binary point is a left-of value. This means that the PRIGROUP value represents a point starting at the left of the Least Significant Bit (LSB). The lowest value might not be 0 depending on the number of bits allocated for priorities, and implementation choices. | RW | 0b000 | |||||||||||
| 7:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x0 | |||||||||||
| 3 | SYSRESETREQS | System reset request Secure only. The value of this bit defines whether the SYSRESETREQ bit is functional for Non-secure use |
RW | 0 | |||||||||||
| 2 | SYSRESETREQ | Requests a warm reset. Setting this bit does not prevent Halting Debug from running. | WO | 0 | |||||||||||
| 1 | VECTCLRACTIVE | Clears all active state information for active NMI, fault, and interrupts. It is the responsibility of the application to reinitialize the stack. This bit is for returning to a known state during debug. The bit self-clears. IPSR is not cleared by this operation. So, if used by an application, it must only be used at the base level of activation, or within a system handler whose active bit can be set. | WO | 0 | |||||||||||
| 0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | WO | 0 | |||||||||||
| Address Offset | 0x0000 0010 | ||
| Physical Address | 0xE000 ED10 | Instance | 0xE000 ED10 |
| Description | System Control This register is used for power-management functions, i.e., signaling to the system when the processor can enter a low power state, controlling how the processor enters and exits low power states. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | |||||||||||
| 31:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0b000 0000 0000 0000 0000 0000 0000 | |||||||||||
| 4 | SEVONPEND | Send Event on Pending bit: 0: Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded 1: Enabled events and all interrupts, including disabled interrupts, can wakeup the processor. When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of an SEV instruction. |
RW | 0 | |||||||||||
| 3 | SLEEPDEEPS | Sleep deep secure. This field controls whether the SLEEPDEEP bit is only accessible from the Secure state | RW | 0 | |||||||||||
| 2 | SLEEPDEEP | Controls whether the processor uses sleep or deep sleep as its low power mode
|
RW | 0 | |||||||||||
| 1 | SLEEPONEXIT | Sleep on exit when returning from Handler mode to Thread mode. Enables interrupt driven applications to avoid returning to empty main application. 0: Do not sleep when returning to thread mode 1: Sleep on ISR exit |
RW | 0 | |||||||||||
| 0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0 | |||||||||||
| Address Offset | 0x0000 0014 | ||
| Physical Address | 0xE000 ED14 | Instance | 0xE000 ED14 |
| Description | Configuration Control This register is used to enable NMI, HardFault and FAULTMASK to ignore bus fault, trap divide by zero and unaligned accesses, enable user access to the Software Trigger Interrupt Register (STIR), control entry to Thread Mode. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:10 | RESERVED10 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0b00 0000 0000 0000 0000 0000 | ||
| 9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| 8 | BFHFNMIGN | Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions. This applies to the HardFault, NMI, and FAULTMASK escalated handlers: 0: Data BusFaults caused by load and store instructions cause a lock-up 1: Data BusFaults caused by load and store instructions are ignored. Set this bit to 1 only when the handler and its data are in absolutely safe memory. The normal use of this bit is to probe system devices and bridges to detect problems. |
RW | 0 | ||
| 7:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0b000 | ||
| 4 | DIV_0_TRP | Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0: 0: Do not trap divide by 0. In this mode, a divide by zero returns a quotient of 0. 1: Trap divide by 0. The relevant Usage Fault Status Register bit is CFSR.DIVBYZERO. |
RW | 0 | ||
| 3 | UNALIGN_TRP | Enables unaligned access traps: 0: Do not trap unaligned halfword and word accesses 1: Trap unaligned halfword and word accesses. The relevant Usage Fault Status Register bit is CFSR.UNALIGNED. If this bit is set to 1, an unaligned access generates a UsageFault. Unaligned LDM, STM, LDRD, and STRD instructions always fault regardless of the value in UNALIGN_TRP. |
RW | 0 | ||
| 2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0 | ||
| 1 | USERSETMPEND | Enables unprivileged software access to STIR: 0: User code is not allowed to write to the Software Trigger Interrupt register (STIR). 1: User code can write the Software Trigger Interrupt register (STIR) to trigger (pend) a Main exception, which is associated with the Main stack pointer. |
RW | 0 | ||
| 0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 1 | ||
| Address Offset | 0x0000 0018 | ||
| Physical Address | 0xE000 ED18 | Instance | 0xE000 ED18 |
| Description | System Handlers 4-7 Priority This register is used to prioritize the following system handlers: Memory manage, Bus fault, and Usage fault. System Handlers are a special class of exception handler that can have their priority set to any of the priority levels. Most can be masked on (enabled) or off (disabled). When disabled, the fault is always treated as a Hard Fault. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x00 | ||
| 23:16 | PRI_6 | Priority of system handler 6. UsageFault | RW | 0x00 | ||
| 15:8 | PRI_5 | Priority of system handler 5: BusFault | RW | 0x00 | ||
| 7:0 | PRI_4 | Priority of system handler 4: MemManage | RW | 0x00 | ||
| Address Offset | 0x0000 001C | ||
| Physical Address | 0xE000 ED1C | Instance | 0xE000 ED1C |
| Description | System Handlers 8-11 Priority This register is used to prioritize the SVC handler. System Handlers are a special class of exception handler that can have their priority set to any of the priority levels. Most can be masked on (enabled) or off (disabled). When disabled, the fault is always treated as a Hard Fault. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_11 | Priority of system handler 11. SVCall | RW | 0x00 | ||
| 23:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x00 0000 | ||
| Address Offset | 0x0000 0020 | ||
| Physical Address | 0xE000 ED20 | Instance | 0xE000 ED20 |
| Description | System Handlers 12-15 Priority This register is used to prioritize the following system handlers: SysTick, PendSV and Debug Monitor. System Handlers are a special class of exception handler that can have their priority set to any of the priority levels. Most can be masked on (enabled) or off (disabled). When disabled, the fault is always treated as a Hard Fault. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_15 | Priority of system handler 15. SysTick exception | RW | 0x00 | ||
| 23:16 | PRI_14 | Priority of system handler 14. Pend SV | RW | 0x00 | ||
| 15:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x00 | ||
| 7:0 | PRI_12 | Priority of system handler 12. Debug Monitor | RW | 0x00 | ||
| Address Offset | 0x0000 0024 | ||
| Physical Address | 0xE000 ED24 | Instance | 0xE000 ED24 |
| Description | System Handler Control and State This register is used to enable or disable the system handlers, determine the pending status of bus fault, mem manage fault, and SVC, determine the active status of the system handlers. If a fault condition occurs while its fault handler is disabled, the fault escalates to a Hard Fault. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | |||||||||||
| 31:22 | RESERVED22 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0b00 0000 0000 | |||||||||||
| 21 | HARDFAULTPENDED | SecureFault exception pended state
|
RO | 0 | |||||||||||
| 20 | SECUREFAULTPENDED | SecureFault exception pended state
|
RO | 0 | |||||||||||
| 19 | SECUREFAULTENA | SecureFault exception enable.
|
RW | 0 | |||||||||||
| 18 | USGFAULTENA | Usage fault system handler enable
|
RW | 0 | |||||||||||
| 17 | BUSFAULTENA | Bus fault system handler enable
|
RW | 0 | |||||||||||
| 16 | MEMFAULTENA | MemManage fault system handler enable
|
RW | 0 | |||||||||||
| 15 | SVCALLPENDED | SVCall pending
|
RO | 0 | |||||||||||
| 14 | BUSFAULTPENDED | BusFault pending
|
RO | 0 | |||||||||||
| 13 | MEMFAULTPENDED | MemManage exception pending
|
RO | 0 | |||||||||||
| 12 | USGFAULTPENDED | Usage fault pending
|
RO | 0 | |||||||||||
| 11 | SYSTICKACT | SysTick active flag. 0x0: Not active 0x1: Active
|
RO | 0 | |||||||||||
| 10 | PENDSVACT | PendSV active 0x0: Not active 0x1: Active |
RO | 0 | |||||||||||
| 9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||
| 8 | MONITORACT | Debug monitor active
|
RO | 0 | |||||||||||
| 7 | SVCALLACT | SVCall active
|
RO | 0 | |||||||||||
| 6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||
| 5 | NMIACT | NMI exception active state
|
RO | 0 | |||||||||||
| 4 | SECUREFAULTACT | SecureFault exception active state
|
RO | 0 | |||||||||||
| 3 | USGFAULTACT | UsageFault exception active
|
RO | 0 | |||||||||||
| 2 | HARDFAULTACT | HardFault exception active state. Indicates and allows limited modification of the active state of the HardFault exception for the selected Security state
|
RO | 0 | |||||||||||
| 1 | BUSFAULTACT | BusFault exception active
|
RO | 0 | |||||||||||
| 0 | MEMFAULTACT | MemManage exception active
|
RO | 0 | |||||||||||
| Address Offset | 0x0000 0028 | ||
| Physical Address | 0xE000 ED28 | Instance | 0xE000 ED28 |
| Description | Configurable Fault Status This register is used to obtain information about local faults. These registers include three subsections: The first byte is Memory Manage Fault Status Register (MMFSR). The second byte is Bus Fault Status Register (BFSR). The higher half-word is Usage Fault Status Register (UFSR). The flags in these registers indicate the causes of local faults. Multiple flags can be set if more than one fault occurs. These register are read/write-clear. This means that they can be read normally, but writing a 1 to any bit clears that bit. The CFSR is byte accessible. CFSR or its subregisters can be accessed as follows: The following accesses are possible to the CFSR register: - access the complete register with a word access to 0xE000ED28. - access the MMFSR with a byte access to 0xE000ED28 - access the MMFSR and BFSR with a halfword access to 0xE000ED28 - access the BFSR with a byte access to 0xE000ED29 - access the UFSR with a halfword access to 0xE000ED2A. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:26 | RESERVED26 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0b00 0000 | ||
| 25 | DIVBYZERO | When CCR.DIV_0_TRP (see Configuration Control Register on page 8-26) is enabled and an SDIV or UDIV instruction is used with a divisor of 0, this fault occurs The instruction is executed and the return PC points to it. If CCR.DIV_0_TRP is not set, then the divide returns a quotient of 0. | RW | 0 | ||
| 24 | UNALIGNED | When CCR.UNALIGN_TRP is enabled, and there is an attempt to make an unaligned memory access, then this fault occurs. Unaligned LDM/STM/LDRD/STRD instructions always fault irrespective of the setting of CCR.UNALIGN_TRP. | RW | 0 | ||
| 23:20 | RESERVED20 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x0 | ||
| 19 | NOCP | Attempt to use a coprocessor instruction. The processor does not support coprocessor instructions. | RW | 0 | ||
| 18 | INVPC | Attempt to load EXC_RETURN into PC illegally. Invalid instruction, invalid context, invalid value. The return PC points to the instruction that tried to set the PC. | RW | 0 | ||
| 17 | INVSTATE | Indicates an attempt to execute in an invalid EPSR state (e.g. after a BX type instruction has changed state). This includes state change after entry to or return from exception, as well as from inter-working instructions. Return PC points to faulting instruction, with the invalid state. | RW | 0 | ||
| 16 | UNDEFINSTR | This bit is set when the processor attempts to execute an undefined instruction. This is an instruction that the processor cannot decode. The return PC points to the undefined instruction. | RW | 0 | ||
| 15 | BFARVALID | This bit is set if the Bus Fault Address Register (BFAR) contains a valid address. This is true after a bus fault where the address is known. Other faults can clear this bit, such as a Mem Manage fault occurring later. If a Bus fault occurs that is escalated to a Hard Fault because of priority, the Hard Fault handler must clear this bit. This prevents problems if returning to a stacked active Bus fault handler whose BFAR value has been overwritten. | RW | 0 | ||
| 14:13 | RESERVED13 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0b00 | ||
| 12 | STKERR | Stacking from exception has caused one or more bus faults. The SP is still adjusted and the values in the context area on the stack might be incorrect. BFAR is not written. | RW | 0 | ||
| 11 | UNSTKERR | Unstack from exception return has caused one or more bus faults. This is chained to the handler, so that the original return stack is still present. SP is not adjusted from failing return and new save is not performed. BFAR is not written. | RW | 0 | ||
| 10 | IMPRECISERR | Imprecise data bus error. It is a BusFault, but the Return PC is not related to the causing instruction. This is not a synchronous fault. So, if detected when the priority of the current activation is higher than the Bus Fault, it only pends. Bus fault activates when returning to a lower priority activation. If a precise fault occurs before returning to a lower priority exception, the handler detects both IMPRECISERR set and one of the precise fault status bits set at the same time. BFAR is not written. | RW | 0 | ||
| 9 | PRECISERR | Precise data bus error return. | RW | 0 | ||
| 8 | IBUSERR | Instruction bus error flag. This flag is set by a prefetch error. The fault stops on the instruction, so if the error occurs under a branch shadow, no fault occurs. BFAR is not written. | RW | 0 | ||
| 7 | MMARVALID | Memory Manage Address Register (MMFAR) address valid flag. A later-arriving fault, such as a bus fault, can clear a memory manage fault.. If a MemManage fault occurs that is escalated to a Hard Fault because of priority, the Hard Fault handler must clear this bit. This prevents problems on return to a stacked active MemManage handler whose MMFAR value has been overwritten. | RW | 0 | ||
| 6:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0b00 | ||
| 4 | MSTKERR | Stacking from exception has caused one or more access violations. The SP is still adjusted and the values in the context area on the stack might be incorrect. MMFAR is not written. | RW | 0 | ||
| 3 | MUNSTKERR | Unstack from exception return has caused one or more access violations. This is chained to the handler, so that the original return stack is still present. SP is not adjusted from failing return and new save is not performed. MMFAR is not written. | RW | 0 | ||
| 2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0 | ||
| 1 | DACCVIOL | Data access violation flag. Attempting to load or store at a location that does not permit the operation sets this flag. The return PC points to the faulting instruction. This error loads MMFAR with the address of the attempted access. | RW | 0 | ||
| 0 | IACCVIOL | Instruction access violation flag. Attempting to fetch an instruction from a location that does not permit execution sets this flag. This occurs on any access to an XN region, even when the MPU is disabled or not present. The return PC points to the faulting instruction. MMFAR is not written. | RW | 0 | ||
| Address Offset | 0x0000 002C | ||
| Physical Address | 0xE000 ED2C | Instance | 0xE000 ED2C |
| Description | Hard Fault Status This register is used to obtain information about events that activate the Hard Fault handler. This register is a write-clear register. This means that writing a 1 to a bit clears that bit. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31 | DEBUGEVT | This bit is set if there is a fault related to debug. This is only possible when halting debug is not enabled. For monitor enabled debug, it only happens for BKPT when the current priority is higher than the monitor. When both halting and monitor debug are disabled, it only happens for debug events that are not ignored (minimally, BKPT). The Debug Fault Status Register is updated. | RW | 0 | ||
| 30 | FORCED | Hard Fault activated because a Configurable Fault was received and cannot activate because of priority or because the Configurable Fault is disabled. The Hard Fault handler then has to read the other fault status registers to determine cause. | RW | 0 | ||
| 29:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x000 0000 | ||
| 1 | VECTTBL | This bit is set if there is a fault because of vector table read on exception processing (Bus Fault). This case is always a Hard Fault. The return PC points to the pre-empted instruction. | RW | 0 | ||
| 0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0 | ||
| Address Offset | 0x0000 0030 | ||
| Physical Address | 0xE000 ED30 | Instance | 0xE000 ED30 |
| Description | Debug Fault Status This register is used to monitor external debug requests, vector catches, data watchpoint match, BKPT instruction execution, halt requests. Multiple flags in the Debug Fault Status Register can be set when multiple fault conditions occur. The register is read/write clear. This means that it can be read normally. Writing a 1 to a bit clears that bit. Note that these bits are not set unless the event is caught. This means that it causes a stop of some sort. If halting debug is enabled, these events stop the processor into debug. If debug is disabled and the debug monitor is enabled, then this becomes a debug monitor handler call, if priority permits. If debug and the monitor are both disabled, some of these events are Hard Faults, and some are ignored. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0b000 0000 0000 0000 0000 0000 0000 | ||
| 4 | EXTERNAL | External debug request flag. The processor stops on next instruction boundary. 0x0: External debug request signal not asserted 0x1: External debug request signal asserted |
RW | 0 | ||
| 3 | VCATCH | Vector catch flag. When this flag is set, a flag in one of the local fault status registers is also set to indicate the type of fault. 0x0: No vector catch occurred 0x1: Vector catch occurred |
RW | 0 | ||
| 2 | DWTTRAP | Data Watchpoint and Trace (DWT) flag. The processor stops at the current instruction or at the next instruction. 0x0: No DWT match 0x1: DWT match |
RW | 0 | ||
| 1 | BKPT | BKPT flag. The BKPT flag is set by a BKPT instruction in flash patch code, and also by normal code. Return PC points to breakpoint containing instruction. 0x0: No BKPT instruction execution 0x1: BKPT instruction execution |
RW | 0 | ||
| 0 | HALTED | Halt request flag. The processor is halted on the next instruction. 0x0: No halt request 0x1: Halt requested by NVIC, including step |
RW | 0 | ||
| Address Offset | 0x0000 0034 | ||
| Physical Address | 0xE000 ED34 | Instance | 0xE000 ED34 |
| Description | Mem Manage Fault Address This register is used to read the address of the location that caused a Memory Manage Fault. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | ADDRESS | Mem Manage fault address field. This field is the data address of a faulted load or store attempt. When an unaligned access faults, the address is the actual address that faulted. Because an access can be split into multiple parts, each aligned, this address can be any offset in the range of the requested size. Flags CFSR.IACCVIOL, CFSR.DACCVIOL ,CFSR.MUNSTKERR and CFSR.MSTKERR in combination with CFSR.MMARVALIDindicate the cause of the fault. |
RW | 0xXXXX XXXX | ||
| Address Offset | 0x0000 0038 | ||
| Physical Address | 0xE000 ED38 | Instance | 0xE000 ED38 |
| Description | Bus Fault Address This register is used to read the address of the location that generated a Bus Fault. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | ADDRESS | Bus fault address field. This field is the data address of a faulted load or store attempt. When an unaligned access faults, the address is the address requested by the instruction, even if that is not the address that faulted. Flags CFSR.IBUSERR, CFSR.PRECISERR, CFSR.IMPRECISERR, CFSR.UNSTKERR and CFSR.STKERR in combination with CFSR.BFARVALID indicate the cause of the fault. |
RW | 0xXXXX XXXX | ||
| Address Offset | 0x0000 003C | ||
| Physical Address | 0xE000 ED3C | Instance | 0xE000 ED3C |
| Description | Auxiliary Fault Status This register is used to determine additional system fault information to software. Single-cycle high level on an auxiliary faults is latched as one. The bit can only be cleared by writing a one to the corresponding bit. Auxiliary fault inputs to the CPU are tied to 0. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | IMPDEF | Implementation defined. The bits map directly onto the signal assignment to the auxiliary fault inputs. Tied to 0 | RW | 0x0000 0000 | ||
| Address Offset | 0x0000 0040 | ||
| Physical Address | 0xE000 ED40 | Instance | 0xE000 ED40 |
| Description | Processor Feature 0 | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:4 | STATE1 | State1 (T-bit == 1) 0x0: N/A 0x1: N/A 0x2: Thumb-2 encoding with the 16-bit basic instructions plus 32-bit Buncond/BL but no other 32-bit basic instructions (Note non-basic 32-bit instructions can be added using the appropriate instruction attribute, but other 32-bit basic instructions cannot.) 0x3: Thumb-2 encoding with all Thumb-2 basic instructions |
RO | 0x3 | ||
| 3:0 | STATE0 | State0 (T-bit == 0) 0x0: No ARM encoding 0x1: N/A |
RO | 0x0 | ||
| Address Offset | 0x0000 0044 | ||
| Physical Address | 0xE000 ED44 | Instance | 0xE000 ED44 |
| Description | Processor Feature 1 | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:12 | RESERVED12 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 0000 | ||
| 11:8 | MICROCONTROLLER_PROGRAMMERS_MODEL | Microcontroller programmer's model 0x0: Not supported 0x2: Two-stack support |
RO | 0x2 | ||
| 7:4 | SECURITY | Security. Identifies whether the Security Extension is implemented | RO | 0x1 | ||
| 3:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 | ||
| Address Offset | 0x0000 0048 | ||
| Physical Address | 0xE000 ED48 | Instance | 0xE000 ED48 |
| Description | Debug Feature 0 This register provides a high level view of the debug system. Further details are provided in the debug infrastructure itself. |
||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 | ||
| 23:20 | MICROCONTROLLER_DEBUG_MODEL | Microcontroller Debug Model - memory mapped 0x0: Not supported 0x1: Microcontroller debug v1 (ITMv1 and DWTv1) |
RO | 0x1 | ||
| 19:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 0000 | ||
| Address Offset | 0x0000 004C | ||
| Physical Address | 0xE000 ED4C | Instance | 0xE000 ED4C |
| Description | Auxiliary Feature 0 This register provides some freedom for implementation defined features to be registered. Not used in Cortex-M. |
||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0050 | ||
| Physical Address | 0xE000 ED50 | Instance | 0xE000 ED50 |
| Description | Memory Model Feature 0 General information on the memory model and memory management support. |
||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0010 0030 | ||
| Address Offset | 0x0000 0054 | ||
| Physical Address | 0xE000 ED54 | Instance | 0xE000 ED54 |
| Description | Memory Model Feature 1 General information on the memory model and memory management support. |
||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0058 | ||
| Physical Address | 0xE000 ED58 | Instance | 0xE000 ED58 |
| Description | Memory Model Feature 2 General information on the memory model and memory management support. |
||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:28 | RESERVED28 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 | ||
| 27:24 | WAIT_FOR_INTERRUPT_STALLING | wait for interrupt stalling 0x0: Not supported 0x1: Wait for interrupt supported |
RO | 0x1 | ||
| 23:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| Address Offset | 0x0000 005C | ||
| Physical Address | 0xE000 ED5C | Instance | 0xE000 ED5C |
| Description | Memory Model Feature 3 General information on the memory model and memory management support. |
||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0060 | ||
| Physical Address | 0xE000 ED60 | Instance | 0xE000 ED60 |
| Description | ISA Feature 0 Information on the instruction set attributes register |
||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0110 1110 | ||
| Address Offset | 0x0000 0064 | ||
| Physical Address | 0xE000 ED64 | Instance | 0xE000 ED64 |
| Description | ISA Feature 1 Information on the instruction set attributes register |
||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0211 2000 | ||
| Address Offset | 0x0000 0068 | ||
| Physical Address | 0xE000 ED68 | Instance | 0xE000 ED68 |
| Description | ISA Feature 2 Information on the instruction set attributes register |
||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x2123 2231 | ||
| Address Offset | 0x0000 006C | ||
| Physical Address | 0xE000 ED6C | Instance | 0xE000 ED6C |
| Description | ISA Feature 3 Information on the instruction set attributes register |
||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0111 1131 | ||
| Address Offset | 0x0000 0070 | ||
| Physical Address | 0xE000 ED70 | Instance | 0xE000 ED70 |
| Description | ISA Feature 4 Information on the instruction set attributes register |
||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0131 0132 | ||
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