CPU_NVIC

Instance: CPU_NVIC
Component: CPU_NVIC
Base address: 0xE000E100


Cortex-M's Nested Vectored Interrupt Controller (NVIC)

TOP:CPU_NVIC Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

ISER0

RW

32

0x0000 0000

0x0000 0000

0xE000 E100

ISER1

RW

32

0x0000 0000

0x0000 0004

0xE000 E104

ICER0

RW

32

0x0000 0000

0x0000 0080

0xE000 E180

ICER1

RW

32

0x0000 0000

0x0000 0084

0xE000 E184

ISPR0

RW

32

0x0000 0000

0x0000 0100

0xE000 E200

ISPR1

RW

32

0x0000 0000

0x0000 0104

0xE000 E204

ICPR0

RW

32

0x0000 0000

0x0000 0180

0xE000 E280

ICPR1

RW

32

0x0000 0000

0x0000 0184

0xE000 E284

IABR0

RW

32

0x0000 0000

0x0000 0200

0xE000 E300

IABR1

RW

32

0x0000 0000

0x0000 0204

0xE000 E304

ITNS0

RW

32

0x0000 0000

0x0000 0280

0xE000 E380

ITNS1

RW

32

0x0000 0000

0x0000 0284

0xE000 E384

IPR0

RW

32

0x0000 0000

0x0000 0300

0xE000 E400

IPR1

RW

32

0x0000 0000

0x0000 0304

0xE000 E404

IPR2

RW

32

0x0000 0000

0x0000 0308

0xE000 E408

IPR3

RW

32

0x0000 0000

0x0000 030C

0xE000 E40C

IPR4

RW

32

0x0000 0000

0x0000 0310

0xE000 E410

IPR5

RW

32

0x0000 0000

0x0000 0314

0xE000 E414

IPR6

RW

32

0x0000 0000

0x0000 0318

0xE000 E418

IPR7

RW

32

0x0000 0000

0x0000 031C

0xE000 E41C

IPR8

RW

32

0x0000 0000

0x0000 0320

0xE000 E420

IPR9

RW

32

0x0000 0000

0x0000 0324

0xE000 E424

IPR10

RW

32

0x0000 0000

0x0000 0328

0xE000 E428

IPR11

RW

32

0x0000 0000

0x0000 032C

0xE000 E42C

TOP:CPU_NVIC Register Descriptions

TOP:CPU_NVIC:ISER0

Address Offset 0x0000 0000
Physical Address 0xE000 E100 Instance 0xE000 E100
Description Enables or reads the enabled state of each group of 32 interrupts
Type RW
Bits Field Name Description Type Reset
31:0 SETENA For SETENA[m] in NVIC_ISER*n, indicates whether interrupt 32*n + m is enabled RO 0x0000 0000

TOP:CPU_NVIC:ISER1

Address Offset 0x0000 0004
Physical Address 0xE000 E104 Instance 0xE000 E104
Description Enables or reads the enabled state of each group of 32 interrupts
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 SETENA For SETENA[m] in NVIC_ISER*n, indicates whether interrupt 32*n + m is enabled RO 0x0000

TOP:CPU_NVIC:ICER0

Address Offset 0x0000 0080
Physical Address 0xE000 E180 Instance 0xE000 E180
Description Clears or reads the enabled state of each group of 32 interrupts
Type RW
Bits Field Name Description Type Reset
31:0 CLRENA For CLRENA[m] in NVIC_ICER*n, indicates whether interrupt 32*n + m is enabled RO 0x0000 0000

TOP:CPU_NVIC:ICER1

Address Offset 0x0000 0084
Physical Address 0xE000 E184 Instance 0xE000 E184
Description Clears or reads the enabled state of each group of 32 interrupts
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 CLRENA For CLRENA[m] in NVIC_ICER*n, indicates whether interrupt 32*n + m is enabled RO 0x0000

TOP:CPU_NVIC:ISPR0

Address Offset 0x0000 0100
Physical Address 0xE000 E200 Instance 0xE000 E200
Description Enables or reads the pending state of each group of 32 interrupts
Type RW
Bits Field Name Description Type Reset
31:0 SETPEND For SETPEND[m] in NVIC_ISPR*n, indicates whether interrupt 32*n + m is pending RO 0x0000 0000

TOP:CPU_NVIC:ISPR1

Address Offset 0x0000 0104
Physical Address 0xE000 E204 Instance 0xE000 E204
Description Enables or reads the pending state of each group of 32 interrupts
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 SETPEND For SETPEND[m] in NVIC_ISPR*n, indicates whether interrupt 32*n + m is pending RO 0x0000

TOP:CPU_NVIC:ICPR0

Address Offset 0x0000 0180
Physical Address 0xE000 E280 Instance 0xE000 E280
Description Clears or reads the pending state of each group of 32 interrupts
Type RW
Bits Field Name Description Type Reset
31:0 CLRPEND For CLRPEND[m] in NVIC_ICPR*n, indicates whether interrupt 32*n + m is pending RO 0x0000 0000

TOP:CPU_NVIC:ICPR1

Address Offset 0x0000 0184
Physical Address 0xE000 E284 Instance 0xE000 E284
Description Clears or reads the pending state of each group of 32 interrupts
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 CLRPEND For CLRPEND[m] in NVIC_ICPR*n, indicates whether interrupt 32*n + m is pending RO 0x0000

TOP:CPU_NVIC:IABR0

Address Offset 0x0000 0200
Physical Address 0xE000 E300 Instance 0xE000 E300
Description For each group of 32 interrupts, shows the active state of each interrupt
Type RW
Bits Field Name Description Type Reset
31:0 ACTIVE For ACTIVE[m] in NVIC_IABR*n, indicates the active state for interrupt 32*n+m RO 0x0000 0000

TOP:CPU_NVIC:IABR1

Address Offset 0x0000 0204
Physical Address 0xE000 E304 Instance 0xE000 E304
Description For each group of 32 interrupts, shows the active state of each interrupt
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 ACTIVE For ACTIVE[m] in NVIC_IABR*n, indicates the active state for interrupt 32*n+m RO 0x0000

TOP:CPU_NVIC:ITNS0

Address Offset 0x0000 0280
Physical Address 0xE000 E380 Instance 0xE000 E380
Description For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state
Type RW
Bits Field Name Description Type Reset
31:0 ITNS For ITNS[m] in NVIC_ITNS*n, the target Security state for interrupt 32*n+m RW 0x0000 0000

TOP:CPU_NVIC:ITNS1

Address Offset 0x0000 0284
Physical Address 0xE000 E384 Instance 0xE000 E384
Description For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 ITNS For ITNS[m] in NVIC_ITNS*n, the target Security state for interrupt 32*n+m RW 0x0000

TOP:CPU_NVIC:IPR0

Address Offset 0x0000 0300
Physical Address 0xE000 E400 Instance 0xE000 E400
Description Sets or reads interrupt priorities
Type RW
Bits Field Name Description Type Reset
31:24 PRI_N3 For register NVIC_IPR*0, the priority of interrupt number 4*0+3, or is RES0 if the PE does not implement this interrupt RW 0x00
23:16 PRI_N2 For register NVIC_IPR*0, the priority of interrupt number 4*0+2, or is RES0 if the PE does not implement this interrupt RW 0x00
15:8 PRI_N1 For register NVIC_IPR*0, the priority of interrupt number 4*0+1, or is RES0 if the PE does not implement this interrupt RW 0x00
7:0 PRI_N0 For register NVIC_IPR*0, the priority of interrupt number 4*0+0, or is RES0 if the PE does not implement this interrupt RW 0x00

TOP:CPU_NVIC:IPR1

Address Offset 0x0000 0304
Physical Address 0xE000 E404 Instance 0xE000 E404
Description Sets or reads interrupt priorities
Type RW
Bits Field Name Description Type Reset
31:24 PRI_N3 For register NVIC_IPR*1, the priority of interrupt number 4*1+3, or is RES0 if the PE does not implement this interrupt RW 0x00
23:16 PRI_N2 For register NVIC_IPR*1, the priority of interrupt number 4*1+2, or is RES0 if the PE does not implement this interrupt RW 0x00
15:8 PRI_N1 For register NVIC_IPR*1, the priority of interrupt number 4*1+1, or is RES0 if the PE does not implement this interrupt RW 0x00
7:0 PRI_N0 For register NVIC_IPR*1, the priority of interrupt number 4*1+0, or is RES0 if the PE does not implement this interrupt RW 0x00

TOP:CPU_NVIC:IPR2

Address Offset 0x0000 0308
Physical Address 0xE000 E408 Instance 0xE000 E408
Description Sets or reads interrupt priorities
Type RW
Bits Field Name Description Type Reset
31:24 PRI_N3 For register NVIC_IPR*2, the priority of interrupt number 4*2+3, or is RES0 if the PE does not implement this interrupt RW 0x00
23:16 PRI_N2 For register NVIC_IPR*2, the priority of interrupt number 4*2+2, or is RES0 if the PE does not implement this interrupt RW 0x00
15:8 PRI_N1 For register NVIC_IPR*2, the priority of interrupt number 4*2+1, or is RES0 if the PE does not implement this interrupt RW 0x00
7:0 PRI_N0 For register NVIC_IPR*2, the priority of interrupt number 4*2+0, or is RES0 if the PE does not implement this interrupt RW 0x00

TOP:CPU_NVIC:IPR3

Address Offset 0x0000 030C
Physical Address 0xE000 E40C Instance 0xE000 E40C
Description Sets or reads interrupt priorities
Type RW
Bits Field Name Description Type Reset
31:24 PRI_N3 For register NVIC_IPR*3, the priority of interrupt number 4*3+3, or is RES0 if the PE does not implement this interrupt RW 0x00
23:16 PRI_N2 For register NVIC_IPR*3, the priority of interrupt number 4*3+2, or is RES0 if the PE does not implement this interrupt RW 0x00
15:8 PRI_N1 For register NVIC_IPR*3, the priority of interrupt number 4*3+1, or is RES0 if the PE does not implement this interrupt RW 0x00
7:0 PRI_N0 For register NVIC_IPR*3, the priority of interrupt number 4*3+0, or is RES0 if the PE does not implement this interrupt RW 0x00

TOP:CPU_NVIC:IPR4

Address Offset 0x0000 0310
Physical Address 0xE000 E410 Instance 0xE000 E410
Description Sets or reads interrupt priorities
Type RW
Bits Field Name Description Type Reset
31:24 PRI_N3 For register NVIC_IPR*4, the priority of interrupt number 4*4+3, or is RES0 if the PE does not implement this interrupt RW 0x00
23:16 PRI_N2 For register NVIC_IPR*4, the priority of interrupt number 4*4+2, or is RES0 if the PE does not implement this interrupt RW 0x00
15:8 PRI_N1 For register NVIC_IPR*4, the priority of interrupt number 4*4+1, or is RES0 if the PE does not implement this interrupt RW 0x00
7:0 PRI_N0 For register NVIC_IPR*4, the priority of interrupt number 4*4+0, or is RES0 if the PE does not implement this interrupt RW 0x00

TOP:CPU_NVIC:IPR5

Address Offset 0x0000 0314
Physical Address 0xE000 E414 Instance 0xE000 E414
Description Sets or reads interrupt priorities
Type RW
Bits Field Name Description Type Reset
31:24 PRI_N3 For register NVIC_IPR*5, the priority of interrupt number 4*5+3, or is RES0 if the PE does not implement this interrupt RW 0x00
23:16 PRI_N2 For register NVIC_IPR*5, the priority of interrupt number 4*5+2, or is RES0 if the PE does not implement this interrupt RW 0x00
15:8 PRI_N1 For register NVIC_IPR*5, the priority of interrupt number 4*5+1, or is RES0 if the PE does not implement this interrupt RW 0x00
7:0 PRI_N0 For register NVIC_IPR*5, the priority of interrupt number 4*5+0, or is RES0 if the PE does not implement this interrupt RW 0x00

TOP:CPU_NVIC:IPR6

Address Offset 0x0000 0318
Physical Address 0xE000 E418 Instance 0xE000 E418
Description Sets or reads interrupt priorities
Type RW
Bits Field Name Description Type Reset
31:24 PRI_N3 For register NVIC_IPR*6, the priority of interrupt number 4*6+3, or is RES0 if the PE does not implement this interrupt RW 0x00
23:16 PRI_N2 For register NVIC_IPR*6, the priority of interrupt number 4*6+2, or is RES0 if the PE does not implement this interrupt RW 0x00
15:8 PRI_N1 For register NVIC_IPR*6, the priority of interrupt number 4*6+1, or is RES0 if the PE does not implement this interrupt RW 0x00
7:0 PRI_N0 For register NVIC_IPR*6, the priority of interrupt number 4*6+0, or is RES0 if the PE does not implement this interrupt RW 0x00

TOP:CPU_NVIC:IPR7

Address Offset 0x0000 031C
Physical Address 0xE000 E41C Instance 0xE000 E41C
Description Sets or reads interrupt priorities
Type RW
Bits Field Name Description Type Reset
31:24 PRI_N3 For register NVIC_IPR*7, the priority of interrupt number 4*7+3, or is RES0 if the PE does not implement this interrupt RW 0x00
23:16 PRI_N2 For register NVIC_IPR*7, the priority of interrupt number 4*7+2, or is RES0 if the PE does not implement this interrupt RW 0x00
15:8 PRI_N1 For register NVIC_IPR*7, the priority of interrupt number 4*7+1, or is RES0 if the PE does not implement this interrupt RW 0x00
7:0 PRI_N0 For register NVIC_IPR*7, the priority of interrupt number 4*7+0, or is RES0 if the PE does not implement this interrupt RW 0x00

TOP:CPU_NVIC:IPR8

Address Offset 0x0000 0320
Physical Address 0xE000 E420 Instance 0xE000 E420
Description Sets or reads interrupt priorities
Type RW
Bits Field Name Description Type Reset
31:24 PRI_N3 For register NVIC_IPR*8, the priority of interrupt number 4*8+3, or is RES0 if the PE does not implement this interrupt RW 0x00
23:16 PRI_N2 For register NVIC_IPR*8, the priority of interrupt number 4*8+2, or is RES0 if the PE does not implement this interrupt RW 0x00
15:8 PRI_N1 For register NVIC_IPR*8, the priority of interrupt number 4*8+1, or is RES0 if the PE does not implement this interrupt RW 0x00
7:0 PRI_N0 For register NVIC_IPR*8, the priority of interrupt number 4*8+0, or is RES0 if the PE does not implement this interrupt RW 0x00

TOP:CPU_NVIC:IPR9

Address Offset 0x0000 0324
Physical Address 0xE000 E424 Instance 0xE000 E424
Description Sets or reads interrupt priorities
Type RW
Bits Field Name Description Type Reset
31:24 PRI_N3 For register NVIC_IPR*9, the priority of interrupt number 4*9+3, or is RES0 if the PE does not implement this interrupt RW 0x00
23:16 PRI_N2 For register NVIC_IPR*9, the priority of interrupt number 4*9+2, or is RES0 if the PE does not implement this interrupt RW 0x00
15:8 PRI_N1 For register NVIC_IPR*9, the priority of interrupt number 4*9+1, or is RES0 if the PE does not implement this interrupt RW 0x00
7:0 PRI_N0 For register NVIC_IPR*9, the priority of interrupt number 4*9+0, or is RES0 if the PE does not implement this interrupt RW 0x00

TOP:CPU_NVIC:IPR10

Address Offset 0x0000 0328
Physical Address 0xE000 E428 Instance 0xE000 E428
Description Sets or reads interrupt priorities
Type RW
Bits Field Name Description Type Reset
31:24 PRI_N3 For register NVIC_IPR*10, the priority of interrupt number 4*10+3, or is RES0 if the PE does not implement this interrupt RW 0x00
23:16 PRI_N2 For register NVIC_IPR*10, the priority of interrupt number 4*10+2, or is RES0 if the PE does not implement this interrupt RW 0x00
15:8 PRI_N1 For register NVIC_IPR*10, the priority of interrupt number 4*10+1, or is RES0 if the PE does not implement this interrupt RW 0x00
7:0 PRI_N0 For register NVIC_IPR*10, the priority of interrupt number 4*10+0, or is RES0 if the PE does not implement this interrupt RW 0x00

TOP:CPU_NVIC:IPR11

Address Offset 0x0000 032C
Physical Address 0xE000 E42C Instance 0xE000 E42C
Description Sets or reads interrupt priorities
Type RW
Bits Field Name Description Type Reset
31:24 PRI_N3 For register NVIC_IPR*11, the priority of interrupt number 4*11+3, or is RES0 if the PE does not implement this interrupt RW 0x00
23:16 PRI_N2 For register NVIC_IPR*11, the priority of interrupt number 4*11+2, or is RES0 if the PE does not implement this interrupt RW 0x00
15:8 PRI_N1 For register NVIC_IPR*11, the priority of interrupt number 4*11+1, or is RES0 if the PE does not implement this interrupt RW 0x00
7:0 PRI_N0 For register NVIC_IPR*11, the priority of interrupt number 4*11+0, or is RES0 if the PE does not implement this interrupt RW 0x00


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