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ti
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cc13x4_cc26x4
driverlib
cc13x4_cc26x4/driverlib/rf_mailbox.h
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/******************************************************************************
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* Filename: rf_mailbox.h
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*
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* Description: Definitions for interface between system and radio CPU
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*
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* Copyright (c) 2015 - 2020, Texas Instruments Incorporated
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
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* be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************/
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#ifndef _MAILBOX_H
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#define _MAILBOX_H
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#include <stdint.h>
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#include <string.h>
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#define RF_MODE_AUTO 0x00
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#define RF_MODE_BLE 0x00
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#define RF_MODE_IEEE_15_4 0x00
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#define RF_MODE_PROPRIETARY_2_4 0x00
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#define RF_MODE_PROPRIETARY RF_MODE_PROPRIETARY_2_4
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#define RF_MODE_MULTIPLE 0x00
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typedef
uint32_t
ratmr_t
;
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typedef
struct
{
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uint8_t *pCurrEntry;
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uint8_t *pLastEntry;
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}
dataQueue_t
;
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#define IRQN_COMMAND_DONE 0
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#define IRQN_LAST_COMMAND_DONE 1
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#define IRQN_FG_COMMAND_DONE 2
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#define IRQN_LAST_FG_COMMAND_DONE 3
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#define IRQN_TX_DONE 4
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#define IRQN_TX_ACK 5
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#define IRQN_TX_CTRL 6
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#define IRQN_TX_CTRL_ACK 7
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#define IRQN_TX_CTRL_ACK_ACK 8
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#define IRQN_TX_RETRANS 9
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#define IRQN_TX_ENTRY_DONE 10
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#define IRQN_TX_BUFFER_CHANGED 11
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#define IRQN_COMMAND_STARTED 12
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#define IRQN_FG_COMMAND_STARTED 13
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#define IRQN_PA_CHANGED 14
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#define IRQN_RX_OK 16
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#define IRQN_RX_NOK 17
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#define IRQN_RX_IGNORED 18
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#define IRQN_RX_EMPTY 19
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#define IRQN_RX_CTRL 20
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#define IRQN_RX_CTRL_ACK 21
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#define IRQN_RX_BUF_FULL 22
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#define IRQN_RX_ENTRY_DONE 23
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#define IRQN_RX_DATA_WRITTEN 24
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#define IRQN_RX_N_DATA_WRITTEN 25
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#define IRQN_RX_ABORTED 26
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#define IRQN_RX_COLLISION_DETECTED 27
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#define IRQN_SYNTH_NO_LOCK 28
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#define IRQN_MODULES_UNLOCKED 29
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#define IRQN_BOOT_DONE 30
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#define IRQN_INTERNAL_ERROR 31
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#define IRQ_COMMAND_DONE (1U << IRQN_COMMAND_DONE)
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#define IRQ_LAST_COMMAND_DONE (1U << IRQN_LAST_COMMAND_DONE)
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#define IRQ_FG_COMMAND_DONE (1U << IRQN_FG_COMMAND_DONE)
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#define IRQ_LAST_FG_COMMAND_DONE (1U << IRQN_LAST_FG_COMMAND_DONE)
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#define IRQ_TX_DONE (1U << IRQN_TX_DONE)
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#define IRQ_TX_ACK (1U << IRQN_TX_ACK)
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#define IRQ_TX_CTRL (1U << IRQN_TX_CTRL)
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#define IRQ_TX_CTRL_ACK (1U << IRQN_TX_CTRL_ACK)
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#define IRQ_TX_CTRL_ACK_ACK (1U << IRQN_TX_CTRL_ACK_ACK)
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#define IRQ_TX_RETRANS (1U << IRQN_TX_RETRANS)
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#define IRQ_TX_ENTRY_DONE (1U << IRQN_TX_ENTRY_DONE)
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#define IRQ_TX_BUFFER_CHANGED (1U << IRQN_TX_BUFFER_CHANGED)
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#define IRQ_COMMAND_STARTED (1U << IRQN_COMMAND_STARTED)
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#define IRQ_FG_COMMAND_STARTED (1U << IRQN_FG_COMMAND_STARTED)
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#define IRQ_PA_CHANGED (1U << IRQN_PA_CHANGED)
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#define IRQ_RX_OK (1U << IRQN_RX_OK)
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#define IRQ_RX_NOK (1U << IRQN_RX_NOK)
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#define IRQ_RX_IGNORED (1U << IRQN_RX_IGNORED)
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#define IRQ_RX_EMPTY (1U << IRQN_RX_EMPTY)
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#define IRQ_RX_CTRL (1U << IRQN_RX_CTRL)
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#define IRQ_RX_CTRL_ACK (1U << IRQN_RX_CTRL_ACK)
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#define IRQ_RX_BUF_FULL (1U << IRQN_RX_BUF_FULL)
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#define IRQ_RX_ENTRY_DONE (1U << IRQN_RX_ENTRY_DONE)
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#define IRQ_RX_DATA_WRITTEN (1U << IRQN_RX_DATA_WRITTEN)
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#define IRQ_RX_N_DATA_WRITTEN (1U << IRQN_RX_N_DATA_WRITTEN)
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#define IRQ_RX_ABORTED (1U << IRQN_RX_ABORTED)
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#define IRQ_RX_COLLISION_DETECTED (1U << IRQN_RX_COLLISION_DETECTED)
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#define IRQ_SYNTH_NO_LOCK (1U << IRQN_SYNTH_NO_LOCK)
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#define IRQ_MODULES_UNLOCKED (1U << IRQN_MODULES_UNLOCKED)
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#define IRQ_BOOT_DONE (1U << IRQN_BOOT_DONE)
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#define IRQ_INTERNAL_ERROR (1U << IRQN_INTERNAL_ERROR)
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#define CMDSTA_Pending 0x00
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#define CMDSTA_Done 0x01
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#define CMDSTA_IllegalPointer 0x81
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#define CMDSTA_UnknownCommand 0x82
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#define CMDSTA_UnknownDirCommand 0x83
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#define CMDSTA_ContextError 0x85
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#define CMDSTA_SchedulingError 0x86
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#define CMDSTA_ParError 0x87
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#define CMDSTA_QueueError 0x88
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#define CMDSTA_QueueBusy 0x89
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#define CMDR_DIR_CMD(cmdId) (((cmdId) << 16) | 1)
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#define CMDR_DIR_CMD_1BYTE(cmdId, par) (((cmdId) << 16) | ((par) << 8) | 1)
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#define CMDR_DIR_CMD_2BYTE(cmdId, par) (((cmdId) << 16) | ((par) & 0xFFFC) | 1)
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#define TRIG_NOW 0
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#define TRIG_NEVER 1
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#define TRIG_ABSTIME 2
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#define TRIG_REL_SUBMIT 3
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#define TRIG_REL_START 4
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#define TRIG_REL_PREVSTART 5
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#define TRIG_REL_FIRSTSTART 6
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#define TRIG_REL_PREVEND 7
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#define TRIG_REL_EVT1 8
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#define TRIG_REL_EVT2 9
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#define TRIG_EXTERNAL 10
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#define TRIG_PAST_BM 0x80
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#define COND_ALWAYS 0
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#define COND_NEVER 1
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#define COND_STOP_ON_FALSE 2
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#define COND_STOP_ON_TRUE 3
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#define COND_SKIP_ON_FALSE 4
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#define COND_SKIP_ON_TRUE 5
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#define IDLE 0x0000
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#define PENDING 0x0001
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#define ACTIVE 0x0002
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#define SKIPPED 0x0003
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#define DONE_OK 0x0400
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#define DONE_COUNTDOWN 0x0401
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#define DONE_RXERR 0x0402
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#define DONE_TIMEOUT 0x0403
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#define DONE_STOPPED 0x0404
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#define DONE_ABORT 0x0405
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#define DONE_FAILED 0x0406
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#define ERROR_PAST_START 0x0800
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#define ERROR_START_TRIG 0x0801
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#define ERROR_CONDITION 0x0802
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#define ERROR_PAR 0x0803
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#define ERROR_POINTER 0x0804
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#define ERROR_CMDID 0x0805
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#define ERROR_WRONG_BG 0x0806
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#define ERROR_NO_SETUP 0x0807
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#define ERROR_NO_FS 0x0808
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#define ERROR_SYNTH_PROG 0x0809
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#define ERROR_TXUNF 0x080A
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#define ERROR_RXOVF 0x080B
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#define ERROR_NO_RX 0x080C
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#define ERROR_PENDING 0x080D
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#define DATA_ENTRY_TYPE_GEN 0
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#define DATA_ENTRY_TYPE_MULTI 1
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#define DATA_ENTRY_TYPE_PTR 2
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#define DATA_ENTRY_TYPE_PARTIAL 3
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#define DATA_ENTRY_PENDING 0
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#define DATA_ENTRY_ACTIVE 1
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#define DATA_ENTRY_BUSY 2
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#define DATA_ENTRY_FINISHED 3
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#define DATA_ENTRY_UNFINISHED 4
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#define ADI_VAL_MASK(addr, mask, value) \
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(((addr) & 1) ? (((mask) & 0x0F) | (((value) & 0x0F) << 4)) : \
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((((mask) & 0x0F) << 4) | ((value) & 0x0F)))
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#define HW_REG_OVERRIDE(addr, val) ((((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(val) << 16))
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#define ADI_REG_OVERRIDE(adiNo, addr, val) (2 | ((uint32_t)(val) << 16) | \
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(((addr) & 0x3F) << 24) | (((adiNo) ? 1U : 0) << 31))
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#define ADI_2REG_OVERRIDE(adiNo, addr, val, addr2, val2) \
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(2 | ((uint32_t)(val2) << 2) | (((addr2) & 0x3F) << 10) | ((uint32_t)(val) << 16) | \
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(((addr) & 0x3F) << 24) | (((adiNo) ? 1U : 0) << 31))
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#define ADI_HALFREG_OVERRIDE(adiNo, addr, mask, val) (2 | (ADI_VAL_MASK(addr, mask, val) << 16) | \
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(((addr) & 0x3F) << 24) | (1U << 30) | (((adiNo) ? 1U : 0) << 31))
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#define ADI_2HALFREG_OVERRIDE(adiNo, addr, mask, val, addr2, mask2, val2) \
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(2 | (ADI_VAL_MASK(addr2, mask2, val2) << 2) | (((addr2) & 0x3F) << 10) | \
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(ADI_VAL_MASK(addr, mask, val) << 16) | (((addr) & 0x3F) << 24) | (1U << 30) | (((adiNo) ? 1U : 0) << 31))
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#define SW_REG_OVERRIDE(cmd, field, val) (3 | ((_POSITION_##cmd##_##field) << 4) | ((uint32_t)(val) << 16))
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#define SW_REG_IND_OVERRIDE(cmd, field, offset, val) (3 | \
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(((_POSITION_##cmd##_##field) + ((offset) << 1)) << 4) | ((uint32_t)(val) << 16))
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#define SW_REG_BYTE_OVERRIDE(cmd, field, val) (0x8003 | ((_POSITION_##cmd##_##field) << 4) | \
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(((uint32_t)(val) & 0xFF) << 16))
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#define SW_REG_2BYTE_OVERRIDE(cmd, field, val0, val1) (3 | (((_POSITION_##cmd##_##field) & 0xFFFE) << 4) | \
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(((uint32_t)(val0) << 16) & 0x00FF0000) | ((uint32_t)(val1) << 24))
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#define SW_REG_MASK_OVERRIDE(cmd, field, offset, mask, val) (0x8003 | \
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((_POSITION_##cmd##_##field + (offset)) << 4) | (((uint32_t)(val) & 0xFF) << 16) | (((uint32_t)(mask) & 0xFF) << 24))
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#define HW16_ARRAY_OVERRIDE(addr, length) (1 | (((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(length) << 16))
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#define HW32_ARRAY_OVERRIDE(addr, length) (1 | (((uintptr_t) (addr)) & 0xFFFC) | \
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((uint32_t)(length) << 16) | (1U << 30))
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#define HW16_MASK_ARRAY_OVERRIDE(addr, length) (0x20000001 | (((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(length) << 16))
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#define HW32_MASK_ARRAY_OVERRIDE(addr, length) (0x60000001 | (((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(length) << 16))
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#define HW16_MASK_VAL(mask, val) ((mask) << 16 | (val))
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#define ADI_ARRAY_OVERRIDE(adiNo, addr, bHalfSize, length) (1 | ((((addr) & 0x3F) << 2)) | \
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((!!(bHalfSize)) << 8) | ((!!(adiNo)) << 9) | ((uint32_t)(length) << 16) | (2U << 30))
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#define SW_ARRAY_OVERRIDE(cmd, firstfield, length) (1 | (((_POSITION_##cmd##_##firstfield)) << 2) | \
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((uint32_t)(length) << 16) | (3U << 30))
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#define MCE_RFE_OVERRIDE(mceCfg, mceRomBank, mceMode, rfeCfg, rfeRomBank, rfeMode) \
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(7 | ((mceCfg & 2) << 3) | ((rfeCfg & 2) << 4) |\
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((mceCfg & 1) << 6) | (((mceRomBank) & 0x0F) << 7) | \
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((rfeCfg & 1) << 11) | (((rfeRomBank) & 0x0F) << 12) | \
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(((mceMode) & 0x00FF) << 16) | (((rfeMode) & 0x00FF) << 24))
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#define HPOSC_OVERRIDE(freqOffset) (0x000B | ((freqOffset) << 16))
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#define TX20_POWER_OVERRIDE(tx20Power) (0x002B | (((uint32_t) tx20Power) << 10))
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#define TX_STD_POWER_OVERRIDE(txPower) (0x022B | (((uint32_t) txPower) << 10))
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#define MCE_RFE_SPLIT_OVERRIDE(mceRxCfg, mceTxCfg, rfeRxCfg, rfeTxCfg) \
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(0x003B | ((mceRxCfg) << 12) | ((mceTxCfg) << 17) | ((rfeRxCfg) << 22) | ((rfeTxCfg) << 27))
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#define CENTER_FREQ_OVERRIDE(centerFreq, flags) (0x004B | ((flags & 0x03) << 18) | \
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((centerFreq) << 20))
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#define MOD_TYPE_OVERRIDE(modType, deviation, stepSz, flags) (0x005B | ((flags & 0x01) << 15) | \
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((modType) << 16) | ((deviation) << 19) |((stepSz) << 30) )
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#define NEW_OVERRIDE_SEGMENT(address) (((((uintptr_t)(address)) & 0x03FFFFFC) << 6) | 0x000F | \
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(((((uintptr_t)(address) >> 24) == 0x20) ? 0x01 : \
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(((uintptr_t)(address) >> 24) == 0x21) ? 0x02 : \
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(((uintptr_t)(address) >> 24) == 0xA0) ? 0x03 : \
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(((uintptr_t)(address) >> 24) == 0x00) ? 0x04 : \
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(((uintptr_t)(address) >> 24) == 0x10) ? 0x05 : \
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(((uintptr_t)(address) >> 24) == 0x11) ? 0x06 : \
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(((uintptr_t)(address) >> 24) == 0x40) ? 0x07 : \
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(((uintptr_t)(address) >> 24) == 0x50) ? 0x08 : \
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0x09) << 4)) // Use illegal value for illegal address range
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#define END_OVERRIDE 0xFFFFFFFF
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#define ADI_ADDR_VAL(addr, value) ((((addr) & 0x7F) << 8) | ((value) & 0xFF))
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#define ADI_ADDR_VAL_MASK(addr, mask, value) ((((addr) & 0x7F) << 8) | ADI_VAL_MASK(addr, mask, value))
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#define LOWORD(value) ((value) & 0xFFFF)
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#define HIWORD(value) ((value) >> 16)
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#endif
ratmr_t
uint32_t ratmr_t
Type definition for RAT.
Definition:
cc13x4_cc26x4/driverlib/rf_mailbox.h:57
dataQueue_t
Type definition for a data queue.
Definition:
cc13x2_cc26x2/driverlib/rf_mailbox.h:62
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, Texas Instruments Incorporated. All rights reserved.
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