47 #define RF_MODE_AUTO 0x00 48 #define RF_MODE_BLE 0x00 49 #define RF_MODE_IEEE_15_4 0x00 50 #define RF_MODE_PROPRIETARY_2_4 0x00 51 #define RF_MODE_PROPRIETARY RF_MODE_PROPRIETARY_2_4 52 #define RF_MODE_MULTIPLE 0x00 72 #define IRQN_COMMAND_DONE 0 73 #define IRQN_LAST_COMMAND_DONE 1 74 #define IRQN_FG_COMMAND_DONE 2 75 #define IRQN_LAST_FG_COMMAND_DONE 3 76 #define IRQN_TX_DONE 4 78 #define IRQN_TX_CTRL 6 79 #define IRQN_TX_CTRL_ACK 7 80 #define IRQN_TX_CTRL_ACK_ACK 8 81 #define IRQN_TX_RETRANS 9 82 #define IRQN_TX_ENTRY_DONE 10 83 #define IRQN_TX_BUFFER_CHANGED 11 84 #define IRQN_COMMAND_STARTED 12 85 #define IRQN_FG_COMMAND_STARTED 13 86 #define IRQN_PA_CHANGED 14 88 #define IRQN_RX_NOK 17 89 #define IRQN_RX_IGNORED 18 90 #define IRQN_RX_EMPTY 19 91 #define IRQN_RX_CTRL 20 92 #define IRQN_RX_CTRL_ACK 21 93 #define IRQN_RX_BUF_FULL 22 94 #define IRQN_RX_ENTRY_DONE 23 95 #define IRQN_RX_DATA_WRITTEN 24 96 #define IRQN_RX_N_DATA_WRITTEN 25 97 #define IRQN_RX_ABORTED 26 98 #define IRQN_RX_COLLISION_DETECTED 27 99 #define IRQN_SYNTH_NO_LOCK 28 100 #define IRQN_MODULES_UNLOCKED 29 101 #define IRQN_BOOT_DONE 30 103 #define IRQN_INTERNAL_ERROR 31 105 #define IRQ_COMMAND_DONE (1U << IRQN_COMMAND_DONE) 106 #define IRQ_LAST_COMMAND_DONE (1U << IRQN_LAST_COMMAND_DONE) 107 #define IRQ_FG_COMMAND_DONE (1U << IRQN_FG_COMMAND_DONE) 108 #define IRQ_LAST_FG_COMMAND_DONE (1U << IRQN_LAST_FG_COMMAND_DONE) 110 #define IRQ_TX_DONE (1U << IRQN_TX_DONE) 111 #define IRQ_TX_ACK (1U << IRQN_TX_ACK) 112 #define IRQ_TX_CTRL (1U << IRQN_TX_CTRL) 113 #define IRQ_TX_CTRL_ACK (1U << IRQN_TX_CTRL_ACK) 114 #define IRQ_TX_CTRL_ACK_ACK (1U << IRQN_TX_CTRL_ACK_ACK) 115 #define IRQ_TX_RETRANS (1U << IRQN_TX_RETRANS) 117 #define IRQ_TX_ENTRY_DONE (1U << IRQN_TX_ENTRY_DONE) 118 #define IRQ_TX_BUFFER_CHANGED (1U << IRQN_TX_BUFFER_CHANGED) 120 #define IRQ_COMMAND_STARTED (1U << IRQN_COMMAND_STARTED) 121 #define IRQ_FG_COMMAND_STARTED (1U << IRQN_FG_COMMAND_STARTED) 122 #define IRQ_PA_CHANGED (1U << IRQN_PA_CHANGED) 124 #define IRQ_RX_OK (1U << IRQN_RX_OK) 125 #define IRQ_RX_NOK (1U << IRQN_RX_NOK) 126 #define IRQ_RX_IGNORED (1U << IRQN_RX_IGNORED) 127 #define IRQ_RX_EMPTY (1U << IRQN_RX_EMPTY) 128 #define IRQ_RX_CTRL (1U << IRQN_RX_CTRL) 129 #define IRQ_RX_CTRL_ACK (1U << IRQN_RX_CTRL_ACK) 130 #define IRQ_RX_BUF_FULL (1U << IRQN_RX_BUF_FULL) 131 #define IRQ_RX_ENTRY_DONE (1U << IRQN_RX_ENTRY_DONE) 132 #define IRQ_RX_DATA_WRITTEN (1U << IRQN_RX_DATA_WRITTEN) 133 #define IRQ_RX_N_DATA_WRITTEN (1U << IRQN_RX_N_DATA_WRITTEN) 134 #define IRQ_RX_ABORTED (1U << IRQN_RX_ABORTED) 135 #define IRQ_RX_COLLISION_DETECTED (1U << IRQN_RX_COLLISION_DETECTED) 136 #define IRQ_SYNTH_NO_LOCK (1U << IRQN_SYNTH_NO_LOCK) 137 #define IRQ_MODULES_UNLOCKED (1U << IRQN_MODULES_UNLOCKED) 138 #define IRQ_BOOT_DONE (1U << IRQN_BOOT_DONE) 139 #define IRQ_INTERNAL_ERROR (1U << IRQN_INTERNAL_ERROR) 147 #define CMDSTA_Pending 0x00 148 #define CMDSTA_Done 0x01 150 #define CMDSTA_IllegalPointer 0x81 151 #define CMDSTA_UnknownCommand 0x82 152 #define CMDSTA_UnknownDirCommand 0x83 153 #define CMDSTA_ContextError 0x85 155 #define CMDSTA_SchedulingError 0x86 157 #define CMDSTA_ParError 0x87 159 #define CMDSTA_QueueError 0x88 161 #define CMDSTA_QueueBusy 0x89 171 #define CMDR_DIR_CMD(cmdId) (((cmdId) << 16) | 1) 174 #define CMDR_DIR_CMD_1BYTE(cmdId, par) (((cmdId) << 16) | ((par) << 8) | 1) 177 #define CMDR_DIR_CMD_2BYTE(cmdId, par) (((cmdId) << 16) | ((par) & 0xFFFC) | 1) 187 #define TRIG_ABSTIME 2 188 #define TRIG_REL_SUBMIT 3 189 #define TRIG_REL_START 4 190 #define TRIG_REL_PREVSTART 5 191 #define TRIG_REL_FIRSTSTART 6 192 #define TRIG_REL_PREVEND 7 193 #define TRIG_REL_EVT1 8 194 #define TRIG_REL_EVT2 9 195 #define TRIG_EXTERNAL 10 196 #define TRIG_PAST_BM 0x80 203 #define COND_ALWAYS 0 205 #define COND_STOP_ON_FALSE 2 206 #define COND_STOP_ON_TRUE 3 208 #define COND_SKIP_ON_FALSE 4 210 #define COND_SKIP_ON_TRUE 5 222 #define PENDING 0x0001 223 #define ACTIVE 0x0002 224 #define SKIPPED 0x0003 225 #define DONE_OK 0x0400 229 #define DONE_COUNTDOWN 0x0401 230 #define DONE_RXERR 0x0402 231 #define DONE_TIMEOUT 0x0403 232 #define DONE_STOPPED 0x0404 233 #define DONE_ABORT 0x0405 234 #define DONE_FAILED 0x0406 235 #define ERROR_PAST_START 0x0800 239 #define ERROR_START_TRIG 0x0801 240 #define ERROR_CONDITION 0x0802 241 #define ERROR_PAR 0x0803 242 #define ERROR_POINTER 0x0804 243 #define ERROR_CMDID 0x0805 244 #define ERROR_WRONG_BG 0x0806 246 #define ERROR_NO_SETUP 0x0807 247 #define ERROR_NO_FS 0x0808 248 #define ERROR_SYNTH_PROG 0x0809 249 #define ERROR_TXUNF 0x080A 250 #define ERROR_RXOVF 0x080B 251 #define ERROR_NO_RX 0x080C 252 #define ERROR_PENDING 0x080D 259 #define DATA_ENTRY_TYPE_GEN 0 260 #define DATA_ENTRY_TYPE_MULTI 1 261 #define DATA_ENTRY_TYPE_PTR 2 262 #define DATA_ENTRY_TYPE_PARTIAL 3 268 #define DATA_ENTRY_PENDING 0 269 #define DATA_ENTRY_ACTIVE 1 270 #define DATA_ENTRY_BUSY 2 271 #define DATA_ENTRY_FINISHED 3 272 #define DATA_ENTRY_UNFINISHED 4 279 #define ADI_VAL_MASK(addr, mask, value) \ 280 (((addr) & 1) ? (((mask) & 0x0F) | (((value) & 0x0F) << 4)) : \ 281 ((((mask) & 0x0F) << 4) | ((value) & 0x0F))) 282 #define HW_REG_OVERRIDE(addr, val) ((((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(val) << 16)) 284 #define ADI_REG_OVERRIDE(adiNo, addr, val) (2 | ((uint32_t)(val) << 16) | \ 286 (((addr) & 0x3F) << 24) | (((adiNo) ? 1U : 0) << 31)) 287 #define ADI_2REG_OVERRIDE(adiNo, addr, val, addr2, val2) \ 289 (2 | ((uint32_t)(val2) << 2) | (((addr2) & 0x3F) << 10) | ((uint32_t)(val) << 16) | \ 290 (((addr) & 0x3F) << 24) | (((adiNo) ? 1U : 0) << 31)) 291 #define ADI_HALFREG_OVERRIDE(adiNo, addr, mask, val) (2 | (ADI_VAL_MASK(addr, mask, val) << 16) | \ 293 (((addr) & 0x3F) << 24) | (1U << 30) | (((adiNo) ? 1U : 0) << 31)) 294 #define ADI_2HALFREG_OVERRIDE(adiNo, addr, mask, val, addr2, mask2, val2) \ 296 (2 | (ADI_VAL_MASK(addr2, mask2, val2) << 2) | (((addr2) & 0x3F) << 10) | \ 297 (ADI_VAL_MASK(addr, mask, val) << 16) | (((addr) & 0x3F) << 24) | (1U << 30) | (((adiNo) ? 1U : 0) << 31)) 300 #define SW_REG_OVERRIDE(cmd, field, val) (3 | ((_POSITION_##cmd##_##field) << 4) | ((uint32_t)(val) << 16)) 301 #define SW_REG_IND_OVERRIDE(cmd, field, offset, val) (3 | \ 303 (((_POSITION_##cmd##_##field) + ((offset) << 1)) << 4) | ((uint32_t)(val) << 16)) 304 #define SW_REG_BYTE_OVERRIDE(cmd, field, val) (0x8003 | ((_POSITION_##cmd##_##field) << 4) | \ 306 (((uint32_t)(val) & 0xFF) << 16)) 307 #define SW_REG_2BYTE_OVERRIDE(cmd, field, val0, val1) (3 | (((_POSITION_##cmd##_##field) & 0xFFFE) << 4) | \ 309 (((uint32_t)(val0) << 16) & 0x00FF0000) | ((uint32_t)(val1) << 24)) 310 #define SW_REG_MASK_OVERRIDE(cmd, field, offset, mask, val) (0x8003 | \ 311 ((_POSITION_##cmd##_##field + (offset)) << 4) | (((uint32_t)(val) & 0xFF) << 16) | (((uint32_t)(mask) & 0xFF) << 24)) 313 #define HW16_ARRAY_OVERRIDE(addr, length) (1 | (((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(length) << 16)) 314 #define HW32_ARRAY_OVERRIDE(addr, length) (1 | (((uintptr_t) (addr)) & 0xFFFC) | \ 315 ((uint32_t)(length) << 16) | (1U << 30)) 316 #define HW16_MASK_ARRAY_OVERRIDE(addr, length) (0x20000001 | (((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(length) << 16)) 317 #define HW32_MASK_ARRAY_OVERRIDE(addr, length) (0x60000001 | (((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(length) << 16)) 318 #define HW16_MASK_VAL(mask, val) ((mask) << 16 | (val)) 319 #define ADI_ARRAY_OVERRIDE(adiNo, addr, bHalfSize, length) (1 | ((((addr) & 0x3F) << 2)) | \ 320 ((!!(bHalfSize)) << 8) | ((!!(adiNo)) << 9) | ((uint32_t)(length) << 16) | (2U << 30)) 321 #define SW_ARRAY_OVERRIDE(cmd, firstfield, length) (1 | (((_POSITION_##cmd##_##firstfield)) << 2) | \ 322 ((uint32_t)(length) << 16) | (3U << 30)) 323 #define MCE_RFE_OVERRIDE(mceCfg, mceRomBank, mceMode, rfeCfg, rfeRomBank, rfeMode) \ 324 (7 | ((mceCfg & 2) << 3) | ((rfeCfg & 2) << 4) |\ 325 ((mceCfg & 1) << 6) | (((mceRomBank) & 0x0F) << 7) | \ 326 ((rfeCfg & 1) << 11) | (((rfeRomBank) & 0x0F) << 12) | \ 327 (((mceMode) & 0x00FF) << 16) | (((rfeMode) & 0x00FF) << 24)) 328 #define HPOSC_OVERRIDE(freqOffset) (0x000B | ((freqOffset) << 16)) 329 #define TX20_POWER_OVERRIDE(tx20Power) (0x002B | (((uint32_t) tx20Power) << 10)) 330 #define TX_STD_POWER_OVERRIDE(txPower) (0x022B | (((uint32_t) txPower) << 10)) 331 #define MCE_RFE_SPLIT_OVERRIDE(mceRxCfg, mceTxCfg, rfeRxCfg, rfeTxCfg) \ 332 (0x003B | ((mceRxCfg) << 12) | ((mceTxCfg) << 17) | ((rfeRxCfg) << 22) | ((rfeTxCfg) << 27)) 333 #define CENTER_FREQ_OVERRIDE(centerFreq, flags) (0x004B | ((flags & 0x03) << 18) | \ 334 ((centerFreq) << 20)) 335 #define MOD_TYPE_OVERRIDE(modType, deviation, stepSz, flags) (0x005B | ((flags & 0x01) << 15) | \ 336 ((modType) << 16) | ((deviation) << 19) |((stepSz) << 30) ) 337 #define NEW_OVERRIDE_SEGMENT(address) (((((uintptr_t)(address)) & 0x03FFFFFC) << 6) | 0x000F | \ 338 (((((uintptr_t)(address) >> 24) == 0x20) ? 0x01 : \ 339 (((uintptr_t)(address) >> 24) == 0x21) ? 0x02 : \ 340 (((uintptr_t)(address) >> 24) == 0xA0) ? 0x03 : \ 341 (((uintptr_t)(address) >> 24) == 0x00) ? 0x04 : \ 342 (((uintptr_t)(address) >> 24) == 0x10) ? 0x05 : \ 343 (((uintptr_t)(address) >> 24) == 0x11) ? 0x06 : \ 344 (((uintptr_t)(address) >> 24) == 0x40) ? 0x07 : \ 345 (((uintptr_t)(address) >> 24) == 0x50) ? 0x08 : \ 346 0x09) << 4)) // Use illegal value for illegal address range 347 #define END_OVERRIDE 0xFFFFFFFF 352 #define ADI_ADDR_VAL(addr, value) ((((addr) & 0x7F) << 8) | ((value) & 0xFF)) 353 #define ADI_ADDR_VAL_MASK(addr, mask, value) ((((addr) & 0x7F) << 8) | ADI_VAL_MASK(addr, mask, value)) 356 #define LOWORD(value) ((value) & 0xFFFF) 357 #define HIWORD(value) ((value) >> 16) uint8_t * pCurrEntry
Pointer to the data queue entry to be used, NULL for an empty queue.
Definition: cc13x2_cc26x2/driverlib/rf_mailbox.h:63
uint8_t * pLastEntry
Pointer to the last entry in the queue, NULL for a circular queue.
Definition: cc13x2_cc26x2/driverlib/rf_mailbox.h:64
uint32_t ratmr_t
Type definition for RAT.
Definition: cc13x2_cc26x2/driverlib/rf_mailbox.h:57
Type definition for a data queue.
Definition: cc13x2_cc26x2/driverlib/rf_mailbox.h:62