Instance: NVMNW
Component: NVMNW
Base address: 0x58032000
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RO |
32 |
0x0000 0000 |
0x0000 0020 |
0x5803 2020 |
|
RW |
32 |
0x0000 0000 |
0x0000 0028 |
0x5803 2028 |
|
RO |
32 |
0x0000 0000 |
0x0000 0030 |
0x5803 2030 |
|
RO |
32 |
0x0000 0000 |
0x0000 0038 |
0x5803 2038 |
|
WO |
32 |
0x0000 0000 |
0x0000 0040 |
0x5803 2040 |
|
WO |
32 |
0x0000 0000 |
0x0000 0048 |
0x5803 2048 |
|
RO |
32 |
0x0000 0001 |
0x0000 00E0 |
0x5803 20E0 |
|
RO |
32 |
0x0B40 0010 |
0x0000 00FC |
0x5803 20FC |
|
RW |
32 |
0x0000 0000 |
0x0000 0100 |
0x5803 2100 |
|
RW |
32 |
0bXXXX XXXX XXXX XXXX XXXX XXXX X000 0000 |
0x0000 0104 |
0x5803 2104 |
|
RW |
32 |
0b0000 0000 0000 0000 1100 000X XXX0 0000 |
0x0000 0108 |
0x5803 2108 |
|
RW |
32 |
0x0000 0000 |
0x0000 0120 |
0x5803 2120 |
|
RW |
32 |
0x0000 FFFF |
0x0000 0124 |
0x5803 2124 |
|
RW |
32 |
0x0000 0000 |
0x0000 012C |
0x5803 212C |
|
RW |
32 |
0xFFFF FFFF |
0x0000 0130 |
0x5803 2130 |
|
RW |
32 |
0xFFFF FFFF |
0x0000 0134 |
0x5803 2134 |
|
RW |
32 |
0xFFFF FFFF |
0x0000 0138 |
0x5803 2138 |
|
RW |
32 |
0xFFFF FFFF |
0x0000 013C |
0x5803 213C |
|
RW |
32 |
0xFFFF FFFF |
0x0000 0140 |
0x5803 2140 |
|
RW |
32 |
0xFFFF FFFF |
0x0000 0144 |
0x5803 2144 |
|
RW |
32 |
0xFFFF FFFF |
0x0000 0148 |
0x5803 2148 |
|
RW |
32 |
0xFFFF FFFF |
0x0000 014C |
0x5803 214C |
|
RW |
32 |
0xFFFF FFFF |
0x0000 0150 |
0x5803 2150 |
|
RW |
32 |
0xFFFF FFFF |
0x0000 0154 |
0x5803 2154 |
|
RW |
32 |
0xFFFF FFFF |
0x0000 0158 |
0x5803 2158 |
|
RW |
32 |
0xFFFF FFFF |
0x0000 015C |
0x5803 215C |
|
RW |
32 |
0xFFFF FFFF |
0x0000 0160 |
0x5803 2160 |
|
RW |
32 |
0xFFFF FFFF |
0x0000 0164 |
0x5803 2164 |
|
RW |
32 |
0xFFFF FFFF |
0x0000 0168 |
0x5803 2168 |
|
RW |
32 |
0xFFFF FFFF |
0x0000 016C |
0x5803 216C |
|
RW |
32 |
0xFFFF FFFF |
0x0000 01D0 |
0x5803 21D0 |
|
RW |
32 |
0xFFFF FFFF |
0x0000 01D4 |
0x5803 21D4 |
|
RW |
32 |
0x0000 0001 |
0x0000 0210 |
0x5803 2210 |
|
RW |
32 |
0x0000 0001 |
0x0000 0214 |
0x5803 2214 |
|
RW |
32 |
0x0000 0001 |
0x0000 0218 |
0x5803 2218 |
|
RW |
32 |
0x0000 0002 |
0x0000 03B0 |
0x5803 23B0 |
|
RW |
32 |
0x0000 0000 |
0x0000 03B4 |
0x5803 23B4 |
|
RO |
32 |
0b0000 0000 0000 0000 0000 XXX0 0000 0000 |
0x0000 03D0 |
0x5803 23D0 |
|
RO |
32 |
0x0020 0000 |
0x0000 03D4 |
0x5803 23D4 |
|
RO |
32 |
0x0000 0000 |
0x0000 03D8 |
0x5803 23D8 |
|
RO |
32 |
0bXXXX XXXX XXXX XX00 XXXX 0000 0000 0000 |
0x0000 03DC |
0x5803 23DC |
|
RO |
32 |
0bXXXX XXXX XXXX X010 0000 1000 0000 0000 |
0x0000 03F0 |
0x5803 23F0 |
|
RO |
32 |
0b0000 0000 0000 0100 XXX0 0000 1000 0000 |
0x0000 03F4 |
0x5803 23F4 |
|
RO |
32 |
0x0000 0004 |
0x0000 03F8 |
0x5803 23F8 |
|
RO |
32 |
0x0000 0100 |
0x0000 0400 |
0x5803 2400 |
|
RO |
32 |
0x0001 0101 |
0x0000 0404 |
0x5803 2404 |
|
RO |
32 |
0x0000 0100 |
0x0000 0410 |
0x5803 2410 |
|
RO |
32 |
0x0001 0101 |
0x0000 0414 |
0x5803 2414 |
|
RW |
32 |
0x0000 0000 |
0x0000 0500 |
0x5803 2500 |
|
RW |
32 |
0b0000 0000 0000 X000 0000 0000 0000 0000 |
0x0000 0504 |
0x5803 2504 |
|
RW |
32 |
0x0000 0000 |
0x0000 0508 |
0x5803 2508 |
|
RW |
32 |
0x0000 0002 |
0x0000 050C |
0x5803 250C |
|
RW |
32 |
0x0000 0000 |
0x0000 0510 |
0x5803 2510 |
|
RO |
32 |
0xXXXX 0000 |
0x0000 0514 |
0x5803 2514 |
|
RW |
32 |
0x0000 000F |
0x0000 0540 |
0x5803 2540 |
|
RW |
32 |
0x0000 000F |
0x0000 0544 |
0x5803 2544 |
|
RW |
32 |
0x0000 000F |
0x0000 0548 |
0x5803 2548 |
|
RW |
32 |
0x0000 000F |
0x0000 054C |
0x5803 254C |
|
RW |
32 |
0x0000 1000 |
0x0000 0560 |
0x5803 2560 |
|
RW |
32 |
0bXXXX XXXX XXXX XXXX XXXX XXX1 0000 0000 |
0x0000 0564 |
0x5803 2564 |
Address Offset | 0x0000 0020 | ||
Physical Address | 0x5803 2020 | Instance | 0x5803 2020 |
Description | Interrupt Index Register: The IIDX register provides the highest priority enabled interrupt index. PSD compliant register. Note that it is not recommended to use this register if the system clock is running at a slower clock frequency than the NoWrapper clock. If this is the case, then reading this register may fail to update the RIS register correctly. The MIS register should be read directly, and a write to ICLR should be used to clear interrupts when this clock relationship is present. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
0 | STAT | Indicates which interrupt has fired. 0x0 means no event pending. The priority order is fixed. On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flags in the RIS and MIS are cleared as well. After a read from the CPU (not from the debug interface), the register must be updated with the next highest priority interrupt.
|
RO | 0 |
Address Offset | 0x0000 0028 | ||
Physical Address | 0x5803 2028 | Instance | 0x5803 2028 |
Description | Interrupt Mask Register: The IMASK register holds the current interrupt mask settings. Masked interrupts are read in the MIS register. PSD compliant register. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
0 | DONE | Interrupt mask for DONE: 0: Interrupt is disabled in MIS register 1: Interrupt is enabled in MIS register
|
RW | 0 |
Address Offset | 0x0000 0030 | ||
Physical Address | 0x5803 2030 | Instance | 0x5803 2030 |
Description | Raw Interrupt Status Register: The RIS register reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing a 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled. A flag can be set by software by writing a 1 to the ISET register. Reading the IIDX register will also clear the corresponding bit in RIS. PSD compliant register. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
0 | DONE | NoWrapper operation completed. This interrupt bit is set by firmware or the corresponding bit in the ISET register. It is cleared by the corresponding bit in in the ICLR register or reading the IIDX register when this interrupt is the highest priority.
|
RO | 0 |
Address Offset | 0x0000 0038 | ||
Physical Address | 0x5803 2038 | Instance | 0x5803 2038 |
Description | Masked Interrupt Status Register: The MIS register is a bit-wise AND of the contents of the IMASK and RIS registers. This is kept mainly for ARM compatibility, and has limited use since the highest priority interrupt index is returned via the IIDX register. PSD compliant register. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
0 | DONE | NoWrapper operation completed. This masked interrupt bit reflects the bitwise AND of the corresponding RIS and IMASK bits.
|
RO | 0 |
Address Offset | 0x0000 0040 | ||
Physical Address | 0x5803 2040 | Instance | 0x5803 2040 |
Description | Interrupt Set Register: The ISET register allows software to write a 1 to set corresponding interrupt. Safety: This meets a safety requirement to allow software diagnostics to trigger interrupts. PSD compliant register. |
||
Type | WO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
0 | DONE | 0: No effect 1: Set the DONE interrupt in the RIS register
|
WO | 0 |
Address Offset | 0x0000 0048 | ||
Physical Address | 0x5803 2048 | Instance | 0x5803 2048 |
Description | Interrupt Clear Register. The ICLR register allows allows software to write a 1 to clear corresponding interrupt. PSD compliant register. |
||
Type | WO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
0 | DONE | 0: No effect 1: Clear the DONE interrupt in the RIS register
|
WO | 0 |
Address Offset | 0x0000 00E0 | ||
Physical Address | 0x5803 20E0 | Instance | 0x5803 20E0 |
Description | Event mode register. It is used to select whether each line is disabled, in software mode (software clears the RIS) or in hardware mode (hardware clears the RIS). |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||||||||
31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||||||||||||||
1:0 | INT0_CFG | Event line mode select for peripheral event
|
RO | 0b01 |
Address Offset | 0x0000 00FC | ||
Physical Address | 0x5803 20FC | Instance | 0x5803 20FC |
Description | Hardware Version Description Register: This register identifies the NoWrapper hardware version and feature set used. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:16 | MODULEID | Module ID
|
RO | 0x0B40 | |||||||||||
15:12 | FEATUREVER | Feature set
|
RO | 0x0 | |||||||||||
11:8 | INSTNUM | Instance number
|
RO | 0x0 | |||||||||||
7:4 | MAJREV | Major Revision
|
RO | 0x1 | |||||||||||
3:0 | MINREV | Minor Revision
|
RO | 0x0 |
Address Offset | 0x0000 0100 | ||
Physical Address | 0x5803 2100 | Instance | 0x5803 2100 |
Description | Command Execute Register: Initiates execution of the command specified in the CMDTYPE register. This register is blocked for writes after being written to 1 and prior to STATCMD.DONE being set by the NoWrapper hardware. NoWrapper hardware clears this register after the processing of the command has completed. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
0 | VAL | Command Execute value Initiates execution of the command specified in the CMDTYPE register.
|
RW | 0 |
Address Offset | 0x0000 0104 | ||
Physical Address | 0x5803 2104 | Instance | 0x5803 2104 |
Description | Command Type Register This register specifies the type of command to be executed by the NoWrapper hardware. This register is blocked for writes after CMDEXEC is written to a 1 and prior to STATCMD.DONE being set by the hardware to indicate that command execution has completed. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||||||||
6:4 | SIZE | Command size
|
RW | 0b000 | ||||||||||||||||||||||||||
3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||||||||||||||||||||||||||
2:0 | COMMAND | Command type
|
RW | 0b000 |
Address Offset | 0x0000 0108 | ||
Physical Address | 0x5803 2108 | Instance | 0x5803 2108 |
Description | Command Control Register This register configures specific capabilities of the state machine for related to the execution of a command. This register is blocked for writes after CMDEXEC is written to a 1 and prior to STATCMD.DONE being set by the hardware to indicate that command execution has completed. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||||||||||||||||||||
31:22 | RESERVED22 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 | ||||||||||||||||||||||||||||||||||||||
21 | DATAVEREN | Enable invalid data verify. This checks for 0->1 transitions in the memory when a program operation is initiated. If such a transition is found, the program will fail with an error without doing any programming.
|
RW | 0 | ||||||||||||||||||||||||||||||||||||||
20 | SSERASEDIS | Disable Stair-Step Erase. If set, the default VHV trim voltage setting will be used for all erase pulses. By default, this bit is reset, meaning that the VHV voltage will be stepped during successive erase pulses. The step count, step voltage, begin and end voltages are all hard-wired.
|
RW | 0 | ||||||||||||||||||||||||||||||||||||||
19 | ERASEMASKDIS | Disable use of erase mask for erase Bit masking will not be used during erase verify. If any sectors fail the verify either before (prever) or after (postver) the operation, then all specified flash sectors will receive subsequent erase pulse.
|
RW | 0 | ||||||||||||||||||||||||||||||||||||||
18 | PROGMASKDIS | Disable use of program mask for programming. Bit masking will not be used during program verify. If any bits fail the verify either before (prever) or after (postver) the operation, then all specified flash entries will receive subsequent program pulse.
|
RW | 0 | ||||||||||||||||||||||||||||||||||||||
17 | RESERVED17 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||||||||||||||||||||||||||||||||||||||
16 | ADDRXLATEOVR | Override hardware address translation of address in CMDADDR from a system address to a bank address and bank ID. Use data written to CMDADDR directly as the bank address. Use the value written to CMDCTL.BANKSEL directly as the bank ID. Use the value written to CMDCTL.REGIONSEL directly as the region ID.
|
RW | 0 | ||||||||||||||||||||||||||||||||||||||
15 | POSTVEREN | Enable verify after program or erase
|
RW | 1 | ||||||||||||||||||||||||||||||||||||||
14 | PREVEREN | Enable verify before program or erase. For program, bits already programmed to the requested value will be masked. For erase, sectors already erased will be masked.
|
RW | 1 | ||||||||||||||||||||||||||||||||||||||
13 | RESERVED13 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||||||||||||||||||||||||||||||||||||||
12:9 | REGIONSEL | Bank Region A specific region ID can be written to this field to indicate to which region an operation should be applied if CMDCTL.ADDRXLATEOVR is set.
|
RW | 0x0 | ||||||||||||||||||||||||||||||||||||||
4 | BANKSEL | Bank Select A specific Bank ID can be written to this field to indicate to which bank an operation should be applied if CMDCTL.ADDRXLATEOVR is set.
|
RW | 0 | ||||||||||||||||||||||||||||||||||||||
3:0 | MODESEL | Mode This field is only used for the Mode Change command type. Otherwise, bank and pump modes are set automaticlly via the NW hardware.
|
RW | 0x0 |
Address Offset | 0x0000 0120 | ||
Physical Address | 0x5803 2120 | Instance | 0x5803 2120 |
Description | Command Address Register: This register forms the target address of a command. The use cases are as follows: 1)For single-word program, this address indicates the flash bank word to be programmed. 2)For multi-word program, this address indicates the first flash bank address for the program. The address will be incremented for further words. 3)For sector erase, this address indicates the sector to be erased. 4)For bank erase, the address indicates the bank to be erased. 5)For read verify, the address indications follow program/erase listed above. Note the address written to this register will be submitted for translation to the NoWrapper address translation interface, and the translated address will be used to access the bank. However, if the CMDCTL.ADDRXLATEOVR bit is set, then the address written to this register will be used directly as the bank address. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by the NoWrapper hardware. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:0 | VAL | Address value
|
RW | 0x0000 0000 |
Address Offset | 0x0000 0124 | ||
Physical Address | 0x5803 2124 | Instance | 0x5803 2124 |
Description | Command Program Byte Enable Register: This register forms a per-byte enable for programming data. For data bytes to be programmed, a 1 must be written to the corresponding bit in this register. Normally, all bits are written to 1, allowing program of full flash words. However, leaving some bits 0 allows programming of 8-bit, 16-bit, 32-bit or 64-bit portions of a flash word. In addtion, the read verify command will ignore data bytes read from the flash in its comparison if the corresponding CMDBYTEN bit is 0. ECC data bytes are protected by the 1-2 MSB bits in this register, depending on the presence of ECC and the flash word data width. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by the NoWrapper hardware. This register is written to all 0 after the completion of all NoWrapper commands. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | |||||||||||
15:0 | VAL | Command Byte Enable value. A 1-bit per flash word byte value is placed in this register.
|
RW | 0xFFFF |
Address Offset | 0x0000 012C | ||
Physical Address | 0x5803 212C | Instance | 0x5803 212C |
Description | Command Program Data Index Register: When multiple data registers are available for multi-word program, this register can be written with an index which points to one of the data registers. When a write to CMDDATA* is done, the data will be written to the physical data register indexed by the value in this register. Up to 8 data registers can be present, so this register can be written with 0x0 to 0x7. If less than 8 data registers are present, successive MSB bits of this register are ignored when indexing the CMDDATA* registers. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by the NoWrapper hardware. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
1:0 | VAL | Data register index
|
RW | 0b00 |
Address Offset | 0x0000 0130 | ||
Physical Address | 0x5803 2130 | Instance | 0x5803 2130 |
Description | Command Data Register 0 This register forms the data for a command. For DATAWIDTH == 128:This register represents bits 31:0 of flash word data register 0. For DATAWIDTH == 64:This register represents bits 31:0 of flash word data register 0. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by the NoWrapper hardware. This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands. Use cases for the CMDDATA* registers are as follows: 1)Program - These registers contain the data to be programmed. 2)Erase - These registers are not used. 3)Read Verify - These registers contain data to be verified. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:0 | VAL | A 32-bit data value is placed in this field.
|
RW | 0xFFFF FFFF |
Address Offset | 0x0000 0134 | ||
Physical Address | 0x5803 2134 | Instance | 0x5803 2134 |
Description | Command Data Register 1 This register forms the data for a command. For DATAWIDTH == 128:This register represents bits 63:32 of flash word data register 0. For DATAWIDTH == 64:This register represents bits 63:32 of flash word data register 0. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to CMDSTAT.DONE being set by the NoWrapper hardware. This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands. Use cases for the CMDDATA* registers are as follows: 1)Program - These registers contain the data to be programmed. 2)Erase - These registers are not used. 3)Read Verify - These registers contain data to be verified. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:0 | VAL | A 32-bit data value is placed in this field.
|
RW | 0xFFFF FFFF |
Address Offset | 0x0000 0138 | ||
Physical Address | 0x5803 2138 | Instance | 0x5803 2138 |
Description | Command Data Register 2 This register forms the data for a command. For DATAWIDTH == 128:This register represents bits 95:64 of flash word data register 0. For DATAWIDTH == 64:This register represents bits 31:0 of flash word data register 1. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by the NoWrapper hardware. This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands. Use cases for the CMDDATA* registers are as follows: 1)Program - These registers contain the data to be programmed. 2)Erase - These registers are not used. 3)Read Verify - These registers contain data to be verified. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:0 | VAL | A 32-bit data value is placed in this field.
|
RW | 0xFFFF FFFF |
Address Offset | 0x0000 013C | ||
Physical Address | 0x5803 213C | Instance | 0x5803 213C |
Description | Command Data Register 3 This register forms the data for a command. For DATAWIDTH == 128:This register represents bits 127:96 of flash word data register 0. For DATAWIDTH == 64:This register represents bits 63:32 of flash word data register 1. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by the NoWrapper hardware. This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands. Use cases for the CMDDATA* registers are as follows: 1)Program - These registers contain the data to be programmed. 2)Erase - These registers are not used. 3)Read Verify - These registers contain data to be verified. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:0 | VAL | A 32-bit data value is placed in this field.
|
RW | 0xFFFF FFFF |
Address Offset | 0x0000 0140 | ||
Physical Address | 0x5803 2140 | Instance | 0x5803 2140 |
Description | Command Data Register 4 This register forms the data for a command. For DATAWIDTH == 128:This register represents bits 31:0 of flash word data register 1. For DATAWIDTH == 64:This register represents bits 31:0 of flash word data register 2. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by the NoWrapper hardware. This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands. Use cases for the CMDDATA* registers are as follows: 1)Program - These registers contain the data to be programmed. 2)Erase - These registers are not used. 3)Read Verify - These registers contain data to be verified. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:0 | VAL | A 32-bit data value is placed in this field. T
|
RW | 0xFFFF FFFF |
Address Offset | 0x0000 0144 | ||
Physical Address | 0x5803 2144 | Instance | 0x5803 2144 |
Description | Command Data Register 5 This register forms the data for a command. For DATAWIDTH == 128:This register represents bits 63:32 of flash word data register 1. For DATAWIDTH == 64:This register represents bits 63:32 of flash word data register 2. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by the NoWrapper hardware. This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands. Use cases for the CMDDATA* registers are as follows: 1)Program - These registers contain the data to be programmed. 2)Erase - These registers are not used. 3)Read Verify - These registers contain data to be verified. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:0 | VAL | A 32-bit data value is placed in this field.
|
RW | 0xFFFF FFFF |
Address Offset | 0x0000 0148 | ||
Physical Address | 0x5803 2148 | Instance | 0x5803 2148 |
Description | Command Data Register 6 This register forms the data for a command. For DATAWIDTH == 128:This register represents bits 95:64 of flash word data register 1. For DATAWIDTH == 64:This register represents bits 31:0 of flash word data register 3. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by the NoWrapper hardware. This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands. Use cases for the CMDDATA* registers are as follows: 1)Program - These registers contain the data to be programmed. 2)Erase - These registers are not used. 3)Read Verify - These registers contain data to be verified. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:0 | VAL | A 32-bit data value is placed in this field.
|
RW | 0xFFFF FFFF |
Address Offset | 0x0000 014C | ||
Physical Address | 0x5803 214C | Instance | 0x5803 214C |
Description | Command Data Register 7 This register forms the data for a command. For DATAWIDTH == 128:This register represents bits 127:96 of flash word data register 1. For DATAWIDTH == 64:This register represents bits 63:32 of flash word data register 3. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by the NoWrapper hardware. This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands. Use cases for the CMDDATA* registers are as follows: 1)Program - These registers contain the data to be programmed. 2)Erase - These registers are not used. 3)Read Verify - These registers contain data to be verified. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:0 | VAL | A 32-bit data value is placed in this field.
|
RW | 0xFFFF FFFF |
Address Offset | 0x0000 0150 | ||
Physical Address | 0x5803 2150 | Instance | 0x5803 2150 |
Description | Command Data Register 8 This register forms the data for a command. For DATAWIDTH == 128:This register represents bits 31:0 of flash word data register 2. For DATAWIDTH == 64:This register represents bits 31:0 of flash word data register 4. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by the NoWrapper hardware. This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands. Use cases for the CMDDATA* registers are as follows: 1)Program - These registers contain the data to be programmed. 2)Erase - These registers are not used. 3)Read Verify - These registers contain data to be verified. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:0 | VAL | A 32-bit data value is placed in this field.
|
RW | 0xFFFF FFFF |
Address Offset | 0x0000 0154 | ||
Physical Address | 0x5803 2154 | Instance | 0x5803 2154 |
Description | Command Data Register 9 This register forms the data for a command. For DATAWIDTH == 128:This register represents bits 63:32 of flash word data register 2. For DATAWIDTH == 64:This register represents bits 63:32 of flash word data register 4. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by the NoWrapper hardware. This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands. Use cases for the CMDDATA* registers are as follows: 1)Program - These registers contain the data to be programmed. 2)Erase - These registers are not used. 3)Read Verify - These registers contain data to be verified. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:0 | VAL | A 32-bit data value is placed in this field.
|
RW | 0xFFFF FFFF |
Address Offset | 0x0000 0158 | ||
Physical Address | 0x5803 2158 | Instance | 0x5803 2158 |
Description | Command Data Register 10 This register forms the data for a command. For DATAWIDTH == 128:This register represents bits 95:64 of flash word data register 2. For DATAWIDTH == 64:This register represents bits 31:0 of flash word data register 5. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by the NoWrapper hardware. This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands. Use cases for the CMDDATA* registers are as follows: 1)Program - These registers contain the data to be programmed. 2)Erase - These registers are not used. 3)Read Verify - These registers contain data to be verified. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:0 | VAL | A 32-bit data value is placed in this field.
|
RW | 0xFFFF FFFF |
Address Offset | 0x0000 015C | ||
Physical Address | 0x5803 215C | Instance | 0x5803 215C |
Description | Command Data Register 11 This register forms the data for a command. For DATAWIDTH == 128:This register represents bits 127:96 of flash word data register 2. For DATAWIDTH == 64:This register represents bits 63:32 of flash word data register 5. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by the NoWrapper hardware. This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands. Use cases for the CMDDATA* registers are as follows: 1)Program - These registers contain the data to be programmed. 2)Erase - These registers are not used. 3)Read Verify - These registers contain data to be verified. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:0 | VAL | A 32-bit data value is placed in this field.
|
RW | 0xFFFF FFFF |
Address Offset | 0x0000 0160 | ||
Physical Address | 0x5803 2160 | Instance | 0x5803 2160 |
Description | Command Data Register 12 This register forms the data for a command. For DATAWIDTH == 128:This register represents bits 31:0 of flash word data register 3. For DATAWIDTH == 64:This register represents bits 31:0 of flash word data register 6. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by the NoWrapper hardware. This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands. Use cases for the CMDDATA* registers are as follows: 1)Program - These registers contain the data to be programmed. 2)Erase - These registers are not used. 3)Read Verify - These registers contain data to be verified. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:0 | VAL | A 32-bit data value is placed in this field.
|
RW | 0xFFFF FFFF |
Address Offset | 0x0000 0164 | ||
Physical Address | 0x5803 2164 | Instance | 0x5803 2164 |
Description | Command Data Register 13 This register forms the data for a command. For DATAWIDTH == 128:This register represents bits 63:32 of flash word data register 3. For DATAWIDTH == 64:This register represents bits 63:32 of flash word data register 6. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by the NoWrapper hardware. This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands. Use cases for the CMDDATA* registers are as follows: 1)Program - These registers contain the data to be programmed. 2)Erase - These registers are not used. 3)Read Verify - These registers contain data to be verified. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:0 | VAL | A 32-bit data value is placed in this field.
|
RW | 0xFFFF FFFF |
Address Offset | 0x0000 0168 | ||
Physical Address | 0x5803 2168 | Instance | 0x5803 2168 |
Description | Command Data Register 14 This register forms the data for a command. For DATAWIDTH == 128:This register represents bits 95:64 of flash word data register 3. For DATAWIDTH == 64:This register represents bits 31:0 of flash word data register 7. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by the NoWrapper hardware. This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands. Use cases for the CMDDATA* registers are as follows: 1)Program - These registers contain the data to be programmed. 2)Erase - These registers are not used. 3)Read Verify - These registers contain data to be verified. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:0 | VAL | A 32-bit data value is placed in this field.
|
RW | 0xFFFF FFFF |
Address Offset | 0x0000 016C | ||
Physical Address | 0x5803 216C | Instance | 0x5803 216C |
Description | Command Data Register 15 This register forms the data for a command. For DATAWIDTH == 128:This register represents bits 127:96 of flash word data register 3. For DATAWIDTH == 64:This register represents bits 63:32 of flash word data register 7. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by the NoWrapper hardware. This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all NoWrapper commands. Use cases for the CMDDATA* registers are as follows: 1)Program - These registers contain the data to be programmed. 2)Erase - These registers are not used. 3)Read Verify - These registers contain data to be verified. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:0 | VAL | A 32-bit data value is placed in this field.
|
RW | 0xFFFF FFFF |
Address Offset | 0x0000 01D0 | ||
Physical Address | 0x5803 21D0 | Instance | 0x5803 21D0 |
Description | Command WriteErase Protect A Register This register allows the first 32 sectors of the main region to be protected from program or erase, with 1 bit protecting each sector. If the main region size is smaller than 32 sectors, then this register provides protection for the whole region. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by the NoWrapper hardware. In addition, this register is used to aggregate masking for sectors that do not require additional erase pulses during bank erase operations, and will be written to all 1 after the completion of all NoWrapper commands. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:0 | VAL | Each bit protects 1 sector. bit [0]:When 1, sector 0 of the flash memory will be protected from program and erase. bit [1]:When 1, sector 1 of the flash memory will be protected from program and erase. : : bit [31]:When 1, sector 31 of the flash memory will be protected from program and erase.
|
RW | 0xFFFF FFFF |
Address Offset | 0x0000 01D4 | ||
Physical Address | 0x5803 21D4 | Instance | 0x5803 21D4 |
Description | Command WriteErase Protect B Register This register allows main region sectors to be protected from program and erase. Each bit corresponds to a group of 8 sectors. There are 3 cases for how these protect bits are applied: 1. Single-bank system: In the case where only a single flash bank is present, the first 32 sectors are protected via the CMDWEPROTA register. Thus, the protection give by the bits in CMDWEPROTB begin with sector 32. 2. Multi-bank system, Bank 0: When multiple flash banks are present, the first 32 sectors of bank 0 are protected via the CMDWEPROTA register. Thus, only bits 4 and above of CMDWEPROTB would be applicable to bank 0. The protection of bit 4 and above would begin at sector 32. Bits 3:0 of WEPROTB are ignored for bank 0. 3. Multi-bank system, Banks 1-N: For banks other than bank 0 in a multi-bank system, CMDWEPROTA has no effect, so the bits in CMDWEPROTB will protect these banks starting from sector 0. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by the NoWrapper hardware. In addition, this register is used to aggregate masking for sectors that do not require additional erase pulses during bank erase operations, and will be written to all 1 after the completion of all NoWrapper commands. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:0 | VAL | Each bit protects a group of 8 sectors. When a bit is 1, the associated 8 sectors in the flash will be protected from program and erase. A maximum of 256 sectors can be protected with this register.
|
RW | 0xFFFF FFFF |
Address Offset | 0x0000 0210 | ||
Physical Address | 0x5803 2210 | Instance | 0x5803 2210 |
Description | Command WriteErase Protect Non-Main Register This register allows non-main region region sectors to be protected from program and erase. Each bit corresponds to 1 sector. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by the NoWrapper hardware. In addition, this register is used to aggregate masking for sectors that do not require additional erase pulses during bank erase operations, and will be written to all 1 after the completion of all NoWrapper commands. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
0 | VAL | Each bit protects 1 sector. bit [0]:When 1, sector 0 of the non-main region will be protected from program and erase. bit [1]:When 1, sector 1 of the non-main region will be protected from program and erase. : : bit [31]:When 1, sector 31 of the non-main will be protected from program and erase.
|
RW | 1 |
Address Offset | 0x0000 0214 | ||
Physical Address | 0x5803 2214 | Instance | 0x5803 2214 |
Description | Command WriteErase Protect Trim Register This register allows trim region sectors to be protected from program and erase. Each bit corresponds to 1 sector. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by the NoWrapper hardware. In addition, this register is used to aggregate masking for sectors that do not require additional erase pulses during bank erase operations, and will be written to all 1 after the completion of all NoWrapper commands. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
0 | VAL | Each bit protects 1 sector. bit [0]:When 1, sector 0 of the engr region will be protected from program and erase. bit [1]:When 1, sector 1 of the engr region will be protected from program and erase. : : bit [31]:When 1, sector 31 of the engr region will be protected from program and erase.
|
RW | 1 |
Address Offset | 0x0000 0218 | ||
Physical Address | 0x5803 2218 | Instance | 0x5803 2218 |
Description | Command WriteErase Protect Engr Register This register allows engr region sectors to be protected from program and erase. Each bit corresponds to 1 sector. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by the NoWrapper hardware. In addition, this register is used to aggregate masking for sectors that do not require additional erase pulses during bank erase operations, and will be written to all 1 after the completion of all NoWrapper commands. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
0 | VAL | Each bit protects 1 sector. bit [0]:When 1, sector 0 of the engr region will be protected from program and erase. bit [1]:When 1, sector 1 of the engr region will be protected from program and erase. : : bit [31]:When 1, sector 31 of the engr region will be protected from program and erase.
|
RW | 1 |
Address Offset | 0x0000 03B0 | ||
Physical Address | 0x5803 23B0 | Instance | 0x5803 23B0 |
Description | Command Configuration Register This register configures specific capabilities of the state machine for related to the execution of a command. This register is blocked for writes after CMDEXEC is written to a 1 and prior to STATCMD.DONE being set by the hardware to indicate that command execution has completed. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
32:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
3:0 | WAITSTATE | Wait State setting for program verify, erase verify and read verify
|
RW | 0x2 |
Address Offset | 0x0000 03B4 | ||
Physical Address | 0x5803 23B4 | Instance | 0x5803 23B4 |
Description | Pulse Counter Configuration Register This register allows further configuration of maximum pulse counts for program and erase operations. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by the NoWrapper hardware. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
32:12 | RESERVED12 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 | |||||||||||
11:4 | MAXPCNTVAL | Override maximum pulse counter with this value. If MAXPCNTOVR = 0, then this field is ignored. If MAXPCNTOVR = 1 and MAXERSPCNTOVR = 0, then this value will be used to override the max pulse count for both program and erase. Full max value will be {4'h0, MAXPCNTVAL} . If MAXPCNTOVR = 1 and MAXERSPCNTOVR = 1, then this value will be used to override the max pulse count for program only. Full max value will be {4'h0, MAXPCNTVAL}.
|
RW | 0x00 | |||||||||||
3:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||
0 | MAXPCNTOVR | Override hard-wired maximum pulse count. If MAXERSPCNTOVR is not set, then setting this value alone will override the max pulse count for both program and erase. If MAXERSPCNTOVR is set, then this bit will only control the max pulse count setting for program. By default, this bit is 0, and a hard-wired max pulse count is used.
|
RW | 0 |
Address Offset | 0x0000 03D0 | ||
Physical Address | 0x5803 23D0 | Instance | 0x5803 23D0 |
Description | Command Status Register This register contains status regarding completion and errors of command execution. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:13 | RESERVED13 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 | |||||||||||
12 | FAILMISC | Command failed due to error other than write/erase protect violation or verify error. This is an extra bit in case a new failure mechanism is added which requires a status bit.
|
RO | 0 | |||||||||||
8 | FAILINVDATA | Program command failed because an attempt was made to program a stored 0 value to a 1.
|
RO | 0 | |||||||||||
7 | FAILMODE | Command failed because a bank has been set to a mode other than READ. Program and Erase commands cannot be initiated unless all banks are in READ mode.
|
RO | 0 | |||||||||||
6 | FAILILLADDR | Command failed due to the use of an illegal address
|
RO | 0 | |||||||||||
5 | FAILVERIFY | Command failed due to verify error
|
RO | 0 | |||||||||||
4 | FAILWEPROT | Command failed due to Write/Erase Protect Sector Violation
|
RO | 0 | |||||||||||
3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||
2 | CMDINPROGRESS | Command In Progress
|
RO | 0 | |||||||||||
1 | CMDPASS | Command Pass - valid when CMD_DONE field is 1
|
RO | 0 | |||||||||||
0 | CMDDONE | Command Done
|
RO | 0 |
Address Offset | 0x0000 03D4 | ||
Physical Address | 0x5803 23D4 | Instance | 0x5803 23D4 |
Description | Current Address Counter Value Read only register giving read access to the state machine current address. A bank id, region id and address are stored in this register and are incremented as necessary during execution of a command. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||
31:26 | RESERVED26 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 | ||||||||||||||||||||
25:21 | BANKID | Current Bank ID A bank indicator is stored in this register which represents the current bank on which the state machine is operating. There is 1 bit per bank.
|
RO | 0b0 0001 | ||||||||||||||||||||
20:16 | REGIONID | Current Region ID A region indicator is stored in this register which represents the current flash region on which the state machine is operating.
|
RO | 0b0 0000 | ||||||||||||||||||||
15:0 | BANKADDR | Current Bank Address A bank offset address is stored in this register.
|
RO | 0x0000 |
Address Offset | 0x0000 03D8 | ||
Physical Address | 0x5803 23D8 | Instance | 0x5803 23D8 |
Description | Current Pulse Count Register: Read only register giving read access to the state machine current pulse count value for program/erase operations. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:12 | RESERVED12 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 0000 | |||||||||||
11:0 | PULSECNT | Current Pulse Counter Value
|
RO | 0x000 |
Address Offset | 0x0000 03DC | ||
Physical Address | 0x5803 23DC | Instance | 0x5803 23DC |
Description | Mode Status Register Indicates any banks which not in READ mode, and it indicates the mode which the bank(s) are in. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||||||||||||||||||||
17 | BANK1TRDY | Bank 1T Ready. Bank(s) are ready for 1T access. This is accomplished when the bank and pump have been trimmed.
|
RO | 0 | ||||||||||||||||||||||||||||||||||||||
16 | BANK2TRDY | Bank 2T Ready. Bank(s) are ready for 2T access. This is accomplished when the pump has fully driven power rails to the bank(s).
|
RO | 0 | ||||||||||||||||||||||||||||||||||||||
11:8 | BANKMODE | Indicates mode of bank(s) that are not in READ mode
|
RO | 0x0 | ||||||||||||||||||||||||||||||||||||||
7:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 | ||||||||||||||||||||||||||||||||||||||
0 | BANKNOTINRD | Bank not in read mode. Indicates which banks are not in READ mode. There is 1 bit per bank.
|
RO | 0 |
Address Offset | 0x0000 03F0 | ||
Physical Address | 0x5803 23F0 | Instance | 0x5803 23F0 |
Description | Global Info 0 Register Read only register detailing information about sector size and number of banks present. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
18:16 | NUMBANKS | Number of banks instantiated Minimum:1 Maximum:5
|
RO | 0b010 | |||||||||||
15:0 | SECTORSIZE | Sector size in bytes
|
RO | 0x0800 |
Address Offset | 0x0000 03F4 | ||
Physical Address | 0x5803 23F4 | Instance | 0x5803 23F4 |
Description | Global Info 1 Register Read only register detailing information about data, ecc and redundant data widths in bits. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||||||||
31:19 | RESERVED19 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 | ||||||||||||||
18:16 | REDWIDTH | Redundant data width in bits
|
RO | 0b100 | ||||||||||||||
12:8 | ECCWIDTH | ECC data width in bits
|
RO | 0b0 0000 | ||||||||||||||
7:0 | DATAWIDTH | Data width in bits
|
RO | 0x80 |
Address Offset | 0x0000 03F8 | ||
Physical Address | 0x5803 23F8 | Instance | 0x5803 23F8 |
Description | Global Info 2 Register Read only register detailing information about the number of data registers present. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | |||||||||||
3:0 | DATAREGISTERS | Number of data registers present.
|
RO | 0x4 |
Address Offset | 0x0000 0400 | ||
Physical Address | 0x5803 2400 | Instance | 0x5803 2400 |
Description | Bank Info 0 Register for bank 0. Read only register detailing information about Main region size in the bank. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:12 | RESERVED12 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 0000 | |||||||||||
11:0 | MAINSIZE | Main region size in sectors Minimum:0x8 (8) Maximum:0x200 (512)
|
RO | 0x100 |
Address Offset | 0x0000 0404 | ||
Physical Address | 0x5803 2404 | Instance | 0x5803 2404 |
Description | Bank Info1 Register for bank 0. Read only register detailing information about Non-Main, Trim, and Engr region sizes in the bank. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 | |||||||||||
23:16 | ENGRSIZE | Engr region size in sectors Minimum:0x0 (0) Maximum:0x10 (16)
|
RO | 0x01 | |||||||||||
15:8 | TRIMSIZE | Trim region size in sectors Minimum:0x0 (0) Maximum:0x10 (16)
|
RO | 0x01 | |||||||||||
7:0 | NONMAINSIZE | Non-main region size in sectors Minimum:0x0 (0) Maximum:0x10 (16)
|
RO | 0x01 |
Address Offset | 0x0000 0410 | ||
Physical Address | 0x5803 2410 | Instance | 0x5803 2410 |
Description | Bank Info 0 Register for bank 1. Read only register detailing information about Main region size in the bank. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:12 | RESERVED12 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 0000 | |||||||||||
11:0 | MAINSIZE | Main region size in sectors Minimum:0x8 (8) Maximum:0x200 (512)
|
RO | 0x100 |
Address Offset | 0x0000 0414 | ||
Physical Address | 0x5803 2414 | Instance | 0x5803 2414 |
Description | Bank Info1 Register for bank 1. Read only register detailing information about Non-Main, Trim, and Engr region sizes in the bank. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 | |||||||||||
23:16 | ENGRSIZE | Engr region size in sectors Minimum:0x0 (0) Maximum:0x10 (16)
|
RO | 0x01 | |||||||||||
15:8 | TRIMSIZE | Trim region size in sectors
|
RO | 0x01 | |||||||||||
7:0 | NONMAINSIZE | Non-main region size in sectors
|
RO | 0x01 |
Address Offset | 0x0000 0500 | ||
Physical Address | 0x5803 2500 | Instance | 0x5803 2500 |
Description | DFT Enable Register Allows control of NoWrapper test features. When set, DFT* registers in this aperture open for write access. When cleared, DFT* registers are read-only. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by the NoWrapper hardware. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
0 | ENABLE | Enable Test Features
|
RW | 0 |
Address Offset | 0x0000 0504 | ||
Physical Address | 0x5803 2504 | Instance | 0x5803 2504 |
Description | DFT Command Control Register This register configures specific capabilities for test. This register is only writable when DFTEN.ENABLE is set. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by the NoWrapper hardware. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||
31:28 | DTBMUXSEL | DTB Mux Select This field will form the select for the primary DTB mux. This mux selects up to 16 sets of 32-bit fields of internal signals to be present to the 32-bit DTB output.
|
RW | 0x0 | ||||||||||||||
27:21 | RESERVED21 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 | ||||||||||||||
20 | STOPVERONFAIL | Stop read verify on fail. If this bit is set, read verify will halt when the first verify fail is detected. If command is program or erase, another program or erase pulse will be executed. If command is read verify, comand will terminate.
|
RW | 0 | ||||||||||||||
18 | ODDROWINVDATA | Invert data at odd row addresses for program or verify. The LSB of the row address is bit [4] of the bank address. This bit only applies when pattern data is used; i.e. the DATAPATEN bit is set. It will have no effect if CMDDATA is used.
|
RW | 0 | ||||||||||||||
17 | ODDWORDINVDATA | Invert data at odd bank addresses for program or verify. This bit only applies when pattern data is used; i.e. the DATAPATEN bit is set. It will have no effect if CMDDATA is used.
|
RW | 0 | ||||||||||||||
16 | ALWAYSINVDATA | Invert data always for program or verify. This bit only applies when pattern data is used; i.e. the DATAPATEN bit is set. It will have no effect if CMDDATA is used.
|
RW | 0 | ||||||||||||||
15:13 | DATAPATSEL | Select data pattern. Valid when DATAPATEN bit is set to 1. Overrides CMDDATA registers for program or verify.
|
RW | 0b000 | ||||||||||||||
12 | DATAPATEN | Enable data pattern. Data pattern select in DATAPATSEL field will override data from CMDDATA registers for use as program or verify data.
|
RW | 0 | ||||||||||||||
11:10 | RESERVED10 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||||||||||||||
9 | PULSECNTLDDIS | Override pulse counter enable. When set, the state machine pulse counter will not be loaded when a command is initiated.
|
RW | 0 | ||||||||||||||
8 | ADDRCNTLDDIS | Override address counter enable. When set, the state machine address counter will not be loaded when a command is initiated.
|
RW | 0 | ||||||||||||||
7:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||||||||||||||
5 | REDMATCHFORCE | Force redundancy match. If set to 1, repair configuration encoded in the flash bank trim will be forced for every access.
|
RW | 0 | ||||||||||||||
4 | REDMATCHDIS | Disable redundancy matching. Any repair configuration encoded into the bank trim bits is disabled.
|
RW | 0 | ||||||||||||||
3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||||||||||||||
2 | AMX2TDIS | 2T address mux disable control. When set to 1 2T address shifting is disabled. This bit should only be enabled for reads. Indeterminate behavior will result if this bit is set during program/erase. Furthermore, only reads done via a READVERIFY command will be guaranteed to work properly. Reads via the FBAP port are not guaranteed to operate.
|
RW | 0 | ||||||||||||||
1 | FORCE2TEN | Force 2T Enable - Force 2T access to regions that are designated as 1T. Regions designated as 2T will still be accessed as 2T.
|
RW | 0 | ||||||||||||||
0 | FORCE1TEN | Force 1T Enable - Force 1T access to regions that are designated as 2T. Regions designated as 1T will still be accessed as 1T.
|
RW | 0 |
Address Offset | 0x0000 0508 | ||
Physical Address | 0x5803 2508 | Instance | 0x5803 2508 |
Description | DFT Timer Control Register This allows some configuration of timing values for various phases of flash operations for test. These time values are hard-coded for functional execution. This register is only writable when DFT.ENABLE is set. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by the NoWrapper hardware. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||
31 | RESERVED31 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||||||||||||||||||||
30:28 | TIMERCLOCKOVR | Override Timer clock frequency using an ICG-based clock divide mechanism. To divide the timer clock, pulses can be skipped based on settings in this field. By default, this field is 0, which corresponds to no division on the timer clock.
|
RW | 0b000 | |||||||||||||||||||||||||||||
27:12 | PEPULSETIMEVAL | Program/Erase Pulse Time Value If operation is a program, this value gets loaded into bits [15:0] of the timer when the PEPULSETIMEVALOVR field is set to 1. If operation is an erase, this value gets loaded into bits [19:4] of the timer when the PEPULSETIMEVALOVR field is set to 1.
|
RW | 0x0000 | |||||||||||||||||||||||||||||
11:9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||||||||||||||||||||
8 | PEPULSETIMEOVR | Override Program/Erase Pulse Time If set, this will force the program or erase pulse time to be overridden with the value in the PEPULSETIMEVAL field. If not set, then a hard-coded value will be used for this pulse time.
|
RW | 0 | |||||||||||||||||||||||||||||
7 | READMODETIME | Read Mode Change Time
|
RW | 0 | |||||||||||||||||||||||||||||
6 | PEVHOLDTIME | Program/Erase Verify Hold Time
|
RW | 0 | |||||||||||||||||||||||||||||
5 | PEVSETUPTIME | Program/Erase Verify Setup Time
|
RW | 0 | |||||||||||||||||||||||||||||
4 | PEVMODETIME | Program/Erase Verify Mode Change Time
|
RW | 0 | |||||||||||||||||||||||||||||
3 | PEHOLDTIME | Program/Erase Hold Time
|
RW | 0 | |||||||||||||||||||||||||||||
2 | PPVWORDLINETIME | Program and Program Verify Wordline Switching Time
|
RW | 0 | |||||||||||||||||||||||||||||
1 | PVHVSETUPTIME | Program VHV Setup Time
|
RW | 0 | |||||||||||||||||||||||||||||
0 | PESETUPTIME | Program/Erase Setup Time
|
RW | 0 |
Address Offset | 0x0000 050C | ||
Physical Address | 0x5803 250C | Instance | 0x5803 250C |
Description | DFT EXECUTEZ control register. This register allows direct control of the EXECUTEZ to bank and pump for test. This register is only writable when DFTEN.ENABLE is set. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by the NoWrapper hardware. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
1 | EXEZ_OVR | Override value to be applied to EXECUTEZ
|
RW | 1 | |||||||||||
0 | EXEZOVREN | Enable override of EXECUTEZ Note that when this bit is set, NoWrapper has control of the bank pins.
|
RW | 0 |
Address Offset | 0x0000 0510 | ||
Physical Address | 0x5803 2510 | Instance | 0x5803 2510 |
Description | DFT Pump Clock Test Control Register. This register controls hardware features that allow the pump clock to be characterized for trim development. This register is only writable when DFTEN.ENABLE is set. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by the NoWrapper hardware. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
0 | ENABLE | Enable the state machine which sequences measurement of pump clock frequency.
|
RW | 0 |
Address Offset | 0x0000 0514 | ||
Physical Address | 0x5803 2514 | Instance | 0x5803 2514 |
Description | DFT Pump Clock Test Status Register. This register shows status reported by the hardware features that allow the pump clock to be characterized for trim development. This register is only writable when DFTEN.ENABLE is set. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
15:4 | CLOCKCNT | Indicates the core clock count captured during the pump clock measurement.
|
RO | 0x000 | |||||||||||
3:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||
0 | BUSY | Indicates that a pump clock measurement is in progress.
|
RO | 0 |
Address Offset | 0x0000 0540 | ||
Physical Address | 0x5803 2540 | Instance | 0x5803 2540 |
Description | DFT Redundancy Data Register 0 This register is used when testing the redundant columns in the flash. It acts as an extension of the CMDDATA* registers. The bits in this register correspond to flash data word register 0. In addition, this register is used to aggregate masking for bits that do not require additional program pulses during program operations. The original data written to this register will be lost during program command execution. Use cases for this register are as follows: 1)Program - Contains the data to be programmed. 2)Erase - Not used. 3)Read Verify - Contains data to be verified. This register is only writable when DFTEN.ENABLE is set. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by the NoWrapper hardware. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | ||
3:0 | VAL | Data for redundant bits | RW | 0xF |
Address Offset | 0x0000 0544 | ||
Physical Address | 0x5803 2544 | Instance | 0x5803 2544 |
Description | DFT Redundancy Data Register 1 This register is used when testing the redundant columns in the flash. It acts as an extension of the CMDDATA* registers. The bits in this register correspond to flash data word register 1. In addition, this register is used to aggregate masking for bits that do not require additional program pulses during program operations. The original data written to this register will be lost during program command execution. Use cases for this register are as follows: 1)Program - Contains the data to be programmed. 2)Erase - Not used. 3)Read Verify - Contains data to be verified. This register is only writable when DFTEN.ENABLE is set. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by the NoWrapper hardware. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | ||
3:0 | VAL | Data for redundant bits | RW | 0xF |
Address Offset | 0x0000 0548 | ||
Physical Address | 0x5803 2548 | Instance | 0x5803 2548 |
Description | DFT Redundancy Data Register 2 This register is used when testing the redundant columns in the flash. It acts as an extension of the CMDDATA* registers. The bits in this register correspond to flash data word register 2. In addition, this register is used to aggregate masking for bits that do not require additional program pulses during program operations. The original data written to this register will be lost during program command execution. Use cases for this register are as follows: 1)Program - Contains the data to be programmed. 2)Erase - Not used. 3)Read Verify - Contains data to be verified. This register is only writable when DFTEN.ENABLE is set. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by the NoWrapper hardware. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | ||
3:0 | VAL | Data for redundant bits | RW | 0xF |
Address Offset | 0x0000 054C | ||
Physical Address | 0x5803 254C | Instance | 0x5803 254C |
Description | DFT Redundancy Data Register 3 This register is used when testing the redundant columns in the flash. It acts as an extension of the CMDDATA* registers. The bits in this register correspond to flash data word register 3. In addition, this register is used to aggregate masking for bits that do not require additional program pulses during program operations. The original data written to this register will be lost during program command execution. Use cases for this register are as follows: 1)Program - Contains the data to be programmed. 2)Erase - Not used. 3)Read Verify - Contains data to be verified. This register is only writable when DFTEN.ENABLE is set. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by the NoWrapper hardware. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | ||
3:0 | VAL | Data for redundant bits | RW | 0xF |
Address Offset | 0x0000 0560 | ||
Physical Address | 0x5803 2560 | Instance | 0x5803 2560 |
Description | DFT Pump Control Register This allows some configuration of pump parameters during test. This register is only writable when DFTEN.ENABLE is set. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by the NoWrapper hardware. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:19 | RESERVED19 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 | |||||||||||
18:16 | IREFEVCTL | IREFEV control IREFVRD, REFTC, IREFCONST, IREFCCOR blocks in IREFEV | RW | 0b000 | |||||||||||
15:12 | CONFIGPMP | Pump configuration control. LP, HP operation | RW | 0x1 | |||||||||||
11:10 | RESERVED10 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | |||||||||||
9 | SSEN | Dither control for oscillator Enumeration: 0: Disable Dither 1: Enable Dither
|
RW | 0 | |||||||||||
8 | PUMPCLKEN | Allows direct control of the pump oscillator which is used to generate pumpclk. Normally, enable/disable of pumpclk is under NoWrapper state machine control. This bit allows system to enable the clock independently.
|
RW | 0 | |||||||||||
7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||
6:0 | TCR | TCR test mode to be applied to the pump
|
RW | 0b000 0000 |
Address Offset | 0x0000 0564 | ||
Physical Address | 0x5803 2564 | Instance | 0x5803 2564 |
Description | DFT Bank Control Register This allows some configuration of bank parameters during test. This register is only writable when DFTEN.ENABLE is set. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by the NoWrapper hardware. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
8 | TEZ | When set, TEZ is asserted to the flash banks. Which banks get the asserted signal is determined by the BANKSELECT field in CMDCTL. 0x0 Do no assert TEZ 0x1 Assert TEZ
|
RW | 1 | |||||||||||
7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||
6:0 | TCR | TCR test mode to be applied to the bank
|
RW | 0b000 0000 |
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