UDMACC26XX.h
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103 #ifndef ti_drivers_UDMACC26XX__include
104 #define ti_drivers_UDMACC26XX__include
105 
106 #include <stdint.h>
107 #include <stdbool.h>
108 
109 #include <ti/drivers/Power.h>
111 
112 #include <ti/devices/DeviceFamily.h>
113 #include DeviceFamily_constructPath(inc/hw_types.h)
114 #include DeviceFamily_constructPath(driverlib/udma.h)
115 
116 #ifdef __cplusplus
117 extern "C" {
118 #endif
119 
130 /* Add DMACC26XX_STATUS_* macros here */
131 
144 /* Add DMACC26XX_CMD_* macros here */
145 
149 #if !defined(UDMACC26XX_CONFIG_BASE) && \
150  (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X2_CC26X2)
151  /* On CC13X2, CC13X2X7, CC26X2, and CC26X2X7 devices, the uDMA table needs
152  * to be offset a few kB since the ROM area of SRAM is placed at the start
153  * of SRAM on those devices.
154  */
155  #define UDMACC26XX_CONFIG_BASE 0x20001800
156 #elif !defined(UDMACC26XX_CONFIG_BASE) && \
157  (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X1_CC26X1 || \
158  DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4)
159  /* Since there is no ROM area of SRAM on the CC13X1, CC26X1, CC13X4, and
160  * CC26X4 devices, we can move the uDMA table closer to the start of SRAM.
161  * This improves the linker efficiency when using dynamically sized heaps.
162  */
163  #define UDMACC26XX_CONFIG_BASE 0x20000400
164 #elif !defined(UDMACC26XX_CONFIG_BASE)
165  #define UDMACC26XX_CONFIG_BASE 0x20000400
166 #endif
167 
169 #if(UDMACC26XX_CONFIG_BASE & 0x3FF)
170  #error "Base address for DMA control table 'UDMACC26XX_CONFIG_BASE' must be 1024 bytes aligned."
171 #endif
172 
174 #if defined(__IAR_SYSTEMS_ICC__)
175 #define ALLOCATE_CONTROL_TABLE_ENTRY(ENTRY_NAME, CHANNEL_INDEX) \
176 __no_init static volatile tDMAControlTable ENTRY_NAME @ UDMACC26XX_CONFIG_BASE + CHANNEL_INDEX * sizeof(tDMAControlTable)
177 #elif defined(__TI_COMPILER_VERSION__) || defined(__clang__)
178 #define ALLOCATE_CONTROL_TABLE_ENTRY(ENTRY_NAME, CHANNEL_INDEX) \
179 static volatile tDMAControlTable ENTRY_NAME __attribute__((retain, location(\
180  UDMACC26XX_CONFIG_BASE + CHANNEL_INDEX * sizeof(tDMAControlTable))))
181 #elif defined(__GNUC__)
182 #define ALLOCATE_CONTROL_TABLE_ENTRY(ENTRY_NAME, CHANNEL_INDEX) \
183  extern int UDMACC26XX_ ## ENTRY_NAME ## _is_placed; __attribute__ ((section("."#ENTRY_NAME))) static volatile tDMAControlTable ENTRY_NAME = {&UDMACC26XX_ ## ENTRY_NAME ## _is_placed}
184 #else
185 #error "don't know how to define ALLOCATE_CONTROL_TABLE_ENTRY for this toolchain"
186 #endif
187 
189 #define UDMACC26XX_SET_TRANSFER_SIZE(SIZE) (((SIZE - 1) << UDMA_XFER_SIZE_S) & UDMA_XFER_SIZE_M)
190 
191 #define UDMACC26XX_GET_TRANSFER_SIZE(CONTROL) (((CONTROL & UDMA_XFER_SIZE_M) >> UDMA_XFER_SIZE_S) + 1)
192 
196 typedef struct {
197  bool isOpen;
198  HwiP_Struct hwi;
200 
204 typedef struct {
205  uint32_t baseAddr;
206  PowerCC26XX_Resource powerMngrId;
207  uint8_t intNum;
229  uint8_t intPriority;
231 
235 typedef struct {
236  void *object;
237  void const *hwAttrs;
239 
244 
245 /* Extern'd hwiIntFxn */
246 extern void UDMACC26XX_hwiIntFxn(uintptr_t callbacks);
247 
260 __STATIC_INLINE void UDMACC26XX_init(UDMACC26XX_Handle handle)
261 {
262  UDMACC26XX_Object *object;
263 
264  /* Get the pointer to the object */
265  object = (UDMACC26XX_Object *)(handle->object);
266 
267  /* mark the module as available */
268  object->isOpen = false;
269 }
270 
286 extern UDMACC26XX_Handle UDMACC26XX_open(void);
287 
301 __STATIC_INLINE void UDMACC26XX_channelEnable(UDMACC26XX_Handle handle, uint32_t channelBitMask)
302 {
303  UDMACC26XX_HWAttrs const *hwAttrs;
304 
305  /* Get the pointer to the hwAttrs */
306  hwAttrs = (UDMACC26XX_HWAttrs *)(handle->hwAttrs);
307 
308  /* Enable DMA channel */
309  HWREG(hwAttrs->baseAddr + UDMA_O_SETCHANNELEN) = channelBitMask;
310 }
311 
330 __STATIC_INLINE bool UDMACC26XX_channelDone(UDMACC26XX_Handle handle, uint32_t channelBitMask)
331 {
332  UDMACC26XX_HWAttrs const *hwAttrs;
333 
334  /* Get the pointer to the hwAttrs */
335  hwAttrs = (UDMACC26XX_HWAttrs *)(handle->hwAttrs);
336 
337  /* Check if REQDONE is set for a specific channel */
338  return (uDMAIntStatus(hwAttrs->baseAddr) & channelBitMask) ? true : false;
339 }
340 
358 __STATIC_INLINE void UDMACC26XX_clearInterrupt(UDMACC26XX_Handle handle, uint32_t channelBitMask)
359 {
360  UDMACC26XX_HWAttrs const *hwAttrs;
361 
362  /* Get the pointer to the hwAttrs and object */
363  hwAttrs = (UDMACC26XX_HWAttrs *)(handle->hwAttrs);
364 
365  /* Clear UDMA done interrupt */
366  uDMAIntClear(hwAttrs->baseAddr, channelBitMask);
367 }
368 
386 __STATIC_INLINE void UDMACC26XX_channelDisable(UDMACC26XX_Handle handle, uint32_t channelBitMask)
387 {
388  UDMACC26XX_HWAttrs const *hwAttrs;
389 
390  /* Get the pointer to the hwAttrs */
391  hwAttrs = (UDMACC26XX_HWAttrs *)(handle->hwAttrs);
392 
393  HWREG(hwAttrs->baseAddr + UDMA_O_CLEARCHANNELEN) = channelBitMask;
394 }
395 
416 __STATIC_INLINE void UDMACC26XX_disableAttribute(UDMACC26XX_Handle handle,
417  uint32_t channelNum, uint32_t attr)
418 {
419  UDMACC26XX_HWAttrs const *hwAttrs;
420 
421  /* Get the pointer to the hwAttrs */
422  hwAttrs = (UDMACC26XX_HWAttrs *)(handle->hwAttrs);
423 
424  uDMAChannelAttributeDisable(hwAttrs->baseAddr, channelNum, attr);
425 }
426 
442 extern void UDMACC26XX_close(UDMACC26XX_Handle handle);
443 
444 #ifdef __cplusplus
445 }
446 #endif
447 
448 #endif /* ti_drivers_UDMACC26XX__include */
bool isOpen
Definition: UDMACC26XX.h:197
HwiP_Struct hwi
Definition: UDMACC26XX.h:198
void UDMACC26XX_hwiIntFxn(uintptr_t callbacks)
PowerCC26XX_Resource powerMngrId
Definition: UDMACC26XX.h:206
void UDMACC26XX_close(UDMACC26XX_Handle handle)
Function to close the DMA driver.
UDMACC26XX_Handle UDMACC26XX_open(void)
Function to initialize the CC26XX DMA peripheral.
__STATIC_INLINE void UDMACC26XX_clearInterrupt(UDMACC26XX_Handle handle, uint32_t channelBitMask)
Definition: UDMACC26XX.h:358
Power Manager.
__STATIC_INLINE void UDMACC26XX_channelEnable(UDMACC26XX_Handle handle, uint32_t channelBitMask)
Definition: UDMACC26XX.h:301
uint8_t intNum
Definition: UDMACC26XX.h:207
__STATIC_INLINE void UDMACC26XX_init(UDMACC26XX_Handle handle)
Function to initialize the CC26XX DMA driver.
Definition: UDMACC26XX.h:260
__STATIC_INLINE void UDMACC26XX_disableAttribute(UDMACC26XX_Handle handle, uint32_t channelNum, uint32_t attr)
Definition: UDMACC26XX.h:416
UDMACC26XX Global configuration.
Definition: UDMACC26XX.h:235
Power manager interface for CC26XX/CC13XX.
UDMACC26XX hardware attributes.
Definition: UDMACC26XX.h:204
void * object
Definition: UDMACC26XX.h:236
uint8_t intPriority
UDMACC26XX error interrupt priority. intPriority is the DMA peripheral&#39;s interrupt priority...
Definition: UDMACC26XX.h:229
__STATIC_INLINE void UDMACC26XX_channelDisable(UDMACC26XX_Handle handle, uint32_t channelBitMask)
Definition: UDMACC26XX.h:386
__STATIC_INLINE bool UDMACC26XX_channelDone(UDMACC26XX_Handle handle, uint32_t channelBitMask)
Definition: UDMACC26XX.h:330
uint32_t baseAddr
Definition: UDMACC26XX.h:205
UDMACC26XX object.
Definition: UDMACC26XX.h:196
UDMACC26XX_Config * UDMACC26XX_Handle
A handle that is returned from a UDMACC26XX_open() call.
Definition: UDMACC26XX.h:243
void const * hwAttrs
Definition: UDMACC26XX.h:237
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