Instance: AUX_TIMER2
Component: AUX_TIMER2
Base address: 0x400C3000
AUX Timer2 (AUX_TIMER2) offers flexible:
- generation of waveforms and events.
- capture of signal period and duty cycle.
- generation of single clock pulse.
It consists of a:
- 16-bit counter.
- 4 capture compare channels.
- 4 event outputs, which are mapped to AUX event bus, see EVCTL.
Each channel subscribes to the asynchronous AUX event bus. They can control one or more event outputs in both capture and compare modes. AUX_SYSIF:TIMER2CLKCTL.SRC selects clock source for the timer.
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x0000 0000 |
0x400C 3000 |
|
RW |
32 |
0x0000 0000 |
0x0000 0004 |
0x400C 3004 |
|
RW |
32 |
0x0000 0000 |
0x0000 0008 |
0x400C 3008 |
|
RO |
32 |
0x0000 0000 |
0x0000 000C |
0x400C 300C |
|
RW |
32 |
0x0000 0000 |
0x0000 0010 |
0x400C 3010 |
|
WO |
32 |
0x0000 0000 |
0x0000 0014 |
0x400C 3014 |
|
RW |
32 |
0x0000 0000 |
0x0000 0018 |
0x400C 3018 |
|
RW |
32 |
0x0000 0000 |
0x0000 0080 |
0x400C 3080 |
|
RW |
32 |
0x0000 0000 |
0x0000 0084 |
0x400C 3084 |
|
RW |
32 |
0x0000 0000 |
0x0000 0088 |
0x400C 3088 |
|
RW |
32 |
0x0000 0000 |
0x0000 008C |
0x400C 308C |
|
RW |
32 |
0x0000 0000 |
0x0000 0090 |
0x400C 3090 |
|
RW |
32 |
0x0000 0000 |
0x0000 0094 |
0x400C 3094 |
|
RW |
32 |
0x0000 0000 |
0x0000 0098 |
0x400C 3098 |
|
RW |
32 |
0x0000 0000 |
0x0000 009C |
0x400C 309C |
|
RW |
32 |
0x0000 0000 |
0x0000 00A0 |
0x400C 30A0 |
|
RW |
32 |
0x0000 0000 |
0x0000 00A4 |
0x400C 30A4 |
|
RW |
32 |
0x0000 0000 |
0x0000 00A8 |
0x400C 30A8 |
|
RW |
32 |
0x0000 0000 |
0x0000 00AC |
0x400C 30AC |
|
RW |
32 |
0x0000 0000 |
0x0000 00B0 |
0x400C 30B0 |
|
RW |
32 |
0x0000 0000 |
0x0000 00B4 |
0x400C 30B4 |
|
RW |
32 |
0x0000 0000 |
0x0000 00B8 |
0x400C 30B8 |
|
RW |
32 |
0x0000 0000 |
0x0000 00BC |
0x400C 30BC |
Address Offset | 0x0000 0000 | ||
Physical Address | 0x400C 3000 | Instance | 0x400C 3000 |
Description | Timer Control | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||
31:7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | |||||||||||||||||
6 | CH3_RESET | Channel 3 reset. 0: No effect. 1: Reset CH3CC, CH3PCC, CH3EVCFG, and CH3CCFG. Read returns 0. |
RW | 0 | |||||||||||||||||
5 | CH2_RESET | Channel 2 reset. 0: No effect. 1: Reset CH2CC, CH2PCC, CH2EVCFG, and CH2CCFG. Read returns 0. |
RW | 0 | |||||||||||||||||
4 | CH1_RESET | Channel 1 reset. 0: No effect. 1: Reset CH1CC, CH1PCC, CH1EVCFG, and CH1CCFG. Read returns 0. |
RW | 0 | |||||||||||||||||
3 | CH0_RESET | Channel 0 reset. 0: No effect. 1: Reset CH0CC, CH0PCC, CH0EVCFG, and CH0CCFG. Read returns 0. |
RW | 0 | |||||||||||||||||
2 | TARGET_EN | Select counter target value. You must select TARGET to use shadow target functionality.
|
RW | 0 | |||||||||||||||||
1:0 | MODE | Timer mode control. The timer restarts from 0 when you set MODE to UP_ONCE, UP_PER, or UPDWN_PER. When you write MODE all internally queued updates to CHnCC and TARGET clear.
|
RW | 0b00 |
Address Offset | 0x0000 0004 | ||
Physical Address | 0x400C 3004 | Instance | 0x400C 3004 |
Description | Target User defined counter target. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
15:0 | VALUE | 16 bit user defined counter target value, which is used when selected by CTL.TARGET_EN. | RW | 0x0000 |
Address Offset | 0x0000 0008 | ||
Physical Address | 0x400C 3008 | Instance | 0x400C 3008 |
Description | Shadow Target | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
15:0 | VALUE | Target value for next counter period. The timer copies VALUE to TARGET.VALUE when CNTR.VALUE becomes 0. The copy does not happen when you restart the timer. This is useful to avoid period jitter in PWM applications with time-varying period, sometimes referenced as phase corrected PWM. |
RW | 0x0000 |
Address Offset | 0x0000 000C | ||
Physical Address | 0x400C 300C | Instance | 0x400C 300C |
Description | Counter | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
15:0 | VALUE | 16 bit current counter value. | RO | 0x0000 |
Address Offset | 0x0000 0010 | ||
Physical Address | 0x400C 3010 | Instance | 0x400C 3010 |
Description | Clock Prescaler Configuration | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
7:0 | CLKDIV | Clock division. CLKDIV determines the timer clock frequency for counter, synchronization, and timer event updates. The timer clock frequency is the clock selected by AUX_SYSIF:TIMER2CLKCTL.SRC divided by (CLKDIV + 1). This inverse is the timer clock period. 0x00: Divide by 1. 0x01: Divide by 2. ... 0xFF: Divide by 256. |
RW | 0x00 |
Address Offset | 0x0000 0014 | ||
Physical Address | 0x400C 3014 | Instance | 0x400C 3014 |
Description | Event Control Set and clear individual events manually. Manual update of an event takes priority over automatic channel updates to the same event. You cannot set and clear an event at the same time, such requests will be neglected. An event can be automatically cleared, set, toggled, or pulsed by each channel, listed in decreasing order of priority. The action with highest priority happens when multiple channels want to update an event at the same time. The four events connect to the asynchronous AUX event bus: - Event 0 connects to AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. - Event 1 connects to AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. - Event 2 connects to AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. - Event 3 connects to AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. |
||
Type | WO |
Bits | Field Name | Description | Type | Reset | ||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | WO | 0x00 0000 | ||
7 | EV3_SET | Set event 3. Write 1 to set event 3. |
WO | 0 | ||
6 | EV3_CLR | Clear event 3. Write 1 to clear event 3. |
WO | 0 | ||
5 | EV2_SET | Set event 2. Write 1 to set event 2. |
WO | 0 | ||
4 | EV2_CLR | Clear event 2. Write 1 to clear event 2. |
WO | 0 | ||
3 | EV1_SET | Set event 1. Write 1 to set event 1. |
WO | 0 | ||
2 | EV1_CLR | Clear event 1. Write 1 to clear event 1. |
WO | 0 | ||
1 | EV0_SET | Set event 0. Write 1 to set event 0. |
WO | 0 | ||
0 | EV0_CLR | Clear event 0. Write 1 to clear event 0. |
WO | 0 |
Address Offset | 0x0000 0018 | ||
Physical Address | 0x400C 3018 | Instance | 0x400C 3018 |
Description | Pulse Trigger | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
0 | TRIG | Pulse trigger. Write 1 to generate a pulse to AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. Pulse width equals the duty cycle of AUX_SYSIF:TIMER2CLKCTL.SRC. |
WO | 0 |
Address Offset | 0x0000 0080 | ||
Physical Address | 0x400C 3080 | Instance | 0x400C 3080 |
Description | Channel 0 Event Configuration This register configures channel function and enables event outputs. Each channel has an edge-detection circuit with memory. The circuit is: - enabled while CCACT selects a capture function and CTL.MODE is different from DIS. - flushed while CCACT selects a capture function and you change CTL.MODE from DIS to another mode. The flush action uses two AUX_SYSIF:TIMER2CLKCTL.SRC clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||||||||||||||||||||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
7 | EV3_GEN | Event 3 enable. 0: Channel 0 does not control event 3. 1: Channel 0 controls event 3. When 0 < CCACT < 8, EV3_GEN becomes zero after a capture or compare event. |
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
6 | EV2_GEN | Event 2 enable. 0: Channel 0 does not control event 2. 1: Channel 0 controls event 2. When 0 < CCACT < 8, EV2_GEN becomes zero after a capture or compare event. |
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
5 | EV1_GEN | Event 1 enable. 0: Channel 0 does not control event 1. 1: Channel 0 controls event 1. When 0 < CCACT < 8, EV1_GEN becomes zero after a capture or compare event. |
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
4 | EV0_GEN | Event 0 enable. 0: Channel 0 does not control event 0. 1: Channel 0 controls event 0. When 0 < CCACT < 8, EV0_GEN becomes zero after a capture or compare event. |
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
3:0 | CCACT | Capture-Compare action. Capture-Compare action defines 15 different channel functions that utilize capture, compare, and zero events.
|
RW | 0x0 |
Address Offset | 0x0000 0084 | ||
Physical Address | 0x400C 3084 | Instance | 0x400C 3084 |
Description | Channel 0 Capture Configuration | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | |||||||||||
6:1 | CAPT_SRC | Select capture signal source from the asynchronous AUX event bus. The selected signal enters the edge-detection circuit. False capture events can occur when: - the edge-detection circuit contains expired signal samples and the circuit is enabled without flush as described in CH0EVCFG - this register is reconfigured while CTL.MODE is different from DIS. You can avoid false capture events. When wanted channel function is: - SET_ON_CAPT_DIS, see description for SET_ON_CAPT_DIS in CH0EVCFG.CCACT. - SET_ON_CAPT, see description for SET_ON_CAPT in CH0EVCFG.CCACT. - PER_PULSE_WIDTH_MEAS, see description for PER_PULSE_WIDTH_MEAS in CH0EVCFG.CCACT. If you write a non-enumerated value the behavior is identical to NO_EVENT. The written value is returned when read. |
RW | 0b00 0000 | |||||||||||
0 | EDGE | Edge configuration. Channel captures counter value at selected edge on signal source selected by CAPT_SRC. See CH0EVCFG.CCACT.
|
RW | 0 |
Address Offset | 0x0000 0088 | ||
Physical Address | 0x400C 3088 | Instance | 0x400C 3088 |
Description | Channel 0 Pipeline Capture Compare | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
15:0 | VALUE | Pipeline Capture Compare value. 16-bit user defined pipeline compare value or channel-updated capture value. Compare mode: An update of VALUE will be transferred to CH0CC.VALUE when the next CNTR.VALUE is zero and CTL.MODE is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal. Capture mode: When CH0EVCFG.CCACT equals PER_PULSE_WIDTH_MEAS then VALUE contains the width of the low or high phase of the selected signal. This is specified by CH0CCFG.EDGE and CH0CCFG.CAPT_SRC. |
RW | 0x0000 |
Address Offset | 0x0000 008C | ||
Physical Address | 0x400C 308C | Instance | 0x400C 308C |
Description | Channel 0 Capture Compare | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
15:0 | VALUE | Capture Compare value. 16-bit user defined compare value or channel-updated capture value. Compare mode: VALUE is compared against CNTR.VALUE and an event is generated as specified by CH0EVCFG.CCACT when these are equal. Capture mode: The current counter value is stored in VALUE when a capture event occurs. CH0EVCFG.CCACT determines if VALUE is a signal period or a regular capture value. |
RW | 0x0000 |
Address Offset | 0x0000 0090 | ||
Physical Address | 0x400C 3090 | Instance | 0x400C 3090 |
Description | Channel 1 Event Configuration This register configures channel function and enables event outputs. Each channel has an edge-detection circuit with memory. The circuit is: - enabled while CCACT selects a capture function and CTL.MODE is different from DIS. - flushed while CCACT selects a capture function and you change CTL.MODE from DIS to another mode. The flush action uses two AUX_SYSIF:TIMER2CLKCTL.SRC clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||||||||||||||||||||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
7 | EV3_GEN | Event 3 enable. 0: Channel 1 does not control event 3. 1: Channel 1 controls event 3. When 0 < CCACT < 8, EV3_GEN becomes zero after a capture or compare event. |
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
6 | EV2_GEN | Event 2 enable. 0: Channel 1 does not control event 2. 1: Channel 1 controls event 2. When 0 < CCACT < 8, EV2_GEN becomes zero after a capture or compare event. |
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
5 | EV1_GEN | Event 1 enable. 0: Channel 1 does not control event 1. 1: Channel 1 controls event 1. When 0 < CCACT < 8, EV1_GEN becomes zero after a capture or compare event. |
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
4 | EV0_GEN | Event 0 enable. 0: Channel 1 does not control event 0. 1: Channel 1 controls event 0. When 0 < CCACT < 8, EV0_GEN becomes zero after a capture or compare event. |
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
3:0 | CCACT | Capture-Compare action. Capture-Compare action defines 15 different channel functions that utilize capture, compare, and zero events.
|
RW | 0x0 |
Address Offset | 0x0000 0094 | ||
Physical Address | 0x400C 3094 | Instance | 0x400C 3094 |
Description | Channel 1 Capture Configuration | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | |||||||||||
6:1 | CAPT_SRC | Select capture signal source from the asynchronous AUX event bus. The selected signal enters the edge-detection circuit. False capture events can occur when: - the edge-detection circuit contains expired signal samples and the circuit is enabled without flush as described in CH1EVCFG - this register is reconfigured while CTL.MODE is different from DIS. You can avoid false capture events. When wanted channel function is: - SET_ON_CAPT_DIS, see description for SET_ON_CAPT_DIS in CH1EVCFG.CCACT. - SET_ON_CAPT, see description for SET_ON_CAPT in CH1EVCFG.CCACT. - PER_PULSE_WIDTH_MEAS, see description for PER_PULSE_WIDTH_MEAS in CH1EVCFG.CCACT. If you write a non-enumerated value the behavior is identical to NO_EVENT. The written value is returned when read. |
RW | 0b00 0000 | |||||||||||
0 | EDGE | Edge configuration. Channel captures counter value at selected edge on signal source selected by CAPT_SRC. See CH1EVCFG.CCACT.
|
RW | 0 |
Address Offset | 0x0000 0098 | ||
Physical Address | 0x400C 3098 | Instance | 0x400C 3098 |
Description | Channel 1 Pipeline Capture Compare | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
15:0 | VALUE | Pipeline Capture Compare value. 16-bit user defined pipeline compare value or channel-updated capture value. Compare mode: An update of VALUE will be transferred to CH1CC.VALUE when the next CNTR.VALUE is zero and CTL.MODE is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal. Capture mode: When CH1EVCFG.CCACT equals PER_PULSE_WIDTH_MEAS then VALUE contains the width of the low or high phase of the selected signal. This is specified by CH1CCFG.EDGE and CH1CCFG.CAPT_SRC. |
RW | 0x0000 |
Address Offset | 0x0000 009C | ||
Physical Address | 0x400C 309C | Instance | 0x400C 309C |
Description | Channel 1 Capture Compare | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
15:0 | VALUE | Capture Compare value. 16-bit user defined compare value or channel-updated capture value. Compare mode: VALUE is compared against CNTR.VALUE and an event is generated as specified by CH1EVCFG.CCACT when these are equal. Capture mode: The current counter value is stored in VALUE when a capture event occurs. CH1EVCFG.CCACT determines if VALUE is a signal period or a regular capture value. |
RW | 0x0000 |
Address Offset | 0x0000 00A0 | ||
Physical Address | 0x400C 30A0 | Instance | 0x400C 30A0 |
Description | Channel 2 Event Configuration This register configures channel function and enables event outputs. Each channel has an edge-detection circuit with memory. The circuit is: - enabled while CCACT selects a capture function and CTL.MODE is different from DIS. - flushed while CCACT selects a capture function and you change CTL.MODE from DIS to another mode. The flush action uses two AUX_SYSIF:TIMER2CLKCTL.SRC clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||||||||||||||||||||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
7 | EV3_GEN | Event 3 enable. 0: Channel 2 does not control event 3. 1: Channel 2 controls event 3. When 0 < CCACT < 8, EV3_GEN becomes zero after a capture or compare event. |
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
6 | EV2_GEN | Event 2 enable. 0: Channel 2 does not control event 2. 1: Channel 2 controls event 2. When 0 < CCACT < 8, EV2_GEN becomes zero after a capture or compare event. |
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
5 | EV1_GEN | Event 1 enable. 0: Channel 2 does not control event 1. 1: Channel 2 controls event 1. When 0 < CCACT < 8, EV1_GEN becomes zero after a capture or compare event. |
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
4 | EV0_GEN | Event 0 enable. 0: Channel 2 does not control event 0. 1: Channel 2 controls event 0. When 0 < CCACT < 8, EV0_GEN becomes zero after a capture or compare event. |
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
3:0 | CCACT | Capture-Compare action. Capture-Compare action defines 15 different channel functions that utilize capture, compare, and zero events.
|
RW | 0x0 |
Address Offset | 0x0000 00A4 | ||
Physical Address | 0x400C 30A4 | Instance | 0x400C 30A4 |
Description | Channel 2 Capture Configuration | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | |||||||||||
6:1 | CAPT_SRC | Select capture signal source from the asynchronous AUX event bus. The selected signal enters the edge-detection circuit. False capture events can occur when: - the edge-detection circuit contains expired signal samples and the circuit is enabled without flush as described in CH2EVCFG - this register is reconfigured while CTL.MODE is different from DIS. You can avoid false capture events. When wanted channel function is: - SET_ON_CAPT_DIS, see description for SET_ON_CAPT_DIS in CH2EVCFG.CCACT. - SET_ON_CAPT, see description for SET_ON_CAPT in CH2EVCFG.CCACT. - PER_PULSE_WIDTH_MEAS, see description for PER_PULSE_WIDTH_MEAS in CH2EVCFG.CCACT. If you write a non-enumerated value the behavior is identical to NO_EVENT. The written value is returned when read. |
RW | 0b00 0000 | |||||||||||
0 | EDGE | Edge configuration. Channel captures counter value at selected edge on signal source selected by CAPT_SRC. See CH2EVCFG.CCACT.
|
RW | 0 |
Address Offset | 0x0000 00A8 | ||
Physical Address | 0x400C 30A8 | Instance | 0x400C 30A8 |
Description | Channel 2 Pipeline Capture Compare | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
15:0 | VALUE | Pipeline Capture Compare value. 16-bit user defined pipeline compare value or channel-updated capture value. Compare mode: An update of VALUE will be transferred to CH2CC.VALUE when the next CNTR.VALUE is zero and CTL.MODE is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal. Capture mode: When CH2EVCFG.CCACT equals PER_PULSE_WIDTH_MEAS then VALUE contains the width of the low or high phase of the selected signal. This is specified by CH2CCFG.EDGE and CH2CCFG.CAPT_SRC. |
RW | 0x0000 |
Address Offset | 0x0000 00AC | ||
Physical Address | 0x400C 30AC | Instance | 0x400C 30AC |
Description | Channel 2 Capture Compare | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
15:0 | VALUE | Capture Compare value. 16-bit user defined compare value or channel-updated capture value. Compare mode: VALUE is compared against CNTR.VALUE and an event is generated as specified by CH2EVCFG.CCACT when these are equal. Capture mode: The current counter value is stored in VALUE when a capture event occurs. CH2EVCFG.CCACT determines if VALUE is a signal period or a regular capture value. |
RW | 0x0000 |
Address Offset | 0x0000 00B0 | ||
Physical Address | 0x400C 30B0 | Instance | 0x400C 30B0 |
Description | Channel 3 Event Configuration This register configures channel function and enables event outputs. Each channel has an edge-detection circuit with memory. The circuit is: - enabled while CCACT selects a capture function and CTL.MODE is different from DIS. - flushed while CCACT selects a capture function and you change CTL.MODE from DIS to another mode. The flush action uses two AUX_SYSIF:TIMER2CLKCTL.SRC clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||||||||||||||||||||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
7 | EV3_GEN | Event 3 enable. 0: Channel 3 does not control event 3. 1: Channel 3 controls event 3. When 0 < CCACT < 8, EV3_GEN becomes zero after a capture or compare event. |
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
6 | EV2_GEN | Event 2 enable. 0: Channel 3 does not control event 2. 1: Channel 3 controls event 2. When 0 < CCACT < 8, EV2_GEN becomes zero after a capture or compare event. |
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
5 | EV1_GEN | Event 1 enable. 0: Channel 3 does not control event 1. 1: Channel 3 controls event 1. When 0 < CCACT < 8, EV1_GEN becomes zero after a capture or compare event. |
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
4 | EV0_GEN | Event 0 enable. 0: Channel 3 does not control event 0. 1: Channel 3 controls event 0. When 0 < CCACT < 8, EV0_GEN becomes zero after a capture or compare event. |
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
3:0 | CCACT | Capture-Compare action. Capture-Compare action defines 15 different channel functions that utilize capture, compare, and zero events.
|
RW | 0x0 |
Address Offset | 0x0000 00B4 | ||
Physical Address | 0x400C 30B4 | Instance | 0x400C 30B4 |
Description | Channel 3 Capture Configuration | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | |||||||||||
6:1 | CAPT_SRC | Select capture signal source from the asynchronous AUX event bus. The selected signal enters the edge-detection circuit. False capture events can occur when: - the edge-detection circuit contains expired signal samples and the circuit is enabled without flush as described in CH3EVCFG - this register is reconfigured while CTL.MODE is different from DIS. You can avoid false capture events. When wanted channel function: - SET_ON_CAPT_DIS, see description for SET_ON_CAPT_DIS in CH3EVCFG.CCACT. - SET_ON_CAPT, see description for SET_ON_CAPT in CH3EVCFG.CCACT. - PER_PULSE_WIDTH_MEAS, see description for PER_PULSE_WIDTH_MEAS in CH3EVCFG.CCACT. If you write a non-enumerated value the behavior is identical to NO_EVENT. The written value is returned when read. |
RW | 0b00 0000 | |||||||||||
0 | EDGE | Edge configuration. Channel captures counter value at selected edge on signal source selected by CAPT_SRC. See CH3EVCFG.CCACT.
|
RW | 0 |
Address Offset | 0x0000 00B8 | ||
Physical Address | 0x400C 30B8 | Instance | 0x400C 30B8 |
Description | Channel 3 Pipeline Capture Compare | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
15:0 | VALUE | Pipeline Capture Compare value. 16-bit user defined pipeline compare value or channel-updated capture value. Compare mode: An update of VALUE will be transferred to CH3CC.VALUE when the next CNTR.VALUE is zero and CTL.MODE is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal. Capture mode: When CH3EVCFG.CCACT equals PER_PULSE_WIDTH_MEAS then VALUE contains the width of the low or high phase of the selected signal. This is specified by CH3CCFG.EDGE and CH3CCFG.CAPT_SRC. |
RW | 0x0000 |
Address Offset | 0x0000 00BC | ||
Physical Address | 0x400C 30BC | Instance | 0x400C 30BC |
Description | Channel 3 Capture Compare | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
15:0 | VALUE | Capture Compare value. 16-bit user defined compare value or channel-updated capture value. Compare mode: VALUE is compared against CNTR.VALUE and an event is generated as specified by CH3EVCFG.CCACT when these are equal. Capture mode: The current counter value is stored in VALUE when a capture event occurs. CH3EVCFG.CCACT determines if VALUE is a signal period or a regular capture value. |
RW | 0x0000 |
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