IAR Cortex-M4 Timing Benchmarks
Target Platform: ti.platforms.tiva:TM4C123GH6PM:1
Tool Chain Version: 8.32.2.178
BIOS Version: bios_6_77_00_10_eng
XDCTools Version: xdctools_3_60_00_19_core_eng
Benchmark | Cycles |
---|---|
Interrupt Latency | 116 |
Hwi_restore() | 7 |
Hwi_disable() | 9 |
Hwi dispatcher prolog | 95 |
Hwi dispatcher epilog | 196 |
Hwi dispatcher | 281 |
Hardware Interrupt to Blocked Task | 453 |
Hardware Interrupt to Software Interrupt | 307 |
Swi_enable() | 58 |
Swi_disable() | 12 |
Post Software Interrupt Again | 20 |
Post Software Interrupt without Context Switch | 81 |
Post Software Interrupt with Context Switch | 162 |
Create a New Task without Context Switch | 1941 |
Set a Task Priority without a Context Switch | 145 |
Task_yield() | 184 |
Post Semaphore No Waiting Task | 65 |
Post Semaphore No Task Switch | 160 |
Post Semaphore with Task Switch | 215 |
Pend on Semaphore No Context Switch | 52 |
Pend on Semaphore with Task Switch | 243 |
Clock_getTicks() | 9 |
POSIX Create a New Task without Context Switch | 3457 |
POSIX Set a Task Priority without a Context Switch | 187 |
POSIX Post Semaphore No Waiting Task | 78 |
POSIX Post Semaphore No Task Switch | 172 |
POSIX Post Semaphore with Task Switch | 221 |
POSIX Pend on Semaphore No Context Switch | 42 |
POSIX Pend on Semaphore with Task Switch | 246 |
The M4 target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi CDOCs for details.
See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.