IAR Cortex-M4 Timing Benchmarks
Target Platform: ti.platforms.simplelink:CC3200:1
Tool Chain Version: 8.32.2.178
BIOS Version: bios_6_80_00_08_eng
XDCTools Version: xdctools_3_60_00_24_core
Benchmark | Cycles |
---|---|
Interrupt Latency | 151 |
Hwi_restore() | 13 |
Hwi_disable() | 15 |
Hwi dispatcher prolog | 123 |
Hwi dispatcher epilog | 253 |
Hwi dispatcher | 364 |
Hardware Interrupt to Blocked Task | 591 |
Hardware Interrupt to Software Interrupt | 397 |
Swi_enable() | 77 |
Swi_disable() | 17 |
Post Software Interrupt Again | 23 |
Post Software Interrupt without Context Switch | 110 |
Post Software Interrupt with Context Switch | 211 |
Create a New Task without Context Switch | 2566 |
Set a Task Priority without a Context Switch | 192 |
Task_yield() | 239 |
Post Semaphore No Waiting Task | 83 |
Post Semaphore No Task Switch | 207 |
Post Semaphore with Task Switch | 281 |
Pend on Semaphore No Context Switch | 78 |
Pend on Semaphore with Task Switch | 320 |
Clock_getTicks() | 14 |
POSIX Create a New Task without Context Switch | 4649 |
POSIX Set a Task Priority without a Context Switch | 249 |
POSIX Post Semaphore No Waiting Task | 102 |
POSIX Post Semaphore No Task Switch | 223 |
POSIX Post Semaphore with Task Switch | 292 |
POSIX Pend on Semaphore No Context Switch | 62 |
POSIX Pend on Semaphore with Task Switch | 321 |
The M4 target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi CDOCs for details.
See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.