Instance: CCFG
Component: CCFG
Base address: 0x50003000
Customer configuration area (CCFG)
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RO |
32 |
0xFFFF FFFF |
0x0000 0FA8 |
0x5000 3FA8 |
|
RO |
32 |
0xFFFB FFFF |
0x0000 0FAC |
0x5000 3FAC |
|
RO |
32 |
0xFFFF FFFF |
0x0000 0FB0 |
0x5000 3FB0 |
|
RO |
32 |
0xFFFF FFFF |
0x0000 0FB4 |
0x5000 3FB4 |
|
RO |
32 |
0xFFFF FFFF |
0x0000 0FB8 |
0x5000 3FB8 |
|
RO |
32 |
0xFFFF FFFF |
0x0000 0FBC |
0x5000 3FBC |
|
RO |
32 |
0xFFFF FFFF |
0x0000 0FC0 |
0x5000 3FC0 |
|
RO |
32 |
0xFFFF FFFF |
0x0000 0FC4 |
0x5000 3FC4 |
|
RO |
32 |
0xFFFF FFFF |
0x0000 0FC8 |
0x5000 3FC8 |
|
RO |
32 |
0xFFFF FFFF |
0x0000 0FCC |
0x5000 3FCC |
|
RO |
32 |
0xFFFF FFFF |
0x0000 0FD0 |
0x5000 3FD0 |
|
RO |
32 |
0xFFFF FFFF |
0x0000 0FD4 |
0x5000 3FD4 |
|
RO |
32 |
0xC5FF FFFF |
0x0000 0FD8 |
0x5000 3FD8 |
|
RO |
32 |
0xFFFF FFFF |
0x0000 0FDC |
0x5000 3FDC |
|
RO |
32 |
0xFFFF FFC5 |
0x0000 0FE0 |
0x5000 3FE0 |
|
RO |
32 |
0xFFC5 C5C5 |
0x0000 0FE4 |
0x5000 3FE4 |
|
RO |
32 |
0xFFC5 C5C5 |
0x0000 0FE8 |
0x5000 3FE8 |
|
RO |
32 |
0xFFFF FFFF |
0x0000 0FEC |
0x5000 3FEC |
|
RO |
32 |
0xFFFF FFFF |
0x0000 0FF0 |
0x5000 3FF0 |
|
RO |
32 |
0xFFFF FFFF |
0x0000 0FF4 |
0x5000 3FF4 |
|
RO |
32 |
0xFFFF FFFF |
0x0000 0FF8 |
0x5000 3FF8 |
|
RO |
32 |
0xFFFF FFFF |
0x0000 0FFC |
0x5000 3FFC |
Address Offset | 0x0000 0FA8 | ||
Physical Address | 0x5000 3FA8 | Instance | 0x5000 3FA8 |
Description | Extern LF clock configuration | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:24 | DIO | Unsigned integer, selecting the DIO to supply external 32kHz clock as SCLK_LF when MODE_CONF.SCLK_LF_OPTION is set to EXTERNAL. The selected DIO will be marked as reserved by the pin driver (TI-RTOS environment) and hence not selectable for other usage. | RO | 0xFF | ||
23:0 | RTC_INCREMENT | Unsigned integer, defining the input frequency of the external clock and is written to AON_RTC:SUBSECINC.VALUEINC. Defined as follows: EXT_LF_CLK.RTC_INCREMENT = 2^38/InputClockFrequency in Hertz (e.g.: RTC_INCREMENT=0x800000 for InputClockFrequency=32768 Hz) | RO | 0xFF FFFF |
Address Offset | 0x0000 0FAC | ||
Physical Address | 0x5000 3FAC | Instance | 0x5000 3FAC |
Description | Mode Configuration 1 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:24 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0xFF | ||
23:20 | ALT_DCDC_VMIN | Minimum voltage for when DC/DC should be used if alternate DC/DC setting is enabled (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0). Voltage = (28 + ALT_DCDC_VMIN) / 16. 0: 1.75V 1: 1.8125V ... 14: 2.625V 15: 2.6875V NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must be called regularly to apply this field (handled automatically if using TI RTOS!). |
RO | 0xF | ||
19 | ALT_DCDC_DITHER_EN | Enable DC/DC dithering if alternate DC/DC setting is enabled (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0). 0: Dither disable 1: Dither enable |
RO | 1 | ||
18:16 | ALT_DCDC_IPEAK | Inductor peak current if alternate DC/DC setting is enabled (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0). Assuming 10uH external inductor! Peak current = 31 + ( 4 * ALT_DCDC_IPEAK ) : 0: 31mA (min) ... 4: 47mA ... 7: 59mA (max) |
RO | 0b011 | ||
15:12 | DELTA_IBIAS_INIT | Signed delta value for IBIAS_INIT. Delta value only applies if SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. See FCFG1:AMPCOMP_CTRL1.IBIAS_INIT |
RO | 0xF | ||
11:8 | DELTA_IBIAS_OFFSET | Signed delta value for IBIAS_OFFSET. Delta value only applies if SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. See FCFG1:AMPCOMP_CTRL1.IBIAS_OFFSET |
RO | 0xF | ||
7:0 | XOSC_MAX_START | Unsigned value of maximum XOSC startup time (worst case) in units of 100us. Value only applies if SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. | RO | 0xFF |
Address Offset | 0x0000 0FB0 | ||
Physical Address | 0x5000 3FB0 | Instance | 0x5000 3FB0 |
Description | CCFG Size and Disable Flags | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:16 | SIZE_OF_CCFG | Total size of CCFG in bytes. | RO | 0xFFFF | ||
15:4 | DISABLE_FLAGS | Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. | RO | 0xFFF | ||
3 | DIS_TCXO | Disable TCXO. 0: TCXO functionality enabled. 1: TCXO functionality disabled. Note: An external TCXO is required if DIS_TCXO = 0. |
RO | 1 | ||
2 | DIS_GPRAM | Disable GPRAM (or use the 8K VIMS RAM as CACHE RAM). 0: GPRAM is enabled and hence CACHE disabled. 1: GPRAM is disabled and instead CACHE is enabled (default). Notes: - Disabling CACHE will reduce CPU execution speed (up to 60%). - GPRAM is 8 K-bytes in size and located at 0x11000000-0x11001FFF if enabled. See: VIMS:CTL.MODE |
RO | 1 | ||
1 | DIS_ALT_DCDC_SETTING | Disable alternate DC/DC settings. 0: Enable alternate DC/DC settings. 1: Disable alternate DC/DC settings. See: MODE_CONF_1.ALT_DCDC_VMIN MODE_CONF_1.ALT_DCDC_DITHER_EN MODE_CONF_1.ALT_DCDC_IPEAK NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must be called regularly to apply this field (handled automatically if using TI RTOS!). |
RO | 1 | ||
0 | DIS_XOSC_OVR | Disable XOSC override functionality. 0: Enable XOSC override functionality. 1: Disable XOSC override functionality. See: MODE_CONF_1.DELTA_IBIAS_INIT MODE_CONF_1.DELTA_IBIAS_OFFSET MODE_CONF_1.XOSC_MAX_START |
RO | 1 |
Address Offset | 0x0000 0FB4 | ||
Physical Address | 0x5000 3FB4 | Instance | 0x5000 3FB4 |
Description | Mode Configuration 0 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||
31:28 | VDDR_TRIM_SLEEP_DELTA | Signed delta value to apply to the VDDR_TRIM_SLEEP target, minus one. See FCFG1:VOLT_TRIM.VDDR_TRIM_SLEEP_H. 0x8 (-8) : Delta = -7 ... 0xF (-1) : Delta = 0 0x0 (0) : Delta = +1 ... 0x7 (7) : Delta = +8 |
RO | 0xF | |||||||||||||||||
27 | DCDC_RECHARGE | DC/DC during recharge in powerdown. 0: Use the DC/DC during recharge in powerdown. 1: Do not use the DC/DC during recharge in powerdown (default). NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must be called regularly to apply this field (handled automatically if using TI RTOS!). |
RO | 1 | |||||||||||||||||
26 | DCDC_ACTIVE | DC/DC in active mode. 0: Use the DC/DC during active mode. 1: Do not use the DC/DC during active mode (default). NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must be called regularly to apply this field (handled automatically if using TI RTOS!). |
RO | 1 | |||||||||||||||||
25 | VDDR_EXT_LOAD | Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. | RO | 1 | |||||||||||||||||
24 | VDDS_BOD_LEVEL | VDDS BOD level. 0: VDDS BOD level is 2.0 V (necessary for maximum PA output power on CC13x0). 1: VDDS BOD level is 1.8 V (or 1.7 V for external regulator mode) (default). |
RO | 1 | |||||||||||||||||
23:22 | SCLK_LF_OPTION | Select source for SCLK_LF.
|
RO | 0b11 | |||||||||||||||||
21 | VDDR_TRIM_SLEEP_TC | 0x1: VDDR_TRIM_SLEEP_DELTA is not temperature compensated 0x0: RTOS/driver temperature compensates VDDR_TRIM_SLEEP_DELTA every time standby mode is entered. This improves low-temperature RCOSC_LF frequency stability in standby mode. When temperature compensation is performed, the delta is calculates this way: Delta = max (delta, min(8, floor(62-temp)/8)) Here, delta is given by VDDR_TRIM_SLEEP_DELTA, and temp is the current temperature in degrees C. |
RO | 1 | |||||||||||||||||
20 | RTC_COMP | Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. | RO | 1 | |||||||||||||||||
19:18 | XOSC_FREQ | Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior.
|
RO | 0b11 | |||||||||||||||||
17 | XOSC_CAP_MOD | Enable modification (delta) to XOSC cap-array. Value specified in XOSC_CAPARRAY_DELTA. 0: Apply cap-array delta 1: Do not apply cap-array delta (default) |
RO | 1 | |||||||||||||||||
16 | HF_COMP | Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. | RO | 1 | |||||||||||||||||
15:8 | XOSC_CAPARRAY_DELTA | Signed 8-bit value, directly modifying trimmed XOSC cap-array step value. Enabled by XOSC_CAP_MOD. | RO | 0xFF | |||||||||||||||||
7:0 | VDDR_CAP | Unsigned 8-bit integer, representing the minimum decoupling capacitance (worst case) on VDDR, in units of 100nF. This should take into account capacitor tolerance and voltage dependent capacitance variation. This bit affects the recharge period calculation when going into powerdown or standby. NOTE! If using the following functions this field must be configured (used by TI RTOS): SysCtrlSetRechargeBeforePowerDown() SysCtrlAdjustRechargeAfterPowerDown() |
RO | 0xFF |
Address Offset | 0x0000 0FB8 | ||
Physical Address | 0x5000 3FB8 | Instance | 0x5000 3FB8 |
Description | Voltage Load 0 Enabled by MODE_CONF.VDDR_EXT_LOAD. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:24 | VDDR_EXT_TP45 | Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. | RO | 0xFF | ||
23:16 | VDDR_EXT_TP25 | Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. | RO | 0xFF | ||
15:8 | VDDR_EXT_TP5 | Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. | RO | 0xFF | ||
7:0 | VDDR_EXT_TM15 | Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. | RO | 0xFF |
Address Offset | 0x0000 0FBC | ||
Physical Address | 0x5000 3FBC | Instance | 0x5000 3FBC |
Description | Voltage Load 1 Enabled by MODE_CONF.VDDR_EXT_LOAD. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:24 | VDDR_EXT_TP125 | Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. | RO | 0xFF | ||
23:16 | VDDR_EXT_TP105 | Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. | RO | 0xFF | ||
15:8 | VDDR_EXT_TP85 | Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. | RO | 0xFF | ||
7:0 | VDDR_EXT_TP65 | Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. | RO | 0xFF |
Address Offset | 0x0000 0FC0 | ||
Physical Address | 0x5000 3FC0 | Instance | 0x5000 3FC0 |
Description | Real Time Clock Offset Enabled by MODE_CONF.RTC_COMP. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RTC_COMP_P0 | Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. | RO | 0xFFFF | ||
15:8 | RTC_COMP_P1 | Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. | RO | 0xFF | ||
7:0 | RTC_COMP_P2 | Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. | RO | 0xFF |
Address Offset | 0x0000 0FC4 | ||
Physical Address | 0x5000 3FC4 | Instance | 0x5000 3FC4 |
Description | Frequency Offset | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:16 | HF_COMP_P0 | Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. | RO | 0xFFFF | ||
15:8 | HF_COMP_P1 | Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. | RO | 0xFF | ||
7:0 | HF_COMP_P2 | Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. | RO | 0xFF |
Address Offset | 0x0000 0FC8 | ||
Physical Address | 0x5000 3FC8 | Instance | 0x5000 3FC8 |
Description | IEEE MAC Address 0 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | ADDR | Bits[31:0] of the 64-bits custom IEEE MAC address. If different from 0xFFFFFFFF then the value of this field is applied; otherwise use value from FCFG. |
RO | 0xFFFF FFFF |
Address Offset | 0x0000 0FCC | ||
Physical Address | 0x5000 3FCC | Instance | 0x5000 3FCC |
Description | IEEE MAC Address 1 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | ADDR | Bits[63:32] of the 64-bits custom IEEE MAC address. If different from 0xFFFFFFFF then the value of this field is applied; otherwise use value from FCFG. |
RO | 0xFFFF FFFF |
Address Offset | 0x0000 0FD0 | ||
Physical Address | 0x5000 3FD0 | Instance | 0x5000 3FD0 |
Description | IEEE BLE Address 0 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | ADDR | Bits[31:0] of the 64-bits custom IEEE BLE address. If different from 0xFFFFFFFF then the value of this field is applied; otherwise use value from FCFG. |
RO | 0xFFFF FFFF |
Address Offset | 0x0000 0FD4 | ||
Physical Address | 0x5000 3FD4 | Instance | 0x5000 3FD4 |
Description | IEEE BLE Address 1 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | ADDR | Bits[63:32] of the 64-bits custom IEEE BLE address. If different from 0xFFFFFFFF then the value of this field is applied; otherwise use value from FCFG. |
RO | 0xFFFF FFFF |
Address Offset | 0x0000 0FD8 | ||
Physical Address | 0x5000 3FD8 | Instance | 0x5000 3FD8 |
Description | Bootloader Configuration Configures the functionality of the ROM boot loader. If both the boot loader is enabled by the BOOTLOADER_ENABLE field and the boot loader backdoor is enabled by the BL_ENABLE field it is possible to force entry of the ROM boot loader even if a valid image is present in flash. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:24 | BOOTLOADER_ENABLE | Bootloader enable. Boot loader can be accessed if IMAGE_VALID_CONF.IMAGE_VALID is non-zero or BL_ENABLE is enabled (and conditions for boot loader backdoor are met). 0xC5: Boot loader is enabled. Any other value: Boot loader is disabled. |
RO | 0xC5 | ||
23:17 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b111 1111 | ||
16 | BL_LEVEL | Sets the active level of the selected DIO number BL_PIN_NUMBER if boot loader backdoor is enabled by the BL_ENABLE field. 0: Active low. 1: Active high. |
RO | 1 | ||
15:8 | BL_PIN_NUMBER | DIO number that is level checked if the boot loader backdoor is enabled by the BL_ENABLE field. | RO | 0xFF | ||
7:0 | BL_ENABLE | Enables the boot loader backdoor. 0xC5: Boot loader backdoor is enabled. Any other value: Boot loader backdoor is disabled. NOTE! Boot loader must be enabled (see BOOTLOADER_ENABLE) if boot loader backdoor is enabled. |
RO | 0xFF |
Address Offset | 0x0000 0FDC | ||
Physical Address | 0x5000 3FDC | Instance | 0x5000 3FDC |
Description | Erase Configuration | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:9 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b111 1111 1111 1111 1111 1111 | ||
8 | CHIP_ERASE_DIS_N | Chip erase. This bit controls if a chip erase requested through the JTAG WUC TAP will be ignored in a following boot caused by a reset of the MCU VD. A successful chip erase operation will force the content of the flash main bank back to the state as it was when delivered by TI. 0: Disable. Any chip erase request detected during boot will be ignored. 1: Enable. Any chip erase request detected during boot will be performed by the boot FW. |
RO | 1 | ||
7:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b111 1111 | ||
0 | BANK_ERASE_DIS_N | Bank erase. This bit controls if the ROM serial boot loader will accept a received Bank Erase command (COMMAND_BANK_ERASE). A successful Bank Erase operation will erase all main bank sectors not protected by write protect configuration bits in CCFG. 0: Disable the boot loader bank erase function. 1: Enable the boot loader bank erase function. |
RO | 1 |
Address Offset | 0x0000 0FE0 | ||
Physical Address | 0x5000 3FE0 | Instance | 0x5000 3FE0 |
Description | TI Options | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:8 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0xFF FFFF | ||
7:0 | TI_FA_ENABLE | TI Failure Analysis. 0xC5: Enable the functionality of unlocking the TI FA (TI Failure Analysis) option with the unlock code. All other values: Disable the functionality of unlocking the TI FA option with the unlock code. |
RO | 0xC5 |
Address Offset | 0x0000 0FE4 | ||
Physical Address | 0x5000 3FE4 | Instance | 0x5000 3FE4 |
Description | Test Access Points Enable 0 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:24 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0xFF | ||
23:16 | CPU_DAP_ENABLE | Enable CPU DAP. 0xC5: Main CPU DAP access is enabled during power-up/system-reset by ROM boot FW. Any other value: Main CPU DAP access will remain disabled out of power-up/system-reset. |
RO | 0xC5 | ||
15:8 | PRCM_TAP_ENABLE | Enable PRCM TAP. 0xC5: PRCM TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI. Any other value: PRCM TAP access will remain disabled out of power-up/system-reset. |
RO | 0xC5 | ||
7:0 | TEST_TAP_ENABLE | Enable Test TAP. 0xC5: TEST TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI. Any other value: TEST TAP access will remain disabled out of power-up/system-reset. |
RO | 0xC5 |
Address Offset | 0x0000 0FE8 | ||
Physical Address | 0x5000 3FE8 | Instance | 0x5000 3FE8 |
Description | Test Access Points Enable 1 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:24 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0xFF | ||
23:16 | PBIST2_TAP_ENABLE | Enable PBIST2 TAP. 0xC5: PBIST2 TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI. Any other value: PBIST2 TAP access will remain disabled out of power-up/system-reset. |
RO | 0xC5 | ||
15:8 | PBIST1_TAP_ENABLE | Enable PBIST1 TAP. 0xC5: PBIST1 TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI. Any other value: PBIST1 TAP access will remain disabled out of power-up/system-reset. |
RO | 0xC5 | ||
7:0 | WUC_TAP_ENABLE | Enable WUC TAP 0xC5: WUC TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI. Any other value: WUC TAP access will remain disabled out of power-up/system-reset. |
RO | 0xC5 |
Address Offset | 0x0000 0FEC | ||
Physical Address | 0x5000 3FEC | Instance | 0x5000 3FEC |
Description | Image Valid | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | IMAGE_VALID | This field must have a value of 0x00000000 in order for enabling the boot sequence to transfer control to a flash image. A non-zero value forces the boot sequence to call the boot loader. For CC2640R2: This field must have the address value of the start of the flash vector table in order for enabling the boot sequence to transfer control to a flash image. Any illegal vector table start address value forces the boot sequence to call the boot loader. Note that if any other legal vector table start address value than 0x0 is selected the PRCM:WARMRESET.WR_TO_PINRESET must be set to 1. |
RO | 0xFFFF FFFF |
Address Offset | 0x0000 0FF0 | ||
Physical Address | 0x5000 3FF0 | Instance | 0x5000 3FF0 |
Description | Protect Sectors 0-31 Each bit write protects one 4KB flash sector from being both programmed and erased. Bit must be set to 0 in order to enable sector write protect. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31 | WRT_PROT_SEC_31 | 0: Sector protected | RO | 1 | ||
30 | WRT_PROT_SEC_30 | 0: Sector protected | RO | 1 | ||
29 | WRT_PROT_SEC_29 | 0: Sector protected | RO | 1 | ||
28 | WRT_PROT_SEC_28 | 0: Sector protected | RO | 1 | ||
27 | WRT_PROT_SEC_27 | 0: Sector protected | RO | 1 | ||
26 | WRT_PROT_SEC_26 | 0: Sector protected | RO | 1 | ||
25 | WRT_PROT_SEC_25 | 0: Sector protected | RO | 1 | ||
24 | WRT_PROT_SEC_24 | 0: Sector protected | RO | 1 | ||
23 | WRT_PROT_SEC_23 | 0: Sector protected | RO | 1 | ||
22 | WRT_PROT_SEC_22 | 0: Sector protected | RO | 1 | ||
21 | WRT_PROT_SEC_21 | 0: Sector protected | RO | 1 | ||
20 | WRT_PROT_SEC_20 | 0: Sector protected | RO | 1 | ||
19 | WRT_PROT_SEC_19 | 0: Sector protected | RO | 1 | ||
18 | WRT_PROT_SEC_18 | 0: Sector protected | RO | 1 | ||
17 | WRT_PROT_SEC_17 | 0: Sector protected | RO | 1 | ||
16 | WRT_PROT_SEC_16 | 0: Sector protected | RO | 1 | ||
15 | WRT_PROT_SEC_15 | 0: Sector protected | RO | 1 | ||
14 | WRT_PROT_SEC_14 | 0: Sector protected | RO | 1 | ||
13 | WRT_PROT_SEC_13 | 0: Sector protected | RO | 1 | ||
12 | WRT_PROT_SEC_12 | 0: Sector protected | RO | 1 | ||
11 | WRT_PROT_SEC_11 | 0: Sector protected | RO | 1 | ||
10 | WRT_PROT_SEC_10 | 0: Sector protected | RO | 1 | ||
9 | WRT_PROT_SEC_9 | 0: Sector protected | RO | 1 | ||
8 | WRT_PROT_SEC_8 | 0: Sector protected | RO | 1 | ||
7 | WRT_PROT_SEC_7 | 0: Sector protected | RO | 1 | ||
6 | WRT_PROT_SEC_6 | 0: Sector protected | RO | 1 | ||
5 | WRT_PROT_SEC_5 | 0: Sector protected | RO | 1 | ||
4 | WRT_PROT_SEC_4 | 0: Sector protected | RO | 1 | ||
3 | WRT_PROT_SEC_3 | 0: Sector protected | RO | 1 | ||
2 | WRT_PROT_SEC_2 | 0: Sector protected | RO | 1 | ||
1 | WRT_PROT_SEC_1 | 0: Sector protected | RO | 1 | ||
0 | WRT_PROT_SEC_0 | 0: Sector protected | RO | 1 |
Address Offset | 0x0000 0FF4 | ||
Physical Address | 0x5000 3FF4 | Instance | 0x5000 3FF4 |
Description | Protect Sectors 32-63 Each bit write protects one 4KB flash sector from being both programmed and erased. Bit must be set to 0 in order to enable sector write protect. Not in use by CC26x0 and CC13x0. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31 | WRT_PROT_SEC_63 | 0: Sector protected | RO | 1 | ||
30 | WRT_PROT_SEC_62 | 0: Sector protected | RO | 1 | ||
29 | WRT_PROT_SEC_61 | 0: Sector protected | RO | 1 | ||
28 | WRT_PROT_SEC_60 | 0: Sector protected | RO | 1 | ||
27 | WRT_PROT_SEC_59 | 0: Sector protected | RO | 1 | ||
26 | WRT_PROT_SEC_58 | 0: Sector protected | RO | 1 | ||
25 | WRT_PROT_SEC_57 | 0: Sector protected | RO | 1 | ||
24 | WRT_PROT_SEC_56 | 0: Sector protected | RO | 1 | ||
23 | WRT_PROT_SEC_55 | 0: Sector protected | RO | 1 | ||
22 | WRT_PROT_SEC_54 | 0: Sector protected | RO | 1 | ||
21 | WRT_PROT_SEC_53 | 0: Sector protected | RO | 1 | ||
20 | WRT_PROT_SEC_52 | 0: Sector protected | RO | 1 | ||
19 | WRT_PROT_SEC_51 | 0: Sector protected | RO | 1 | ||
18 | WRT_PROT_SEC_50 | 0: Sector protected | RO | 1 | ||
17 | WRT_PROT_SEC_49 | 0: Sector protected | RO | 1 | ||
16 | WRT_PROT_SEC_48 | 0: Sector protected | RO | 1 | ||
15 | WRT_PROT_SEC_47 | 0: Sector protected | RO | 1 | ||
14 | WRT_PROT_SEC_46 | 0: Sector protected | RO | 1 | ||
13 | WRT_PROT_SEC_45 | 0: Sector protected | RO | 1 | ||
12 | WRT_PROT_SEC_44 | 0: Sector protected | RO | 1 | ||
11 | WRT_PROT_SEC_43 | 0: Sector protected | RO | 1 | ||
10 | WRT_PROT_SEC_42 | 0: Sector protected | RO | 1 | ||
9 | WRT_PROT_SEC_41 | 0: Sector protected | RO | 1 | ||
8 | WRT_PROT_SEC_40 | 0: Sector protected | RO | 1 | ||
7 | WRT_PROT_SEC_39 | 0: Sector protected | RO | 1 | ||
6 | WRT_PROT_SEC_38 | 0: Sector protected | RO | 1 | ||
5 | WRT_PROT_SEC_37 | 0: Sector protected | RO | 1 | ||
4 | WRT_PROT_SEC_36 | 0: Sector protected | RO | 1 | ||
3 | WRT_PROT_SEC_35 | 0: Sector protected | RO | 1 | ||
2 | WRT_PROT_SEC_34 | 0: Sector protected | RO | 1 | ||
1 | WRT_PROT_SEC_33 | 0: Sector protected | RO | 1 | ||
0 | WRT_PROT_SEC_32 | 0: Sector protected | RO | 1 |
Address Offset | 0x0000 0FF8 | ||
Physical Address | 0x5000 3FF8 | Instance | 0x5000 3FF8 |
Description | Protect Sectors 64-95 Each bit write protects one flash sector from being both programmed and erased. Bit must be set to 0 in order to enable sector write protect. Not in use by CC26x0 and CC13x0. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31 | WRT_PROT_SEC_95 | 0: Sector protected | RO | 1 | ||
30 | WRT_PROT_SEC_94 | 0: Sector protected | RO | 1 | ||
29 | WRT_PROT_SEC_93 | 0: Sector protected | RO | 1 | ||
28 | WRT_PROT_SEC_92 | 0: Sector protected | RO | 1 | ||
27 | WRT_PROT_SEC_91 | 0: Sector protected | RO | 1 | ||
26 | WRT_PROT_SEC_90 | 0: Sector protected | RO | 1 | ||
25 | WRT_PROT_SEC_89 | 0: Sector protected | RO | 1 | ||
24 | WRT_PROT_SEC_88 | 0: Sector protected | RO | 1 | ||
23 | WRT_PROT_SEC_87 | 0: Sector protected | RO | 1 | ||
22 | WRT_PROT_SEC_86 | 0: Sector protected | RO | 1 | ||
21 | WRT_PROT_SEC_85 | 0: Sector protected | RO | 1 | ||
20 | WRT_PROT_SEC_84 | 0: Sector protected | RO | 1 | ||
19 | WRT_PROT_SEC_83 | 0: Sector protected | RO | 1 | ||
18 | WRT_PROT_SEC_82 | 0: Sector protected | RO | 1 | ||
17 | WRT_PROT_SEC_81 | 0: Sector protected | RO | 1 | ||
16 | WRT_PROT_SEC_80 | 0: Sector protected | RO | 1 | ||
15 | WRT_PROT_SEC_79 | 0: Sector protected | RO | 1 | ||
14 | WRT_PROT_SEC_78 | 0: Sector protected | RO | 1 | ||
13 | WRT_PROT_SEC_77 | 0: Sector protected | RO | 1 | ||
12 | WRT_PROT_SEC_76 | 0: Sector protected | RO | 1 | ||
11 | WRT_PROT_SEC_75 | 0: Sector protected | RO | 1 | ||
10 | WRT_PROT_SEC_74 | 0: Sector protected | RO | 1 | ||
9 | WRT_PROT_SEC_73 | 0: Sector protected | RO | 1 | ||
8 | WRT_PROT_SEC_72 | 0: Sector protected | RO | 1 | ||
7 | WRT_PROT_SEC_71 | 0: Sector protected | RO | 1 | ||
6 | WRT_PROT_SEC_70 | 0: Sector protected | RO | 1 | ||
5 | WRT_PROT_SEC_69 | 0: Sector protected | RO | 1 | ||
4 | WRT_PROT_SEC_68 | 0: Sector protected | RO | 1 | ||
3 | WRT_PROT_SEC_67 | 0: Sector protected | RO | 1 | ||
2 | WRT_PROT_SEC_66 | 0: Sector protected | RO | 1 | ||
1 | WRT_PROT_SEC_65 | 0: Sector protected | RO | 1 | ||
0 | WRT_PROT_SEC_64 | 0: Sector protected | RO | 1 |
Address Offset | 0x0000 0FFC | ||
Physical Address | 0x5000 3FFC | Instance | 0x5000 3FFC |
Description | Protect Sectors 96-127 Each bit write protects one flash sector from being both programmed and erased. Bit must be set to 0 in order to enable sector write protect. Not in use by CC26x0 and CC13x0. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31 | WRT_PROT_SEC_127 | 0: Sector protected | RO | 1 | ||
30 | WRT_PROT_SEC_126 | 0: Sector protected | RO | 1 | ||
29 | WRT_PROT_SEC_125 | 0: Sector protected | RO | 1 | ||
28 | WRT_PROT_SEC_124 | 0: Sector protected | RO | 1 | ||
27 | WRT_PROT_SEC_123 | 0: Sector protected | RO | 1 | ||
26 | WRT_PROT_SEC_122 | 0: Sector protected | RO | 1 | ||
25 | WRT_PROT_SEC_121 | 0: Sector protected | RO | 1 | ||
24 | WRT_PROT_SEC_120 | 0: Sector protected | RO | 1 | ||
23 | WRT_PROT_SEC_119 | 0: Sector protected | RO | 1 | ||
22 | WRT_PROT_SEC_118 | 0: Sector protected | RO | 1 | ||
21 | WRT_PROT_SEC_117 | 0: Sector protected | RO | 1 | ||
20 | WRT_PROT_SEC_116 | 0: Sector protected | RO | 1 | ||
19 | WRT_PROT_SEC_115 | 0: Sector protected | RO | 1 | ||
18 | WRT_PROT_SEC_114 | 0: Sector protected | RO | 1 | ||
17 | WRT_PROT_SEC_113 | 0: Sector protected | RO | 1 | ||
16 | WRT_PROT_SEC_112 | 0: Sector protected | RO | 1 | ||
15 | WRT_PROT_SEC_111 | 0: Sector protected | RO | 1 | ||
14 | WRT_PROT_SEC_110 | 0: Sector protected | RO | 1 | ||
13 | WRT_PROT_SEC_109 | 0: Sector protected | RO | 1 | ||
12 | WRT_PROT_SEC_108 | 0: Sector protected | RO | 1 | ||
11 | WRT_PROT_SEC_107 | 0: Sector protected | RO | 1 | ||
10 | WRT_PROT_SEC_106 | 0: Sector protected | RO | 1 | ||
9 | WRT_PROT_SEC_105 | 0: Sector protected | RO | 1 | ||
8 | WRT_PROT_SEC_104 | 0: Sector protected | RO | 1 | ||
7 | WRT_PROT_SEC_103 | 0: Sector protected | RO | 1 | ||
6 | WRT_PROT_SEC_102 | 0: Sector protected | RO | 1 | ||
5 | WRT_PROT_SEC_101 | 0: Sector protected | RO | 1 | ||
4 | WRT_PROT_SEC_100 | 0: Sector protected | RO | 1 | ||
3 | WRT_PROT_SEC_99 | 0: Sector protected | RO | 1 | ||
2 | WRT_PROT_SEC_98 | 0: Sector protected | RO | 1 | ||
1 | WRT_PROT_SEC_97 | 0: Sector protected | RO | 1 | ||
0 | WRT_PROT_SEC_96 | 0: Sector protected | RO | 1 |
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