DDI_0_OSC

Instance: DDI_0_OSC
Component: DDI_0_OSC
Base address: 0x400CA000


This is the DDI for the digital block that controls all the analog clock oscillators (OSC_DIG) and performs qualification of the clocks generated.

TOP:DDI_0_OSC Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

CTL0

RW

32

0x0000 0000

0x0000 0000

0x400C A000

CTL1

RW

32

0x0000 0000

0x0000 0004

0x400C A004

RADCEXTCFG

RW

32

0x0000 0000

0x0000 0008

0x400C A008

AMPCOMPCTL

RW

32

0x0000 0000

0x0000 000C

0x400C A00C

AMPCOMPTH1

RW

32

0x0000 0000

0x0000 0010

0x400C A010

AMPCOMPTH2

RW

32

0x0000 0000

0x0000 0014

0x400C A014

ANABYPASSVAL1

RW

32

0x0000 0000

0x0000 0018

0x400C A018

ANABYPASSVAL2

RW

32

0x0000 0000

0x0000 001C

0x400C A01C

ATESTCTL

RW

32

0x0000 0000

0x0000 0020

0x400C A020

ADCDOUBLERNANOAMPCTL

RW

32

0x0000 0000

0x0000 0024

0x400C A024

XOSCHFCTL

RW

32

0x0000 0000

0x0000 0028

0x400C A028

LFOSCCTL

RW

32

0x0000 0000

0x0000 002C

0x400C A02C

RCOSCHFCTL

RW

32

0x0000 0000

0x0000 0030

0x400C A030

STAT0

RO

32

0x0000 0000

0x0000 0034

0x400C A034

STAT1

RO

32

0x0000 0000

0x0000 0038

0x400C A038

STAT2

RO

32

0x0000 0000

0x0000 003C

0x400C A03C

TOP:DDI_0_OSC Register Descriptions

TOP:DDI_0_OSC:CTL0

Address Offset 0x0000 0000
Physical Address 0x400C A000 Instance 0x400C A000
Description Control 0
Controls clock source selects
Type RW
Bits Field Name Description Type Reset
31 XTAL_IS_24M Set based on the accurate high frequency XTAL.
Value ENUM Name Description
0x0 48M Internal. Only to be used through TI provided API.
0x1 24M Internal. Only to be used through TI provided API.
RW 0
30 RESERVED30 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0
29 BYPASS_XOSC_LF_CLK_QUAL Internal. Only to be used through TI provided API. RW 0
28 BYPASS_RCOSC_LF_CLK_QUAL Internal. Only to be used through TI provided API. RW 0
27:26 DOUBLER_START_DURATION Internal. Only to be used through TI provided API. RW 0b00
25 DOUBLER_RESET_DURATION Internal. Only to be used through TI provided API. RW 0
24:23 RESERVED23 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b00
22 FORCE_KICKSTART_EN Internal. Only to be used through TI provided API. RW 0
21:17 RESERVED17 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b0 0000
16 ALLOW_SCLK_HF_SWITCHING 0: Default - Switching of HF clock source is disabled .
1: Allows switching of sclk_hf source.

Provided to prevent switching of the SCLK_HF source when running from flash (a long period during switching could corrupt flash). When sclk_hf switching is disabled, a new source can be started when SCLK_HF_SRC_SEL is changed, but the switch will not occur until this bit is set. This bit should be set to enable clock switching after STAT0.PENDINGSCLKHFSWITCHING indicates the new HF clock is ready. When switching completes (also indicated by STAT0.PENDINGSCLKHFSWITCHING) sclk_hf switching should be disabled to prevent flash corruption. Switching should not be enabled when running from flash.		 RW 0
15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0
14 HPOSC_MODE_EN Internal. Only to be used through TI provided API. RW 0
13 RESERVED13 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0
12 RCOSC_LF_TRIMMED Internal. Only to be used through TI provided API. RW 0
11 XOSC_HF_POWER_MODE Internal. Only to be used through TI provided API. RW 0
10 XOSC_LF_DIG_BYPASS Bypass XOSC_LF and use the digital input clock from AON for the xosc_lf clock.

0: Use 32kHz XOSC as xosc_lf clock source
1: Use digital input (from AON) as xosc_lf clock source.

This bit will only have effect when SCLK_LF_SRC_SEL is selecting the xosc_lf as the sclk_lf source. The muxing performed by this bit is not glitch free. The following procedure must be followed when changing this field to avoid glitches on sclk_lf.

1) Set SCLK_LF_SRC_SEL to select any source other than the xosc_lf clock source.
2) Set or clear this bit to bypass or not bypass the xosc_lf.
3) Set SCLK_LF_SRC_SEL to use xosc_lf.

It is recommended that either the rcosc_hf or xosc_hf (whichever is currently active) be selected as the source in step 1 above. This provides a faster clock change.		 RW 0
9 CLK_LOSS_EN Enable clock loss detection and hence the indicators to system controller. Checks both SCLK_HF and SCLK_LF clock loss indicators.

0: Disable
1: Enable

Clock loss detection must be disabled when changing the sclk_lf source. STAT0.SCLK_LF_SRC can be polled to determine when a change to a new sclk_lf source has completed.		 RW 0
8:7 ACLK_TDC_SRC_SEL Source select for aclk_tdc.

00: RCOSC_HF (48MHz)
01: RCOSC_HF (24MHz)
10: XOSC_HF (24MHz)
11: Not used		 RW 0b00
6:5 ACLK_REF_SRC_SEL Source select for aclk_ref

00: RCOSC_HF derived (31.25kHz)
01: XOSC_HF derived (31.25kHz)
10: RCOSC_LF (32kHz)
11: XOSC_LF (32.768kHz)		 RW 0b00
4 SPARE4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0
3:2 SCLK_LF_SRC_SEL Source select for sclk_lf
Value ENUM Name Description
0x0 RCOSCHFDLF Low frequency clock derived from High Frequency RCOSC
0x1 XOSCHFDLF Low frequency clock derived from High Frequency XOSC
0x2 RCOSCLF Low frequency RCOSC
0x3 XOSCLF Low frequency XOSC
RW 0b00
1 SCLK_MF_SRC_SEL Internal. Only to be used through TI provided API.
Value ENUM Name Description
0x0 RCOSCHFDMF Internal. Only to be used through TI provided API.
0x1 XCOSCHFDMF Medium frequency clock derived from high frequency XOSC.
RW 0
0 SCLK_HF_SRC_SEL Source select for sclk_hf. XOSC option is supported for test and debug only and should be used when the XOSC_HF is running.
Value ENUM Name Description
0x0 RCOSC High frequency RCOSC clock
0x1 XOSC High frequency XOSC clk
RW 0

TOP:DDI_0_OSC:CTL1

Address Offset 0x0000 0004
Physical Address 0x400C A004 Instance 0x400C A004
Description Control 1
This register contains OSC_DIG configuration
Type RW
Bits Field Name Description Type Reset
31:23 RESERVED23 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b0 0000 0000
22:18 RCOSCHFCTRIMFRACT Internal. Only to be used through TI provided API. RW 0b0 0000
17 RCOSCHFCTRIMFRACT_EN Internal. Only to be used through TI provided API. RW 0
16:2 SPARE2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b000 0000 0000 0000
1:0 XOSC_HF_FAST_START Internal. Only to be used through TI provided API. RW 0b00

TOP:DDI_0_OSC:RADCEXTCFG

Address Offset 0x0000 0008
Physical Address 0x400C A008 Instance 0x400C A008
Description RADC External Configuration
Type RW
Bits Field Name Description Type Reset
31:22 HPM_IBIAS_WAIT_CNT Internal. Only to be used through TI provided API. RW 0b00 0000 0000
21:16 LPM_IBIAS_WAIT_CNT Internal. Only to be used through TI provided API. RW 0b00 0000
15:12 IDAC_STEP Internal. Only to be used through TI provided API. RW 0x0
11:6 RADC_DAC_TH Internal. Only to be used through TI provided API. RW 0b00 0000
5 RADC_MODE_IS_SAR Internal. Only to be used through TI provided API. RW 0
4:0 RESERVED0 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b0 0000

TOP:DDI_0_OSC:AMPCOMPCTL

Address Offset 0x0000 000C
Physical Address 0x400C A00C Instance 0x400C A00C
Description Amplitude Compensation Control
Type RW
Bits Field Name Description Type Reset
31 SPARE31 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0
30 AMPCOMP_REQ_MODE Internal. Only to be used through TI provided API. RW 0
29:28 AMPCOMP_FSM_UPDATE_RATE Internal. Only to be used through TI provided API.
Value ENUM Name Description
0x0 2MHZ Internal. Only to be used through TI provided API.
0x1 1MHZ Internal. Only to be used through TI provided API.
0x2 500KHZ Internal. Only to be used through TI provided API.
0x3 250KHZ Internal. Only to be used through TI provided API.
RW 0b00
27 AMPCOMP_SW_CTRL Internal. Only to be used through TI provided API. RW 0
26 AMPCOMP_SW_EN Internal. Only to be used through TI provided API. RW 0
25:24 RESERVED24 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b00
23:20 IBIAS_OFFSET Internal. Only to be used through TI provided API. RW 0x0
19:16 IBIAS_INIT Internal. Only to be used through TI provided API. RW 0x0
15:8 LPM_IBIAS_WAIT_CNT_FINAL Internal. Only to be used through TI provided API. RW 0x00
7:4 CAP_STEP Internal. Only to be used through TI provided API. RW 0x0
3:0 IBIASCAP_HPTOLP_OL_CNT Internal. Only to be used through TI provided API. RW 0x0

TOP:DDI_0_OSC:AMPCOMPTH1

Address Offset 0x0000 0010
Physical Address 0x400C A010 Instance 0x400C A010
Description Amplitude Compensation Threshold 1
This register contains threshold values for amplitude compensation algorithm
Type RW
Bits Field Name Description Type Reset
31:24 SPARE24 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0x00
23:18 HPMRAMP3_LTH Internal. Only to be used through TI provided API. RW 0b00 0000
17:16 SPARE16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b00
15:10 HPMRAMP3_HTH Internal. Only to be used through TI provided API. RW 0b00 0000
9:6 IBIASCAP_LPTOHP_OL_CNT Internal. Only to be used through TI provided API. RW 0x0
5:0 HPMRAMP1_TH Internal. Only to be used through TI provided API. RW 0b00 0000

TOP:DDI_0_OSC:AMPCOMPTH2

Address Offset 0x0000 0014
Physical Address 0x400C A014 Instance 0x400C A014
Description Amplitude Compensation Threshold 2
This register contains threshold values for amplitude compensation algorithm.
Type RW
Bits Field Name Description Type Reset
31:26 LPMUPDATE_LTH Internal. Only to be used through TI provided API. RW 0b00 0000
25:24 SPARE24 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b00
23:18 LPMUPDATE_HTH Internal. Only to be used through TI provided API. RW 0b00 0000
17:16 SPARE16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b00
15:10 ADC_COMP_AMPTH_LPM Internal. Only to be used through TI provided API. RW 0b00 0000
9:8 SPARE8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b00
7:2 ADC_COMP_AMPTH_HPM Internal. Only to be used through TI provided API. RW 0b00 0000
1:0 SPARE0 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b00

TOP:DDI_0_OSC:ANABYPASSVAL1

Address Offset 0x0000 0018
Physical Address 0x400C A018 Instance 0x400C A018
Description Analog Bypass Values 1
Type RW
Bits Field Name Description Type Reset
31:20 RESERVED20 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0x000
19:16 XOSC_HF_ROW_Q12 Internal. Only to be used through TI provided API. RW 0x0
15:0 XOSC_HF_COLUMN_Q12 Internal. Only to be used through TI provided API. RW 0x0000

TOP:DDI_0_OSC:ANABYPASSVAL2

Address Offset 0x0000 001C
Physical Address 0x400C A01C Instance 0x400C A01C
Description Internal. Only to be used through TI provided API.
Type RW
Bits Field Name Description Type Reset
31:14 RESERVED14 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b00 0000 0000 0000 0000
13:0 XOSC_HF_IBIASTHERM Internal. Only to be used through TI provided API. RW 0b00 0000 0000 0000

TOP:DDI_0_OSC:ATESTCTL

Address Offset 0x0000 0020
Physical Address 0x400C A020 Instance 0x400C A020
Description Analog Test Control
Type RW
Bits Field Name Description Type Reset
31:30 SPARE30 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b00
29 SCLK_LF_AUX_EN Enable 32 kHz clock to AUX_COMPB. RW 0
28:0 RESERVED0 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b0 0000 0000 0000 0000 0000 0000 0000

TOP:DDI_0_OSC:ADCDOUBLERNANOAMPCTL

Address Offset 0x0000 0024
Physical Address 0x400C A024 Instance 0x400C A024
Description ADC Doubler Nanoamp Control
Type RW
Bits Field Name Description Type Reset
31:25 RESERVED25 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b000 0000
24 NANOAMP_BIAS_ENABLE Internal. Only to be used through TI provided API. RW 0
23 SPARE23 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RW 0
22:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b0 0000 0000 0000 0000
5 ADC_SH_MODE_EN Internal. Only to be used through TI provided API. RW 0
4 ADC_SH_VBUF_EN Internal. Only to be used through TI provided API. RW 0
3:2 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b00
1:0 ADC_IREF_CTRL Internal. Only to be used through TI provided API. RW 0b00

TOP:DDI_0_OSC:XOSCHFCTL

Address Offset 0x0000 0028
Physical Address 0x400C A028 Instance 0x400C A028
Description XOSCHF Control
Type RW
Bits Field Name Description Type Reset
31:10 RESERVED10 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b00 0000 0000 0000 0000 0000
9:8 PEAK_DET_ITRIM Internal. Only to be used through TI provided API. RW 0b00
7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0
6 BYPASS Internal. Only to be used through TI provided API. RW 0
5 RESERVED5 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0
4:2 HP_BUF_ITRIM Internal. Only to be used through TI provided API. RW 0b000
1:0 LP_BUF_ITRIM Internal. Only to be used through TI provided API. RW 0b00

TOP:DDI_0_OSC:LFOSCCTL

Address Offset 0x0000 002C
Physical Address 0x400C A02C Instance 0x400C A02C
Description Low Frequency Oscillator Control
Type RW
Bits Field Name Description Type Reset
31:24 RESERVED24 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0x00
23:22 XOSCLF_REGULATOR_TRIM Internal. Only to be used through TI provided API. RW 0b00
21:18 XOSCLF_CMIRRWR_RATIO Internal. Only to be used through TI provided API. RW 0x0
17:10 RESERVED10 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0x00
9:8 RCOSCLF_RTUNE_TRIM Internal. Only to be used through TI provided API.
Value ENUM Name Description
0x0 7P5MEG Internal. Only to be used through TI provided API.
0x1 7P0MEG Internal. Only to be used through TI provided API.
0x2 6P5MEG Internal. Only to be used through TI provided API.
0x3 6P0MEG Internal. Only to be used through TI provided API.
RW 0b00
7:0 RCOSCLF_CTUNE_TRIM Internal. Only to be used through TI provided API. RW 0x00

TOP:DDI_0_OSC:RCOSCHFCTL

Address Offset 0x0000 0030
Physical Address 0x400C A030 Instance 0x400C A030
Description RCOSCHF Control
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0x0000
15:8 RCOSCHF_CTRIM Internal. Only to be used through TI provided API. RW 0x00
7:0 RESERVED0 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0x00

TOP:DDI_0_OSC:STAT0

Address Offset 0x0000 0034
Physical Address 0x400C A034 Instance 0x400C A034
Description Status 0
This register contains status signals from OSC_DIG
Type RO
Bits Field Name Description Type Reset
31 SPARE31 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
30:29 SCLK_LF_SRC Indicates source for the sclk_lf
Value ENUM Name Description
0x0 RCOSCHFDLF Low frequency clock derived from High Frequency RCOSC
0x1 XOSCHFDLF Low frequency clock derived from High Frequency XOSC
0x2 RCOSCLF Low frequency RCOSC
0x3 XOSCLF Low frequency XOSC
RO 0b00
28 SCLK_HF_SRC Indicates source for the sclk_hf
Value ENUM Name Description
0x0 RCOSC High frequency RCOSC clock
0x1 XOSC High frequency XOSC
RO 0
27:23 RESERVED23 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
22 RCOSC_HF_EN RCOSC_HF_EN RO 0
21 RCOSC_LF_EN RCOSC_LF_EN RO 0
20 XOSC_LF_EN XOSC_LF_EN RO 0
19 CLK_DCDC_RDY CLK_DCDC_RDY RO 0
18 CLK_DCDC_RDY_ACK CLK_DCDC_RDY_ACK RO 0
17 SCLK_HF_LOSS Indicates sclk_hf is lost RO 0
16 SCLK_LF_LOSS Indicates sclk_lf is lost RO 0
15 XOSC_HF_EN Indicates that XOSC_HF is enabled. RO 0
14 RESERVED14 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
13 XB_48M_CLK_EN Indicates that the 48MHz clock from the DOUBLER is enabled.

It will be enabled if 24 or 48 MHz crystal is used (enabled in doubler bypass for the 48MHz crystal).		 RO 0
12 RESERVED12 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
11 XOSC_HF_LP_BUF_EN XOSC_HF_LP_BUF_EN RO 0
10 XOSC_HF_HP_BUF_EN XOSC_HF_HP_BUF_EN RO 0
9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
8 ADC_THMET ADC_THMET RO 0
7 ADC_DATA_READY indicates when adc_data is ready. RO 0
6:1 ADC_DATA adc_data RO 0b00 0000
0 PENDINGSCLKHFSWITCHING Indicates when sclk_hf is ready to be switched RO 0

TOP:DDI_0_OSC:STAT1

Address Offset 0x0000 0038
Physical Address 0x400C A038 Instance 0x400C A038
Description Status 1
This register contains status signals from OSC_DIG
Type RO
Bits Field Name Description Type Reset
31:28 RAMPSTATE AMPCOMP FSM State
Value ENUM Name Description
0x0 RESET RESET
0x1 INITIALIZATION INITIALIZATION
0x2 HPM_RAMP1 HPM_RAMP1
0x3 HPM_RAMP2 HPM_RAMP2
0x4 HPM_RAMP3 HPM_RAMP3
0x5 HPM_UPDATE HPM_UPDATE
0x6 IDAC_INCREMENT IDAC_INCREMENT
0x7 IBIAS_CAP_UPDATE IBIAS_CAP_UPDATE
0x8 IBIAS_DEC_W_MEASURE IBIAS_DECREMENT_WITH_MEASURE
0x9 LPM_UPDATE LPM_UPDATE
0xA IBIAS_INC IBIAS_INCREMENT
0xB IDAC_DEC_W_MEASURE IDAC_DECREMENT_WITH_MEASURE
0xC DUMMY_TO_INIT_1 DUMMY_TO_INIT_1
0xD FAST_START FAST_START
0xE FAST_START_SETTLE FAST_START_SETTLE
RO 0x0
27:22 HPM_UPDATE_AMP OSC amplitude during HPM_UPDATE state.
When amplitude compensation of XOSC_HF is enabled in high performance mode, this value is the amplitude of the crystal oscillations measured by the on-chip oscillator ADC, divided by 15 mV. For example, a value of 0x20 would indicate that the amplitude of the crystal is approximately 480 mV. To enable amplitude compensation, AON_WUC OSCCFG must be set to a non-zero value.		 RO 0b00 0000
21:16 LPM_UPDATE_AMP OSC amplitude during LPM_UPDATE state
When amplitude compensation of XOSC_HF is enabled in low power mode, this value is the amplitude of the crystal oscillations measured by the on-chip oscillator ADC, divided by 15 mV. For example, a value of 0x20 would indicate that the amplitude of the crystal is approximately 480 mV. To enable amplitude compensation, AON_WUC OSCCFG must be set to a non-zero value.		 RO 0b00 0000
15 FORCE_RCOSC_HF force_rcosc_hf RO 0
14 SCLK_HF_EN SCLK_HF_EN RO 0
13 SCLK_MF_EN SCLK_MF_EN RO 0
12 ACLK_ADC_EN ACLK_ADC_EN RO 0
11 ACLK_TDC_EN ACLK_TDC_EN RO 0
10 ACLK_REF_EN ACLK_REF_EN RO 0
9 CLK_CHP_EN CLK_CHP_EN RO 0
8 CLK_DCDC_EN CLK_DCDC_EN RO 0
7 SCLK_HF_GOOD SCLK_HF_GOOD RO 0
6 SCLK_MF_GOOD SCLK_MF_GOOD RO 0
5 SCLK_LF_GOOD SCLK_LF_GOOD RO 0
4 ACLK_ADC_GOOD ACLK_ADC_GOOD RO 0
3 ACLK_TDC_GOOD ACLK_TDC_GOOD RO 0
2 ACLK_REF_GOOD ACLK_REF_GOOD RO 0
1 CLK_CHP_GOOD CLK_CHP_GOOD RO 0
0 CLK_DCDC_GOOD CLK_DCDC_GOOD RO 0

TOP:DDI_0_OSC:STAT2

Address Offset 0x0000 003C
Physical Address 0x400C A03C Instance 0x400C A03C
Description Status 2
This register contains status signals from AMPCOMP FSM
Type RO
Bits Field Name Description Type Reset
31:26 ADC_DCBIAS DC Bias read by RADC during SAR mode
The value is an unsigned integer. It is used for debug only.		 RO 0b00 0000
25 HPM_RAMP1_THMET Indication of threshold is met for hpm_ramp1 RO 0
24 HPM_RAMP2_THMET Indication of threshold is met for hpm_ramp2 RO 0
23 HPM_RAMP3_THMET Indication of threshold is met for hpm_ramp3 RO 0
22:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000
15:12 RAMPSTATE xosc_hf amplitude compensation FSM

This is identical to STAT1.RAMPSTATE. See that description for encoding.		 RO 0x0
11:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00
3 AMPCOMP_REQ ampcomp_req RO 0
2 XOSC_HF_AMPGOOD amplitude of xosc_hf is within the required threshold (set by DDI). Not used for anything just for debug/status RO 0
1 XOSC_HF_FREQGOOD frequency of xosc_hf is good to use for the digital clocks RO 0
0 XOSC_HF_RF_FREQGOOD frequency of xosc_hf is within +/- 20 ppm and xosc_hf is good for radio operations. Used for SW to start synthesizer. RO 0


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