SAILAPIGuide  1_10_00_06
bma2x2.h
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1 
58 #ifndef __BMA2x2_H__
59 #define __BMA2x2_H__
60 /****************************************************************/
62 /************************************************************/
75 #ifdef __KERNEL__
76 
77 #include <linux/types.h>
78 /* singed integer type*/
79 typedef int8_t s8;
80 typedef int16_t s16;
81 typedef int32_t s32;
82 typedef int64_t s64;
84 typedef u_int8_t u8;
85 typedef u_int16_t u16;
86 typedef u_int32_t u32;
87 typedef u_int64_t u64;
91 #else /* ! __KERNEL__ */
92 /**********************************************************
93 * These definition uses for define the C
94 * standard version data types
95 ***********************************************************/
96 # if !defined(__STDC_VERSION__)
97 
98 /************************************************
99  * compiler is C11 C standard
100 ************************************************/
101 #if (__STDC_VERSION__ == 201112L)
102 
103 /************************************************/
104 #include <stdint.h>
105 /************************************************/
106 
107 /*unsigned integer types*/
108 typedef uint8_t u8;
109 typedef uint16_t u16;
110 typedef uint32_t u32;
111 typedef uint64_t u64;
113 /*signed integer types*/
114 typedef int8_t s8;
115 typedef int16_t s16;
116 typedef int32_t s32;
117 typedef int64_t s64;
118 /************************************************
119  * compiler is C99 C standard
120 ************************************************/
121 
122 #elif (__STDC_VERSION__ == 199901L)
123 
124 /* stdint.h is a C99 supported c library.
125 which is used to fixed the integer size*/
126 /************************************************/
127 #include <stdint.h>
128 /************************************************/
129 
130 /*unsigned integer types*/
131 typedef uint8_t u8;
132 typedef uint16_t u16;
133 typedef uint32_t u32;
134 typedef uint64_t u64;
136 /*signed integer types*/
137 typedef int8_t s8;
138 typedef int16_t s16;
139 typedef int32_t s32;
140 typedef int64_t s64;
141 /************************************************
142  * compiler is C89 or other C standard
143 ************************************************/
144 
145 #else /* !defined(__STDC_VERSION__) */
146 
151 #define MACHINE_32_BIT
152 
157 #ifdef MACHINE_16_BIT
158 #include <limits.h>
159 /*signed integer types*/
160 typedef signed char s8;
161 typedef signed short int s16;
162 typedef signed long int s32;
164 #if defined(LONG_MAX) && LONG_MAX == 0x7fffffffffffffffL
165 typedef long int s64;
166 typedef unsigned long int u64;
167 #elif defined(LLONG_MAX) && (LLONG_MAX == 0x7fffffffffffffffLL)
168 typedef long long int s64;
169 typedef unsigned long long int u64;
170 #else
171 #warning Either the correct data type for signed 64 bit integer \
172 could not be found, or 64 bit integers are not supported in your environment.
173 #warning If 64 bit integers are supported on your platform, \
174 please set s64 manually.
175 #endif
176 
177 /*unsigned integer types*/
178 typedef unsigned char u8;
179 typedef unsigned short int u16;
180 typedef unsigned long int u32;
182 /* If your machine support 32 bit
183 define the MACHINE_32_BIT*/
184 #elif defined MACHINE_32_BIT
185 /*signed integer types*/
186 typedef signed char s8;
187 typedef signed short int s16;
188 typedef signed int s32;
189 typedef signed long long int s64;
191 /*unsigned integer types*/
192 typedef unsigned char u8;
193 typedef unsigned short int u16;
194 typedef unsigned int u32;
195 typedef unsigned long long int u64;
197 /* If your machine support 64 bit
198 define the MACHINE_64_BIT*/
199 #elif defined MACHINE_64_BIT
200 /*signed integer types*/
201 typedef signed char s8;
202 typedef signed short int s16;
203 typedef signed int s32;
204 typedef signed long int s64;
206 /*unsigned integer types*/
207 typedef unsigned char u8;
208 typedef unsigned short int u16;
209 typedef unsigned int u32;
210 typedef unsigned long int u64;
212 #else
213 #warning The data types defined above which not supported \
214 define the data types manually
215 #endif
216 #endif
217 
218 /*** This else will execute for the compilers
219  * which are not supported the C standards
220  * Like C89/C99/C11***/
221 #else
222 
227 #define MACHINE_32_BIT
228 
229 /* If your machine support 16 bit
230 define the MACHINE_16_BIT*/
231 #ifdef MACHINE_16_BIT
232 #include <limits.h>
233 /*signed integer types*/
234 typedef signed char s8;
235 typedef signed short int s16;
236 typedef signed long int s32;
238 #if defined(LONG_MAX) && LONG_MAX == 0x7fffffffffffffffL
239 typedef long int s64;
240 typedef unsigned long int u64;
241 #elif defined(LLONG_MAX) && (LLONG_MAX == 0x7fffffffffffffffLL)
242 typedef long long int s64;
243 typedef unsigned long long int u64;
244 #else
245 #warning Either the correct data type for signed 64 bit integer \
246 could not be found, or 64 bit integers are not supported in your environment.
247 #warning If 64 bit integers are supported on your platform, \
248 please set s64 manually.
249 #endif
250 
251 /*unsigned integer types*/
252 typedef unsigned char u8;
253 typedef unsigned short int u16;
254 typedef unsigned long int u32;
258 #elif defined MACHINE_32_BIT
259 /*signed integer types*/
260 typedef signed char s8;
261 typedef signed short int s16;
262 typedef signed int s32;
263 typedef signed long long int s64;
265 /*unsigned integer types*/
266 typedef unsigned char u8;
267 typedef unsigned short int u16;
268 typedef unsigned int u32;
269 typedef unsigned long long int u64;
271 /* If your machine support 64 bit
272 define the MACHINE_64_BIT*/
273 #elif defined MACHINE_64_BIT
274 /*signed integer types*/
275 typedef signed char s8;
276 typedef signed short int s16;
277 typedef signed int s32;
278 typedef signed long int s64;
280 /*unsigned integer types*/
281 typedef unsigned char u8;
282 typedef unsigned short int u16;
283 typedef unsigned int u32;
284 typedef unsigned long int u64;
286 #else
287 #warning The data types defined above which not supported \
288 define the data types manually
289 #endif
290 #endif
291 #endif
292 
293 /***************************************************************/
295 /***************************************************************/
314 #define BMA2x2_WR_FUNC_PTR s8(*bus_write)\
315 (u8, u8, u8 *, u8)
316 
338 #define BMA2x2_BUS_WRITE_FUNC(dev_addr, reg_addr, reg_data, wr_len)\
339 bus_write(dev_addr, reg_addr, reg_data, wr_len)
340 
341 
361 #define BMA2x2_SPI_RD_MASK 0x80
362 /* for spi read transactions on SPI the MSB has to be set */
363 #define BMA2x2_RD_FUNC_PTR s8(*bus_read)\
364 (u8, u8, u8 *, u8)
365 #define BMA2x2_BRD_FUNC_PTR s8(*burst_read)\
366 (u8, u8, u8 *, u32)
367 
393 #define BMA2x2_BUS_READ_FUNC(dev_addr, reg_addr, reg_data, r_len)\
394 bus_read(dev_addr, reg_addr, reg_data, r_len)
395 #define BMA2x2_BURST_READ_FUNC(device_addr,\
396 register_addr, register_data, rd_len)\
397 burst_read(device_addr, register_addr, register_data, rd_len)
398 /**************************************************************/
400 /**************************************************************/
412 #define BMA2x2_I2C_ADDR1 (0x18)
413 #define BMA2x2_I2C_ADDR2 (0x19)
414 
420 #define BMA2x2_I2C_ADDR3 (0x10)
421 #define BMA2x2_I2C_ADDR4 (0x11)
422 
423 /**************************************************************/
425 /**************************************************************/
426 #define BMA2x2_INIT_VALUE ((u8)0)
427 #define BMA2x2_GEN_READ_WRITE_LENGTH ((u8)1)
428 #define BMA2x2_LSB_MSB_READ_LENGTH ((u8)2)
429 
430 #define BMA2x2_SHIFT_TWO_BITS ((u8)2)
431 #define BMA2x2_SHIFT_FOUR_BITS ((u8)4)
432 #define BMA2x2_SHIFT_FIVE_BITS ((u8)5)
433 #define BMA2x2_SHIFT_SIX_BITS ((u8)6)
434 #define BMA2x2_SHIFT_EIGHT_BITS ((u8)8)
435 
436 #define BMA2x2_FIFO_MODE_STATUS_RANGE ((u8)2)
437 #define BMA2x2_FIFO_DATA_SELECT_RANGE ((u8)4)
438 #define BMA2x2_FIFO_MODE_RANGE ((u8)4)
439 #define BMA2x2_FIFO_WML_RANGE ((u8)32)
440 
441 #define BMA2x2_ACCEL_BW_MIN_RANGE ((u8)7)
442 #define BMA2x2_ACCEL_BW_1000HZ_RANGE ((u8)15)
443 #define BMA2x2_ACCEL_BW_MAX_RANGE ((u8)16)
444 #define BMA2x2_SLEEP_DURN_MIN_RANGE ((u8)4)
445 #define BMA2x2_SLEEP_TIMER_MODE_RANGE ((u8)2)
446 #define BMA2x2_SLEEP_DURN_MAX_RANGE ((u8)16)
447 #define BMA2x2_POWER_MODE_RANGE ((u8)6)
448 #define BMA2x2_SELF_TEST_AXIS_RANGE ((u8)4)
449 #define BMA2x2_SELF_TEST_SIGN_RANGE ((u8)2)
450 
451 /**************************************************************/
453 /**************************************************************/
454 #define E_OUT_OF_RANGE ((s8)-2)
455 #define E_BMA2x2_NULL_PTR ((s8)-127)
456 #define BMA2x2_NULL ((void *)0)
457 #define ERROR ((s8)-1)
458 #define SUCCESS ((u8)0)
459 /**************************************************************/
461 /**************************************************************/
462 #define BMA2x2_RETURN_FUNCTION_TYPE s8
463 
465 /**************************************************************/
467 /**************************************************************/
468 #define BMA2x2_EEP_OFFSET (0x16)
469 #define BMA2x2_IMAGE_BASE (0x38)
470 #define BMA2x2_IMAGE_LEN (22)
471 #define BMA2x2_CHIP_ID_ADDR (0x00)
472 
473 #define BMA2x2_X_AXIS_LSB_ADDR (0x02)
474 #define BMA2x2_X_AXIS_MSB_ADDR (0x03)
475 #define BMA2x2_Y_AXIS_LSB_ADDR (0x04)
476 #define BMA2x2_Y_AXIS_MSB_ADDR (0x05)
477 #define BMA2x2_Z_AXIS_LSB_ADDR (0x06)
478 #define BMA2x2_Z_AXIS_MSB_ADDR (0x07)
479 #define BMA2x2_TEMP_ADDR (0x08)
480 
481 #define BMA2x2_STAT1_ADDR (0x09)
482 #define BMA2x2_STAT2_ADDR (0x0A)
483 #define BMA2x2_STAT_TAP_SLOPE_ADDR (0x0B)
484 #define BMA2x2_STAT_ORIENT_HIGH_ADDR (0x0C)
485 #define BMA2x2_STAT_FIFO_ADDR (0x0E)
486 
487 #define BMA2x2_RANGE_SELECT_ADDR (0x0F)
488 #define BMA2x2_BW_SELECT_ADDR (0x10)
489 #define BMA2x2_MODE_CTRL_ADDR (0x11)
490 #define BMA2x2_LOW_NOISE_CTRL_ADDR (0x12)
491 #define BMA2x2_DATA_CTRL_ADDR (0x13)
492 #define BMA2x2_RST_ADDR (0x14)
493 
494 #define BMA2x2_INTR_ENABLE1_ADDR (0x16)
495 #define BMA2x2_INTR_ENABLE2_ADDR (0x17)
496 #define BMA2x2_INTR_SLOW_NO_MOTION_ADDR (0x18)
497 #define BMA2x2_INTR1_PAD_SELECT_ADDR (0x19)
498 #define BMA2x2_INTR_DATA_SELECT_ADDR (0x1A)
499 #define BMA2x2_INTR2_PAD_SELECT_ADDR (0x1B)
500 #define BMA2x2_INTR_SOURCE_ADDR (0x1E)
501 #define BMA2x2_INTR_SET_ADDR (0x20)
502 #define BMA2x2_INTR_CTRL_ADDR (0x21)
503 
504 #define BMA2x2_LOW_DURN_ADDR (0x22)
505 #define BMA2x2_LOW_THRES_ADDR (0x23)
506 #define BMA2x2_LOW_HIGH_HYST_ADDR (0x24)
507 #define BMA2x2_HIGH_DURN_ADDR (0x25)
508 #define BMA2x2_HIGH_THRES_ADDR (0x26)
509 #define BMA2x2_SLOPE_DURN_ADDR (0x27)
510 #define BMA2x2_SLOPE_THRES_ADDR (0x28)
511 #define BMA2x2_SLOW_NO_MOTION_THRES_ADDR (0x29)
512 #define BMA2x2_TAP_PARAM_ADDR (0x2A)
513 #define BMA2x2_TAP_THRES_ADDR (0x2B)
514 #define BMA2x2_ORIENT_PARAM_ADDR (0x2C)
515 #define BMA2x2_THETA_BLOCK_ADDR (0x2D)
516 #define BMA2x2_THETA_FLAT_ADDR (0x2E)
517 #define BMA2x2_FLAT_HOLD_TIME_ADDR (0x2F)
518 #define BMA2x2_SELFTEST_ADDR (0x32)
519 #define BMA2x2_EEPROM_CTRL_ADDR (0x33)
520 #define BMA2x2_SERIAL_CTRL_ADDR (0x34)
521 
522 #define BMA2x2_OFFSET_CTRL_ADDR (0x36)
523 #define BMA2x2_OFFSET_PARAMS_ADDR (0x37)
524 #define BMA2x2_OFFSET_X_AXIS_ADDR (0x38)
525 #define BMA2x2_OFFSET_Y_AXIS_ADDR (0x39)
526 #define BMA2x2_OFFSET_Z_AXIS_ADDR (0x3A)
527 
528 #define BMA2x2_GP0_ADDR (0x3B)
529 #define BMA2x2_GP1_ADDR (0x3C)
530 
531 #define BMA2x2_FIFO_MODE_ADDR (0x3E)
532 #define BMA2x2_FIFO_DATA_OUTPUT_ADDR (0x3F)
533 #define BMA2x2_FIFO_WML_TRIG (0x30)
534 
535 /**************************************************************/
537 /**************************************************************/
538 #define BMA2x2_12_RESOLUTION (0)
539 #define BMA2x2_10_RESOLUTION (1)
540 #define BMA2x2_14_RESOLUTION (2)
541 
542 /**************************************************************/
544 /**************************************************************/
545 /* register write and read delays */
546 #define BMA2x2_MDELAY_DATA_TYPE u32
547 #define BMA2x2_EE_W_DELAY (28)
548 
549 /**************************************************************/
551 /**************************************************************/
555 struct bma2x2_accel_data {
556 s16 x,
557 y,
558 z;
559 };
564 struct bma2x2_accel_data_temp {
565 s16 x,
566 y,
567 z;
568 s8 temp;
569 };
570 
574 struct bma2x2_accel_eight_resolution {
575 s8 x,
576 y,
577 z;
578 };
582 struct bma2x2_accel_eight_resolution_temp {
583 s8 x,
584 y,
585 z;
586 s8 temp;
587 };
600 struct bma2x2_t {
601 u8 power_mode_u8;
602 u8 chip_id;
603 u8 ctrl_mode_reg;
604 u8 low_mode_reg;
605 u8 dev_addr;
606 u8 fifo_config;
607 BMA2x2_WR_FUNC_PTR;
608 BMA2x2_RD_FUNC_PTR;
609 BMA2x2_BRD_FUNC_PTR;
610 void (*delay_msec)(BMA2x2_MDELAY_DATA_TYPE);
613 };
614 
615 /*********************************************************************/
617 /********************************************************************/
618 /******************************/
620 /******************************/
621 #define BMA2x2_CHIP_ID_POS (0)
622 #define BMA2x2_CHIP_ID_MSK (0xFF)
623 #define BMA2x2_CHIP_ID_LEN (8)
624 #define BMA2x2_CHIP_ID_REG BMA2x2_CHIP_ID_ADDR
625 
626 /******************************/
628 /******************************/
629 #define BMA2x2_NEW_DATA_X_POS (0)
630 #define BMA2x2_NEW_DATA_X_LEN (1)
631 #define BMA2x2_NEW_DATA_X_MSK (0x01)
632 #define BMA2x2_NEW_DATA_X_REG BMA2x2_X_AXIS_LSB_ADDR
633 
634 #define BMA2x2_ACCEL_X14_LSB_POS (2)
635 #define BMA2x2_ACCEL_X14_LSB_LEN (6)
636 #define BMA2x2_ACCEL_X14_LSB_MSK (0xFC)
637 #define BMA2x2_ACCEL_X14_LSB_REG BMA2x2_X_AXIS_LSB_ADDR
638 
639 #define BMA2x2_ACCEL_X12_LSB_POS (4)
640 #define BMA2x2_ACCEL_X12_LSB_LEN (4)
641 #define BMA2x2_ACCEL_X12_LSB_MSK (0xF0)
642 #define BMA2x2_ACCEL_X12_LSB_REG BMA2x2_X_AXIS_LSB_ADDR
643 
644 #define BMA2x2_ACCEL_X10_LSB_POS (6)
645 #define BMA2x2_ACCEL_X10_LSB_LEN (2)
646 #define BMA2x2_ACCEL_X10_LSB_MSK (0xC0)
647 #define BMA2x2_ACCEL_X10_LSB_REG BMA2x2_X_AXIS_LSB_ADDR
648 
649 #define BMA2x2_ACCEL_X8_LSB_POS (0)
650 #define BMA2x2_ACCEL_X8_LSB_LEN (0)
651 #define BMA2x2_ACCEL_X8_LSB_MSK (0x00)
652 #define BMA2x2_ACCEL_X8_LSB_REG BMA2x2_X_AXIS_LSB_ADDR
653 
654 #define BMA2x2_ACCEL_X_MSB_POS (0)
655 #define BMA2x2_ACCEL_X_MSB_LEN (8)
656 #define BMA2x2_ACCEL_X_MSB_MSK (0xFF)
657 #define BMA2x2_ACCEL_X_MSB_REG BMA2x2_X_AXIS_MSB_ADDR
658 /******************************/
660 /******************************/
661 #define BMA2x2_NEW_DATA_Y_POS (0)
662 #define BMA2x2_NEW_DATA_Y_LEN (1)
663 #define BMA2x2_NEW_DATA_Y_MSK (0x01)
664 #define BMA2x2_NEW_DATA_Y_REG BMA2x2_Y_AXIS_LSB_ADDR
665 
666 #define BMA2x2_ACCEL_Y14_LSB_POS (2)
667 #define BMA2x2_ACCEL_Y14_LSB_LEN (6)
668 #define BMA2x2_ACCEL_Y14_LSB_MSK (0xFC)
669 #define BMA2x2_ACCEL_Y14_LSB_REG BMA2x2_Y_AXIS_LSB_ADDR
670 
671 #define BMA2x2_ACCEL_Y12_LSB_POS (4)
672 #define BMA2x2_ACCEL_Y12_LSB_LEN (4)
673 #define BMA2x2_ACCEL_Y12_LSB_MSK (0xF0)
674 #define BMA2x2_ACCEL_Y12_LSB_REG BMA2x2_Y_AXIS_LSB_ADDR
675 
676 #define BMA2x2_ACCEL_Y10_LSB_POS (6)
677 #define BMA2x2_ACCEL_Y10_LSB_LEN (2)
678 #define BMA2x2_ACCEL_Y10_LSB_MSK (0xC0)
679 #define BMA2x2_ACCEL_Y10_LSB_REG BMA2x2_Y_AXIS_LSB_ADDR
680 
681 #define BMA2x2_ACCEL_Y8_LSB_POS (0)
682 #define BMA2x2_ACCEL_Y8_LSB_LEN (0)
683 #define BMA2x2_ACCEL_Y8_LSB_MSK (0x00)
684 #define BMA2x2_ACCEL_Y8_LSB_REG BMA2x2_Y_AXIS_LSB_ADDR
685 
686 #define BMA2x2_ACCEL_Y_MSB_POS (0)
687 #define BMA2x2_ACCEL_Y_MSB_LEN (8)
688 #define BMA2x2_ACCEL_Y_MSB_MSK (0xFF)
689 #define BMA2x2_ACCEL_Y_MSB_REG BMA2x2_Y_AXIS_MSB_ADDR
690 /******************************/
692 /******************************/
693 #define BMA2x2_NEW_DATA_Z_POS (0)
694 #define BMA2x2_NEW_DATA_Z_LEN (1)
695 #define BMA2x2_NEW_DATA_Z_MSK (0x01)
696 #define BMA2x2_NEW_DATA_Z_REG BMA2x2_Z_AXIS_LSB_ADDR
697 
698 #define BMA2x2_ACCEL_Z14_LSB_POS (2)
699 #define BMA2x2_ACCEL_Z14_LSB_LEN (6)
700 #define BMA2x2_ACCEL_Z14_LSB_MSK (0xFC)
701 #define BMA2x2_ACCEL_Z14_LSB_REG BMA2x2_Z_AXIS_LSB_ADDR
702 
703 #define BMA2x2_ACCEL_Z12_LSB_POS (4)
704 #define BMA2x2_ACCEL_Z12_LSB_LEN (4)
705 #define BMA2x2_ACCEL_Z12_LSB_MSK (0xF0)
706 #define BMA2x2_ACCEL_Z12_LSB_REG BMA2x2_Z_AXIS_LSB_ADDR
707 
708 #define BMA2x2_ACCEL_Z10_LSB_POS (6)
709 #define BMA2x2_ACCEL_Z10_LSB_LEN (2)
710 #define BMA2x2_ACCEL_Z10_LSB_MSK (0xC0)
711 #define BMA2x2_ACCEL_Z10_LSB_REG BMA2x2_Z_AXIS_LSB_ADDR
712 
713 #define BMA2x2_ACCEL_Z8_LSB_POS (0)
714 #define BMA2x2_ACCEL_Z8_LSB_LEN (0)
715 #define BMA2x2_ACCEL_Z8_LSB_MSK (0x00)
716 #define BMA2x2_ACCEL_Z8_LSB_REG BMA2x2_Z_AXIS_LSB_ADDR
717 
718 #define BMA2x2_ACCEL_Z_MSB_POS (0)
719 #define BMA2x2_ACCEL_Z_MSB_LEN (8)
720 #define BMA2x2_ACCEL_Z_MSB_MSK (0xFF)
721 #define BMA2x2_ACCEL_Z_MSB_REG BMA2x2_Z_AXIS_MSB_ADDR
722 
723 /******************************/
725 /******************************/
726 #define BMA2x2_ACCEL_TEMP_MSB_POS (0)
727 #define BMA2x2_ACCEL_TEMP_MSB_LEN (8)
728 #define BMA2x2_ACCEL_TEMP_MSB_MSK (0xFF)
729 #define BMA2x2_ACCEL_TEMP_MSB_REG BMA2x2_TEMPERATURE_REG
730 
731 /***************************************/
733 /**************************************/
734 #define BMA2x2_LOW_G_INTR_STAT_POS (0)
735 #define BMA2x2_LOW_G_INTR_STAT_LEN (1)
736 #define BMA2x2_LOW_G_INTR_STAT_MSK (0x01)
737 #define BMA2x2_LOW_G_INTR_STAT_REG BMA2x2_STAT1_ADDR
738 /***************************************/
740 /**************************************/
741 #define BMA2x2_HIGH_G_INTR_STAT_POS (1)
742 #define BMA2x2_HIGH_G_INTR_STAT_LEN (1)
743 #define BMA2x2_HIGH_G_INTR_STAT_MSK (0x02)
744 #define BMA2x2_HIGH_G_INTR_STAT_REG BMA2x2_STAT1_ADDR
745 /***************************************/
747 /**************************************/
748 #define BMA2x2_SLOPE_INTR_STAT_POS (2)
749 #define BMA2x2_SLOPE_INTR_STAT_LEN (1)
750 #define BMA2x2_SLOPE_INTR_STAT_MSK (0x04)
751 #define BMA2x2_SLOPE_INTR_STAT_REG BMA2x2_STAT1_ADDR
752 /*******************************************/
754 /*******************************************/
755 #define BMA2x2_SLOW_NO_MOTION_INTR_STAT_POS (3)
756 #define BMA2x2_SLOW_NO_MOTION_INTR_STAT_LEN (1)
757 #define BMA2x2_SLOW_NO_MOTION_INTR_STAT_MSK (0x08)
758 #define BMA2x2_SLOW_NO_MOTION_INTR_STAT_REG BMA2x2_STAT1_ADDR
759 /***************************************/
761 /**************************************/
762 #define BMA2x2_DOUBLE_TAP_INTR_STAT_POS (4)
763 #define BMA2x2_DOUBLE_TAP_INTR_STAT_LEN (1)
764 #define BMA2x2_DOUBLE_TAP_INTR_STAT_MSK (0x10)
765 #define BMA2x2_DOUBLE_TAP_INTR_STAT_REG BMA2x2_STAT1_ADDR
766 /***************************************/
768 /**************************************/
769 #define BMA2x2_SINGLE_TAP_INTR_STAT_POS (5)
770 #define BMA2x2_SINGLE_TAP_INTR_STAT_LEN (1)
771 #define BMA2x2_SINGLE_TAP_INTR_STAT_MSK (0x20)
772 #define BMA2x2_SINGLE_TAP_INTR_STAT_REG BMA2x2_STAT1_ADDR
773 /***************************************/
775 /**************************************/
776 #define BMA2x2_ORIENT_INTR_STAT_POS (6)
777 #define BMA2x2_ORIENT_INTR_STAT_LEN (1)
778 #define BMA2x2_ORIENT_INTR_STAT_MSK (0x40)
779 #define BMA2x2_ORIENT_INTR_STAT_REG BMA2x2_STAT1_ADDR
780 /***************************************/
782 /**************************************/
783 #define BMA2x2_FLAT_INTR_STAT_POS (7)
784 #define BMA2x2_FLAT_INTR_STAT_LEN (1)
785 #define BMA2x2_FLAT_INTR_STAT_MSK (0x80)
786 #define BMA2x2_FLAT_INTR_STAT_REG BMA2x2_STAT1_ADDR
787 /***************************************/
789 /**************************************/
790 #define BMA2x2_FIFO_FULL_INTR_STAT_POS (5)
791 #define BMA2x2_FIFO_FULL_INTR_STAT_LEN (1)
792 #define BMA2x2_FIFO_FULL_INTR_STAT_MSK (0x20)
793 #define BMA2x2_FIFO_FULL_INTR_STAT_REG BMA2x2_STAT2_ADDR
794 /*******************************************/
796 /******************************************/
797 #define BMA2x2_FIFO_WM_INTR_STAT_POS (6)
798 #define BMA2x2_FIFO_WM_INTR_STAT_LEN (1)
799 #define BMA2x2_FIFO_WM_INTR_STAT_MSK (0x40)
800 #define BMA2x2_FIFO_WM_INTR_STAT_REG BMA2x2_STAT2_ADDR
801 /***************************************/
803 /**************************************/
804 #define BMA2x2_DATA_INTR_STAT_POS (7)
805 #define BMA2x2_DATA_INTR_STAT_LEN (1)
806 #define BMA2x2_DATA_INTR_STAT_MSK (0x80)
807 #define BMA2x2_DATA_INTR_STAT_REG BMA2x2_STAT2_ADDR
808 /*********************************************/
810 /*********************************************/
811 #define BMA2x2_SLOPE_FIRST_X_POS (0)
812 #define BMA2x2_SLOPE_FIRST_X_LEN (1)
813 #define BMA2x2_SLOPE_FIRST_X_MSK (0x01)
814 #define BMA2x2_SLOPE_FIRST_X_REG BMA2x2_STAT_TAP_SLOPE_ADDR
815 
816 #define BMA2x2_SLOPE_FIRST_Y_POS (1)
817 #define BMA2x2_SLOPE_FIRST_Y_LEN (1)
818 #define BMA2x2_SLOPE_FIRST_Y_MSK (0x02)
819 #define BMA2x2_SLOPE_FIRST_Y_REG BMA2x2_STAT_TAP_SLOPE_ADDR
820 
821 #define BMA2x2_SLOPE_FIRST_Z_POS (2)
822 #define BMA2x2_SLOPE_FIRST_Z_LEN (1)
823 #define BMA2x2_SLOPE_FIRST_Z_MSK (0x04)
824 #define BMA2x2_SLOPE_FIRST_Z_REG BMA2x2_STAT_TAP_SLOPE_ADDR
825 
826 #define BMA2x2_SLOPE_SIGN_STAT_POS (3)
827 #define BMA2x2_SLOPE_SIGN_STAT_LEN (1)
828 #define BMA2x2_SLOPE_SIGN_STAT_MSK (0x08)
829 #define BMA2x2_SLOPE_SIGN_STAT_REG BMA2x2_STAT_TAP_SLOPE_ADDR
830 /*********************************************/
832 /*********************************************/
833 #define BMA2x2_TAP_FIRST_X_POS (4)
834 #define BMA2x2_TAP_FIRST_X_LEN (1)
835 #define BMA2x2_TAP_FIRST_X_MSK (0x10)
836 #define BMA2x2_TAP_FIRST_X_REG BMA2x2_STAT_TAP_SLOPE_ADDR
837 
838 #define BMA2x2_TAP_FIRST_Y_POS (5)
839 #define BMA2x2_TAP_FIRST_Y_LEN (1)
840 #define BMA2x2_TAP_FIRST_Y_MSK (0x20)
841 #define BMA2x2_TAP_FIRST_Y_REG BMA2x2_STAT_TAP_SLOPE_ADDR
842 
843 #define BMA2x2_TAP_FIRST_Z_POS (6)
844 #define BMA2x2_TAP_FIRST_Z_LEN (1)
845 #define BMA2x2_TAP_FIRST_Z_MSK (0x40)
846 #define BMA2x2_TAP_FIRST_Z_REG BMA2x2_STAT_TAP_SLOPE_ADDR
847 
848 #define BMA2x2_TAP_SIGN_STAT_POS (7)
849 #define BMA2x2_TAP_SIGN_STAT_LEN (1)
850 #define BMA2x2_TAP_SIGN_STAT_MSK (0x80)
851 #define BMA2x2_TAP_SIGN_STAT_REG BMA2x2_STAT_TAP_SLOPE_ADDR
852 /*********************************************/
854 /*********************************************/
855 #define BMA2x2_HIGH_G_FIRST_X_POS (0)
856 #define BMA2x2_HIGH_G_FIRST_X_LEN (1)
857 #define BMA2x2_HIGH_G_FIRST_X_MSK (0x01)
858 #define BMA2x2_HIGH_G_FIRST_X_REG BMA2x2_STAT_ORIENT_HIGH_ADDR
859 
860 #define BMA2x2_HIGH_G_FIRST_Y_POS (1)
861 #define BMA2x2_HIGH_G_FIRST_Y_LEN (1)
862 #define BMA2x2_HIGH_G_FIRST_Y_MSK (0x02)
863 #define BMA2x2_HIGH_G_FIRST_Y_REG BMA2x2_STAT_ORIENT_HIGH_ADDR
864 
865 #define BMA2x2_HIGH_G_FIRST_Z_POS (2)
866 #define BMA2x2_HIGH_G_FIRST_Z_LEN (1)
867 #define BMA2x2_HIGH_G_FIRST_Z_MSK (0x04)
868 #define BMA2x2_HIGH_G_FIRST_Z_REG BMA2x2_STAT_ORIENT_HIGH_ADDR
869 
870 #define BMA2x2_HIGH_G_SIGN_STAT_POS (3)
871 #define BMA2x2_HIGH_G_SIGN_STAT_LEN (1)
872 #define BMA2x2_HIGH_G_SIGN_STAT_MSK (0x08)
873 #define BMA2x2_HIGH_G_SIGN_STAT_REG BMA2x2_STAT_ORIENT_HIGH_ADDR
874 /*********************************************/
876 /*********************************************/
877 #define BMA2x2_ORIENT_STAT_POS (4)
878 #define BMA2x2_ORIENT_STAT_LEN (3)
879 #define BMA2x2_ORIENT_STAT_MSK (0x70)
880 #define BMA2x2_ORIENT_STAT_REG BMA2x2_STAT_ORIENT_HIGH_ADDR
881 /*********************************************/
883 /*********************************************/
884 #define BMA2x2_FLAT_STAT_POS (7)
885 #define BMA2x2_FLAT_STAT_LEN (1)
886 #define BMA2x2_FLAT_STAT_MSK (0x80)
887 #define BMA2x2_FLAT_STAT_REG BMA2x2_STAT_ORIENT_HIGH_ADDR
888 
889 /*********************************************/
891 /*********************************************/
892 #define BMA2x2_FIFO_FRAME_COUNT_STAT_POS (0)
893 #define BMA2x2_FIFO_FRAME_COUNT_STAT_LEN (7)
894 #define BMA2x2_FIFO_FRAME_COUNT_STAT_MSK (0x7F)
895 #define BMA2x2_FIFO_FRAME_COUNT_STAT_REG BMA2x2_STAT_FIFO_ADDR
896 /*********************************************/
898 /*********************************************/
899 #define BMA2x2_FIFO_OVERRUN_STAT_POS (7)
900 #define BMA2x2_FIFO_OVERRUN_STAT_LEN (1)
901 #define BMA2x2_FIFO_OVERRUN_STAT_MSK (0x80)
902 #define BMA2x2_FIFO_OVERRUN_STAT_REG BMA2x2_STAT_FIFO_ADDR
903 /****************************/
905 /****************************/
906 #define BMA2x2_RANGE_SELECT_POS (0)
907 #define BMA2x2_RANGE_SELECT_LEN (4)
908 #define BMA2x2_RANGE_SELECT_MSK (0x0F)
909 #define BMA2x2_RANGE_SELECT_REG BMA2x2_RANGE_SELECT_ADDR
910 /****************************/
912 /****************************/
913 #define BMA2x2_BW_POS (0)
914 #define BMA2x2_BW_LEN (5)
915 #define BMA2x2_BW_MSK (0x1F)
916 #define BMA2x2_BW_REG BMA2x2_BW_SELECT_ADDR
917 /****************************/
919 /****************************/
920 #define BMA2x2_SLEEP_DURN_POS (1)
921 #define BMA2x2_SLEEP_DURN_LEN (4)
922 #define BMA2x2_SLEEP_DURN_MSK (0x1E)
923 #define BMA2x2_SLEEP_DURN_REG BMA2x2_MODE_CTRL_ADDR
924 /****************************/
926 /****************************/
927 #define BMA2x2_MODE_CTRL_POS (5)
928 #define BMA2x2_MODE_CTRL_LEN (3)
929 #define BMA2x2_MODE_CTRL_MSK (0xE0)
930 #define BMA2x2_MODE_CTRL_REG BMA2x2_MODE_CTRL_ADDR
931 /****************************/
933 /****************************/
934 #define BMA2x2_SLEEP_TIMER_POS (5)
935 #define BMA2x2_SLEEP_TIMER_LEN (1)
936 #define BMA2x2_SLEEP_TIMER_MSK (0x20)
937 #define BMA2x2_SLEEP_TIMER_REG BMA2x2_LOW_NOISE_CTRL_ADDR
938 /****************************/
940 /****************************/
941 #define BMA2x2_LOW_POWER_MODE_POS (6)
942 #define BMA2x2_LOW_POWER_MODE_LEN (1)
943 #define BMA2x2_LOW_POWER_MODE_MSK (0x40)
944 #define BMA2x2_LOW_POWER_MODE_REG BMA2x2_LOW_NOISE_CTRL_ADDR
945 /*******************************************/
947 /*******************************************/
948 #define BMA2x2_DIS_SHADOW_PROC_POS (6)
949 #define BMA2x2_DIS_SHADOW_PROC_LEN (1)
950 #define BMA2x2_DIS_SHADOW_PROC_MSK (0x40)
951 #define BMA2x2_DIS_SHADOW_PROC_REG BMA2x2_DATA_CTRL_ADDR
952 /***************************************************/
954 /***************************************************/
955 #define BMA2x2_ENABLE_DATA_HIGH_BW_POS (7)
956 #define BMA2x2_ENABLE_DATA_HIGH_BW_LEN (1)
957 #define BMA2x2_ENABLE_DATA_HIGH_BW_MSK (0x80)
958 #define BMA2x2_ENABLE_DATA_HIGH_BW_REG BMA2x2_DATA_CTRL_ADDR
959 /***************************************************/
961 /***************************************************/
962 #define BMA2x2_ENABLE_SOFT_RESET_VALUE (0xB6)
963 /**********************************************/
965 /**********************************************/
966 #define BMA2x2_ENABLE_SLOPE_X_INTR_POS (0)
967 #define BMA2x2_ENABLE_SLOPE_X_INTR_LEN (1)
968 #define BMA2x2_ENABLE_SLOPE_X_INTR_MSK (0x01)
969 #define BMA2x2_ENABLE_SLOPE_X_INTR_REG BMA2x2_INTR_ENABLE1_ADDR
970 
971 #define BMA2x2_ENABLE_SLOPE_Y_INTR_POS (1)
972 #define BMA2x2_ENABLE_SLOPE_Y_INTR_LEN (1)
973 #define BMA2x2_ENABLE_SLOPE_Y_INTR_MSK (0x02)
974 #define BMA2x2_ENABLE_SLOPE_Y_INTR_REG BMA2x2_INTR_ENABLE1_ADDR
975 
976 #define BMA2x2_ENABLE_SLOPE_Z_INTR_POS (2)
977 #define BMA2x2_ENABLE_SLOPE_Z_INTR_LEN (1)
978 #define BMA2x2_ENABLE_SLOPE_Z_INTR_MSK (0x04)
979 #define BMA2x2_ENABLE_SLOPE_Z_INTR_REG BMA2x2_INTR_ENABLE1_ADDR
980 /**********************************************/
982 /**********************************************/
983 #define BMA2x2_ENABLE_DOUBLE_TAP_INTR_POS (4)
984 #define BMA2x2_ENABLE_DOUBLE_TAP_INTR_LEN (1)
985 #define BMA2x2_ENABLE_DOUBLE_TAP_INTR_MSK (0x10)
986 #define BMA2x2_ENABLE_DOUBLE_TAP_INTR_REG BMA2x2_INTR_ENABLE1_ADDR
987 /**********************************************/
989 /**********************************************/
990 #define BMA2x2_ENABLE_SINGLE_TAP_INTR_POS (5)
991 #define BMA2x2_ENABLE_SINGLE_TAP_INTR_LEN (1)
992 #define BMA2x2_ENABLE_SINGLE_TAP_INTR_MSK (0x20)
993 #define BMA2x2_ENABLE_SINGLE_TAP_INTR_REG BMA2x2_INTR_ENABLE1_ADDR
994 /**********************************************/
996 /**********************************************/
997 #define BMA2x2_ENABLE_ORIENT_INTR_POS (6)
998 #define BMA2x2_ENABLE_ORIENT_INTR_LEN (1)
999 #define BMA2x2_ENABLE_ORIENT_INTR_MSK (0x40)
1000 #define BMA2x2_ENABLE_ORIENT_INTR_REG BMA2x2_INTR_ENABLE1_ADDR
1001 /**********************************************/
1003 /**********************************************/
1004 #define BMA2x2_ENABLE_FLAT_INTR_POS (7)
1005 #define BMA2x2_ENABLE_FLAT_INTR_LEN (1)
1006 #define BMA2x2_ENABLE_FLAT_INTR_MSK (0x80)
1007 #define BMA2x2_ENABLE_FLAT_INTR_REG BMA2x2_INTR_ENABLE1_ADDR
1008 /**********************************************/
1010 /**********************************************/
1011 #define BMA2x2_ENABLE_HIGH_G_X_INTR_POS (0)
1012 #define BMA2x2_ENABLE_HIGH_G_X_INTR_LEN (1)
1013 #define BMA2x2_ENABLE_HIGH_G_X_INTR_MSK (0x01)
1014 #define BMA2x2_ENABLE_HIGH_G_X_INTR_REG BMA2x2_INTR_ENABLE2_ADDR
1015 
1016 #define BMA2x2_ENABLE_HIGH_G_Y_INTR_POS (1)
1017 #define BMA2x2_ENABLE_HIGH_G_Y_INTR_LEN (1)
1018 #define BMA2x2_ENABLE_HIGH_G_Y_INTR_MSK (0x02)
1019 #define BMA2x2_ENABLE_HIGH_G_Y_INTR_REG BMA2x2_INTR_ENABLE2_ADDR
1020 
1021 #define BMA2x2_ENABLE_HIGH_G_Z_INTR_POS (2)
1022 #define BMA2x2_ENABLE_HIGH_G_Z_INTR_LEN (1)
1023 #define BMA2x2_ENABLE_HIGH_G_Z_INTR_MSK (0x04)
1024 #define BMA2x2_ENABLE_HIGH_G_Z_INTR_REG BMA2x2_INTR_ENABLE2_ADDR
1025 /**********************************************/
1027 /**********************************************/
1028 #define BMA2x2_ENABLE_LOW_G_INTR_POS (3)
1029 #define BMA2x2_ENABLE_LOW_G_INTR_LEN (1)
1030 #define BMA2x2_ENABLE_LOW_G_INTR_MSK (0x08)
1031 #define BMA2x2_ENABLE_LOW_G_INTR_REG BMA2x2_INTR_ENABLE2_ADDR
1032 /**********************************************/
1034 /**********************************************/
1035 #define BMA2x2_ENABLE_NEW_DATA_INTR_POS (4)
1036 #define BMA2x2_ENABLE_NEW_DATA_INTR_LEN (1)
1037 #define BMA2x2_ENABLE_NEW_DATA_INTR_MSK (0x10)
1038 #define BMA2x2_ENABLE_NEW_DATA_INTR_REG BMA2x2_INTR_ENABLE2_ADDR
1039 /**********************************************/
1041 /**********************************************/
1042 #define BMA2x2_INTR_FIFO_FULL_ENABLE_INTR_POS (5)
1043 #define BMA2x2_INTR_FIFO_FULL_ENABLE_INTR_LEN (1)
1044 #define BMA2x2_INTR_FIFO_FULL_ENABLE_INTR_MSK (0x20)
1045 #define BMA2x2_INTR_FIFO_FULL_ENABLE_INTR_REG BMA2x2_INTR_ENABLE2_ADDR
1046 /**********************************************/
1048 /**********************************************/
1049 #define BMA2x2_INTR_FIFO_WM_ENABLE_INTR_POS (6)
1050 #define BMA2x2_INTR_FIFO_WM_ENABLE_INTR_LEN (1)
1051 #define BMA2x2_INTR_FIFO_WM_ENABLE_INTR_MSK (0x40)
1052 #define BMA2x2_INTR_FIFO_WM_ENABLE_INTR_REG BMA2x2_INTR_ENABLE2_ADDR
1053 /************************************************/
1055 /*************************************************/
1056 #define BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_X_INTR_POS (0)
1057 #define BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_X_INTR_LEN (1)
1058 #define BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_X_INTR_MSK (0x01)
1059 #define BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_X_INTR_REG \
1060 BMA2x2_INTR_SLOW_NO_MOTION_ADDR
1061 
1062 #define BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_Y_INTR_POS (1)
1063 #define BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_Y_INTR_LEN (1)
1064 #define BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_Y_INTR_MSK (0x02)
1065 #define BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_Y_INTR_REG \
1066 BMA2x2_INTR_SLOW_NO_MOTION_ADDR
1067 
1068 #define BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_Z_INTR_POS (2)
1069 #define BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_Z_INTR_LEN (1)
1070 #define BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_Z_INTR_MSK (0x04)
1071 #define BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_Z_INTR_REG \
1072 BMA2x2_INTR_SLOW_NO_MOTION_ADDR
1073 /**********************************************/
1075 /**********************************************/
1076 #define BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_SELECT_INTR_POS (3)
1077 #define BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_SELECT_INTR_LEN (1)
1078 #define BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_SELECT_INTR_MSK (0x08)
1079 #define BMA2x2_INTR_SLOW_NO_MOTION_ENABLE_SELECT_INTR_REG \
1080 BMA2x2_INTR_SLOW_NO_MOTION_ADDR
1081 /**********************************************/
1083 /**********************************************/
1084 #define BMA2x2_ENABLE_INTR1_PAD_LOW_G_POS (0)
1085 #define BMA2x2_ENABLE_INTR1_PAD_LOW_G_LEN (1)
1086 #define BMA2x2_ENABLE_INTR1_PAD_LOW_G_MSK (0x01)
1087 #define BMA2x2_ENABLE_INTR1_PAD_LOW_G_REG BMA2x2_INTR1_PAD_SELECT_ADDR
1088 /**********************************************/
1090 /**********************************************/
1091 #define BMA2x2_ENABLE_INTR1_PAD_HIGH_G_POS (1)
1092 #define BMA2x2_ENABLE_INTR1_PAD_HIGH_G_LEN (1)
1093 #define BMA2x2_ENABLE_INTR1_PAD_HIGH_G_MSK (0x02)
1094 #define BMA2x2_ENABLE_INTR1_PAD_HIGH_G_REG BMA2x2_INTR1_PAD_SELECT_ADDR
1095 /**********************************************/
1097 /**********************************************/
1098 #define BMA2x2_ENABLE_INTR1_PAD_SLOPE_POS (2)
1099 #define BMA2x2_ENABLE_INTR1_PAD_SLOPE_LEN (1)
1100 #define BMA2x2_ENABLE_INTR1_PAD_SLOPE_MSK (0x04)
1101 #define BMA2x2_ENABLE_INTR1_PAD_SLOPE_REG BMA2x2_INTR1_PAD_SELECT_ADDR
1102 /**********************************************/
1104 /**********************************************/
1105 #define BMA2x2_ENABLE_INTR1_PAD_SLOW_NO_MOTION_POS (3)
1106 #define BMA2x2_ENABLE_INTR1_PAD_SLOW_NO_MOTION_LEN (1)
1107 #define BMA2x2_ENABLE_INTR1_PAD_SLOW_NO_MOTION_MSK (0x08)
1108 #define BMA2x2_ENABLE_INTR1_PAD_SLOW_NO_MOTION_REG \
1109 BMA2x2_INTR1_PAD_SELECT_ADDR
1110 /**********************************************/
1112 /**********************************************/
1113 #define BMA2x2_ENABLE_INTR1_PAD_DOUBLE_TAP_POS (4)
1114 #define BMA2x2_ENABLE_INTR1_PAD_DOUBLE_TAP_LEN (1)
1115 #define BMA2x2_ENABLE_INTR1_PAD_DOUBLE_TAP_MSK (0x10)
1116 #define BMA2x2_ENABLE_INTR1_PAD_DOUBLE_TAP_REG BMA2x2_INTR1_PAD_SELECT_ADDR
1117 /**********************************************/
1119 /**********************************************/
1120 #define BMA2x2_ENABLE_INTR1_PAD_SINGLE_TAP_POS (5)
1121 #define BMA2x2_ENABLE_INTR1_PAD_SINGLE_TAP_LEN (1)
1122 #define BMA2x2_ENABLE_INTR1_PAD_SINGLE_TAP_MSK (0x20)
1123 #define BMA2x2_ENABLE_INTR1_PAD_SINGLE_TAP_REG BMA2x2_INTR1_PAD_SELECT_ADDR
1124 /**********************************************/
1126 /**********************************************/
1127 #define BMA2x2_ENABLE_INTR1_PAD_ORIENT_POS (6)
1128 #define BMA2x2_ENABLE_INTR1_PAD_ORIENT_LEN (1)
1129 #define BMA2x2_ENABLE_INTR1_PAD_ORIENT_MSK (0x40)
1130 #define BMA2x2_ENABLE_INTR1_PAD_ORIENT_REG BMA2x2_INTR1_PAD_SELECT_ADDR
1131 /**********************************************/
1133 /**********************************************/
1134 #define BMA2x2_ENABLE_INTR1_PAD_FLAT_POS (7)
1135 #define BMA2x2_ENABLE_INTR1_PAD_FLAT_LEN (1)
1136 #define BMA2x2_ENABLE_INTR1_PAD_FLAT_MSK (0x80)
1137 #define BMA2x2_ENABLE_INTR1_PAD_FLAT_REG BMA2x2_INTR1_PAD_SELECT_ADDR
1138 /**********************************************/
1140 /**********************************************/
1141 #define BMA2x2_ENABLE_INTR2_PAD_LOW_G_POS (0)
1142 #define BMA2x2_ENABLE_INTR2_PAD_LOW_G_LEN (1)
1143 #define BMA2x2_ENABLE_INTR2_PAD_LOW_G_MSK (0x01)
1144 #define BMA2x2_ENABLE_INTR2_PAD_LOW_G_REG BMA2x2_INTR2_PAD_SELECT_ADDR
1145 /**********************************************/
1147 /**********************************************/
1148 #define BMA2x2_ENABLE_INTR2_PAD_HIGH_G_POS (1)
1149 #define BMA2x2_ENABLE_INTR2_PAD_HIGH_G_LEN (1)
1150 #define BMA2x2_ENABLE_INTR2_PAD_HIGH_G_MSK (0x02)
1151 #define BMA2x2_ENABLE_INTR2_PAD_HIGH_G_REG BMA2x2_INTR2_PAD_SELECT_ADDR
1152 /**********************************************/
1154 /**********************************************/
1155 #define BMA2x2_ENABLE_INTR2_PAD_SLOPE_POS (2)
1156 #define BMA2x2_ENABLE_INTR2_PAD_SLOPE_LEN (1)
1157 #define BMA2x2_ENABLE_INTR2_PAD_SLOPE_MSK (0x04)
1158 #define BMA2x2_ENABLE_INTR2_PAD_SLOPE_REG BMA2x2_INTR2_PAD_SELECT_ADDR
1159 /**********************************************/
1161 /**********************************************/
1162 #define BMA2x2_ENABLE_INTR2_PAD_SLOW_NO_MOTION_POS (3)
1163 #define BMA2x2_ENABLE_INTR2_PAD_SLOW_NO_MOTION_LEN (1)
1164 #define BMA2x2_ENABLE_INTR2_PAD_SLOW_NO_MOTION_MSK (0x08)
1165 #define BMA2x2_ENABLE_INTR2_PAD_SLOW_NO_MOTION_REG \
1166 BMA2x2_INTR2_PAD_SELECT_ADDR
1167 /**********************************************/
1169 /**********************************************/
1170 #define BMA2x2_ENABLE_INTR2_PAD_DOUBLE_TAP_POS (4)
1171 #define BMA2x2_ENABLE_INTR2_PAD_DOUBLE_TAP_LEN (1)
1172 #define BMA2x2_ENABLE_INTR2_PAD_DOUBLE_TAP_MSK (0x10)
1173 #define BMA2x2_ENABLE_INTR2_PAD_DOUBLE_TAP_REG BMA2x2_INTR2_PAD_SELECT_ADDR
1174 /**********************************************/
1176 /**********************************************/
1177 #define BMA2x2_ENABLE_INTR2_PAD_SINGLE_TAP_POS (5)
1178 #define BMA2x2_ENABLE_INTR2_PAD_SINGLE_TAP_LEN (1)
1179 #define BMA2x2_ENABLE_INTR2_PAD_SINGLE_TAP_MSK (0x20)
1180 #define BMA2x2_ENABLE_INTR2_PAD_SINGLE_TAP_REG BMA2x2_INTR2_PAD_SELECT_ADDR
1181 /**********************************************/
1183 /**********************************************/
1184 #define BMA2x2_ENABLE_INTR2_PAD_ORIENT_POS (6)
1185 #define BMA2x2_ENABLE_INTR2_PAD_ORIENT_LEN (1)
1186 #define BMA2x2_ENABLE_INTR2_PAD_ORIENT_MSK (0x40)
1187 #define BMA2x2_ENABLE_INTR2_PAD_ORIENT_REG BMA2x2_INTR2_PAD_SELECT_ADDR
1188 /**********************************************/
1190 /**********************************************/
1191 #define BMA2x2_ENABLE_INTR2_PAD_FLAT_POS (7)
1192 #define BMA2x2_ENABLE_INTR2_PAD_FLAT_LEN (1)
1193 #define BMA2x2_ENABLE_INTR2_PAD_FLAT_MSK (0x80)
1194 #define BMA2x2_ENABLE_INTR2_PAD_FLAT_REG BMA2x2_INTR2_PAD_SELECT_ADDR
1195 /**********************************************/
1197 /**********************************************/
1198 #define BMA2x2_ENABLE_INTR1_PAD_NEWDATA_POS (0)
1199 #define BMA2x2_ENABLE_INTR1_PAD_NEWDATA_LEN (1)
1200 #define BMA2x2_ENABLE_INTR1_PAD_NEWDATA_MSK (0x01)
1201 #define BMA2x2_ENABLE_INTR1_PAD_NEWDATA_REG BMA2x2_INTR_DATA_SELECT_ADDR
1202 /**********************************************/
1204 /**********************************************/
1205 #define BMA2x2_ENABLE_INTR1_PAD_FIFO_WM_POS (1)
1206 #define BMA2x2_ENABLE_INTR1_PAD_FIFO_WM_LEN (1)
1207 #define BMA2x2_ENABLE_INTR1_PAD_FIFO_WM_MSK (0x02)
1208 #define BMA2x2_ENABLE_INTR1_PAD_FIFO_WM_REG BMA2x2_INTR_DATA_SELECT_ADDR
1209 /**********************************************/
1211 /**********************************************/
1212 #define BMA2x2_ENABLE_INTR1_PAD_FIFO_FULL_POS (2)
1213 #define BMA2x2_ENABLE_INTR1_PAD_FIFO_FULL_LEN (1)
1214 #define BMA2x2_ENABLE_INTR1_PAD_FIFO_FULL_MSK (0x04)
1215 #define BMA2x2_ENABLE_INTR1_PAD_FIFO_FULL_REG BMA2x2_INTR_DATA_SELECT_ADDR
1216 /**********************************************/
1218 /**********************************************/
1219 #define BMA2x2_ENABLE_INTR2_PAD_FIFO_FULL_POS (5)
1220 #define BMA2x2_ENABLE_INTR2_PAD_FIFO_FULL_LEN (1)
1221 #define BMA2x2_ENABLE_INTR2_PAD_FIFO_FULL_MSK (0x20)
1222 #define BMA2x2_ENABLE_INTR2_PAD_FIFO_FULL_REG BMA2x2_INTR_DATA_SELECT_ADDR
1223 /**********************************************/
1225 /**********************************************/
1226 #define BMA2x2_ENABLE_INTR2_PAD_FIFO_WM_POS (6)
1227 #define BMA2x2_ENABLE_INTR2_PAD_FIFO_WM_LEN (1)
1228 #define BMA2x2_ENABLE_INTR2_PAD_FIFO_WM_MSK (0x40)
1229 #define BMA2x2_ENABLE_INTR2_PAD_FIFO_WM_REG BMA2x2_INTR_DATA_SELECT_ADDR
1230 /**********************************************/
1232 /**********************************************/
1233 #define BMA2x2_ENABLE_INTR2_PAD_NEWDATA_POS (7)
1234 #define BMA2x2_ENABLE_INTR2_PAD_NEWDATA_LEN (1)
1235 #define BMA2x2_ENABLE_INTR2_PAD_NEWDATA_MSK (0x80)
1236 #define BMA2x2_ENABLE_INTR2_PAD_NEWDATA_REG BMA2x2_INTR_DATA_SELECT_ADDR
1237 /**********************************************/
1239 /**********************************************/
1240 #define BMA2x2_UNFILT_INTR_SOURCE_LOW_G_POS (0)
1241 #define BMA2x2_UNFILT_INTR_SOURCE_LOW_G_LEN (1)
1242 #define BMA2x2_UNFILT_INTR_SOURCE_LOW_G_MSK (0x01)
1243 #define BMA2x2_UNFILT_INTR_SOURCE_LOW_G_REG BMA2x2_INTR_SOURCE_ADDR
1244 /**********************************************/
1246 /**********************************************/
1247 #define BMA2x2_UNFILT_INTR_SOURCE_HIGH_G_POS (1)
1248 #define BMA2x2_UNFILT_INTR_SOURCE_HIGH_G_LEN (1)
1249 #define BMA2x2_UNFILT_INTR_SOURCE_HIGH_G_MSK (0x02)
1250 #define BMA2x2_UNFILT_INTR_SOURCE_HIGH_G_REG BMA2x2_INTR_SOURCE_ADDR
1251 /**********************************************/
1253 /**********************************************/
1254 #define BMA2x2_UNFILT_INTR_SOURCE_SLOPE_POS (2)
1255 #define BMA2x2_UNFILT_INTR_SOURCE_SLOPE_LEN (1)
1256 #define BMA2x2_UNFILT_INTR_SOURCE_SLOPE_MSK (0x04)
1257 #define BMA2x2_UNFILT_INTR_SOURCE_SLOPE_REG BMA2x2_INTR_SOURCE_ADDR
1258 /**********************************************/
1260 /**********************************************/
1261 #define BMA2x2_UNFILT_INTR_SOURCE_SLOW_NO_MOTION_POS (3)
1262 #define BMA2x2_UNFILT_INTR_SOURCE_SLOW_NO_MOTION_LEN (1)
1263 #define BMA2x2_UNFILT_INTR_SOURCE_SLOW_NO_MOTION_MSK (0x08)
1264 #define BMA2x2_UNFILT_INTR_SOURCE_SLOW_NO_MOTION_REG \
1265 BMA2x2_INTR_SOURCE_ADDR
1266 /**********************************************/
1268 /**********************************************/
1269 #define BMA2x2_UNFILT_INTR_SOURCE_TAP_POS (4)
1270 #define BMA2x2_UNFILT_INTR_SOURCE_TAP_LEN (1)
1271 #define BMA2x2_UNFILT_INTR_SOURCE_TAP_MSK (0x10)
1272 #define BMA2x2_UNFILT_INTR_SOURCE_TAP_REG BMA2x2_INTR_SOURCE_ADDR
1273 /**********************************************/
1275 /**********************************************/
1276 #define BMA2x2_UNFILT_INTR_SOURCE_DATA_POS (5)
1277 #define BMA2x2_UNFILT_INTR_SOURCE_DATA_LEN (1)
1278 #define BMA2x2_UNFILT_INTR_SOURCE_DATA_MSK (0x20)
1279 #define BMA2x2_UNFILT_INTR_SOURCE_DATA_REG BMA2x2_INTR_SOURCE_ADDR
1280 /****************************************************/
1282 /****************************************************/
1283 #define BMA2x2_INTR1_PAD_ACTIVE_LEVEL_POS (0)
1284 #define BMA2x2_INTR1_PAD_ACTIVE_LEVEL_LEN (1)
1285 #define BMA2x2_INTR1_PAD_ACTIVE_LEVEL_MSK (0x01)
1286 #define BMA2x2_INTR1_PAD_ACTIVE_LEVEL_REG BMA2x2_INTR_SET_ADDR
1287 
1288 #define BMA2x2_INTR2_PAD_ACTIVE_LEVEL_POS (2)
1289 #define BMA2x2_INTR2_PAD_ACTIVE_LEVEL_LEN (1)
1290 #define BMA2x2_INTR2_PAD_ACTIVE_LEVEL_MSK (0x04)
1291 #define BMA2x2_INTR2_PAD_ACTIVE_LEVEL_REG BMA2x2_INTR_SET_ADDR
1292 
1293 #define BMA2x2_INTR1_PAD_OUTPUT_TYPE_POS (1)
1294 #define BMA2x2_INTR1_PAD_OUTPUT_TYPE_LEN (1)
1295 #define BMA2x2_INTR1_PAD_OUTPUT_TYPE_MSK (0x02)
1296 #define BMA2x2_INTR1_PAD_OUTPUT_TYPE_REG BMA2x2_INTR_SET_ADDR
1297 
1298 #define BMA2x2_INTR2_PAD_OUTPUT_TYPE_POS (3)
1299 #define BMA2x2_INTR2_PAD_OUTPUT_TYPE_LEN (1)
1300 #define BMA2x2_INTR2_PAD_OUTPUT_TYPE_MSK (0x08)
1301 #define BMA2x2_INTR2_PAD_OUTPUT_TYPE_REG BMA2x2_INTR_SET_ADDR
1302 /****************************************************/
1304 /****************************************************/
1305 #define BMA2x2_LATCH_INTR_POS (0)
1306 #define BMA2x2_LATCH_INTR_LEN (4)
1307 #define BMA2x2_LATCH_INTR_MSK (0x0F)
1308 #define BMA2x2_LATCH_INTR_REG BMA2x2_INTR_CTRL_ADDR
1309 /****************************************************/
1311 /****************************************************/
1312 #define BMA2x2_RESET_INTR_POS (7)
1313 #define BMA2x2_RESET_INTR_LEN (1)
1314 #define BMA2x2_RESET_INTR_MSK (0x80)
1315 #define BMA2x2_RESET_INTR_REG BMA2x2_INTR_CTRL_ADDR
1316 /****************************************************/
1318 /****************************************************/
1319 #define BMA2x2_LOW_G_HYST_POS (0)
1320 #define BMA2x2_LOW_G_HYST_LEN (2)
1321 #define BMA2x2_LOW_G_HYST_MSK (0x03)
1322 #define BMA2x2_LOW_G_HYST_REG BMA2x2_LOW_HIGH_HYST_ADDR
1323 /****************************************************/
1325 /****************************************************/
1326 #define BMA2x2_LOW_G_INTR_MODE_POS (2)
1327 #define BMA2x2_LOW_G_INTR_MODE_LEN (1)
1328 #define BMA2x2_LOW_G_INTR_MODE_MSK (0x04)
1329 #define BMA2x2_LOW_G_INTR_MODE_REG BMA2x2_LOW_HIGH_HYST_ADDR
1330 
1331 /****************************************************/
1333 /****************************************************/
1334 #define BMA2x2_HIGH_G_HYST_POS (6)
1335 #define BMA2x2_HIGH_G_HYST_LEN (2)
1336 #define BMA2x2_HIGH_G_HYST_MSK (0xC0)
1337 #define BMA2x2_HIGH_G_HYST_REG BMA2x2_LOW_HIGH_HYST_ADDR
1338 /****************************************************/
1340 /****************************************************/
1341 #define BMA2x2_SLOPE_DURN_POS (0)
1342 #define BMA2x2_SLOPE_DURN_LEN (2)
1343 #define BMA2x2_SLOPE_DURN_MSK (0x03)
1344 #define BMA2x2_SLOPE_DURN_REG BMA2x2_SLOPE_DURN_ADDR
1345 /****************************************************/
1347 /****************************************************/
1348 #define BMA2x2_SLOW_NO_MOTION_DURN_POS (2)
1349 #define BMA2x2_SLOW_NO_MOTION_DURN_LEN (6)
1350 #define BMA2x2_SLOW_NO_MOTION_DURN_MSK (0xFC)
1351 #define BMA2x2_SLOW_NO_MOTION_DURN_REG BMA2x2_SLOPE_DURN_ADDR
1352 
1353 /****************************************************/
1355 /****************************************************/
1356 #define BMA2x2_TAP_DURN_POS (0)
1357 #define BMA2x2_TAP_DURN_LEN (3)
1358 #define BMA2x2_TAP_DURN_MSK (0x07)
1359 #define BMA2x2_TAP_DURN_REG BMA2x2_TAP_PARAM_ADDR
1360 
1361 /****************************************************/
1363 /****************************************************/
1364 #define BMA2x2_TAP_SHOCK_DURN_POS (6)
1365 #define BMA2x2_TAP_SHOCK_DURN_LEN (1)
1366 #define BMA2x2_TAP_SHOCK_DURN_MSK (0x40)
1367 #define BMA2x2_TAP_SHOCK_DURN_REG BMA2x2_TAP_PARAM_ADDR
1368 
1369 /* This advance tap interrupt only uses for the chip id 0xFB */
1370 #define BMA2x2_ADV_TAP_INTR_POS (5)
1371 #define BMA2x2_ADV_TAP_INTR_LEN (1)
1372 #define BMA2x2_ADV_TAP_INTR_MSK (0x20)
1373 #define BMA2x2_ADV_TAP_INTR_REG BMA2x2_TAP_PARAM_ADDR
1374 /****************************************************/
1376 /****************************************************/
1377 #define BMA2x2_TAP_QUIET_DURN_POS (7)
1378 #define BMA2x2_TAP_QUIET_DURN_LEN (1)
1379 #define BMA2x2_TAP_QUIET_DURN_MSK (0x80)
1380 #define BMA2x2_TAP_QUIET_DURN_REG BMA2x2_TAP_PARAM_ADDR
1381 /****************************************************/
1383 /****************************************************/
1384 #define BMA2x2_TAP_THRES_POS (0)
1385 #define BMA2x2_TAP_THRES_LEN (5)
1386 #define BMA2x2_TAP_THRES_MSK (0x1F)
1387 #define BMA2x2_TAP_THRES_REG BMA2x2_TAP_THRES_ADDR
1388 /****************************************************/
1390 /****************************************************/
1391 #define BMA2x2_TAP_SAMPLES_POS (6)
1392 #define BMA2x2_TAP_SAMPLES_LEN (2)
1393 #define BMA2x2_TAP_SAMPLES_MSK (0xC0)
1394 #define BMA2x2_TAP_SAMPLES_REG BMA2x2_TAP_THRES_ADDR
1395 /****************************************************/
1397 /****************************************************/
1398 #define BMA2x2_ORIENT_MODE_POS (0)
1399 #define BMA2x2_ORIENT_MODE_LEN (2)
1400 #define BMA2x2_ORIENT_MODE_MSK (0x03)
1401 #define BMA2x2_ORIENT_MODE_REG BMA2x2_ORIENT_PARAM_ADDR
1402 /****************************************************/
1404 /****************************************************/
1405 #define BMA2x2_ORIENT_BLOCK_POS (2)
1406 #define BMA2x2_ORIENT_BLOCK_LEN (2)
1407 #define BMA2x2_ORIENT_BLOCK_MSK (0x0C)
1408 #define BMA2x2_ORIENT_BLOCK_REG BMA2x2_ORIENT_PARAM_ADDR
1409 /****************************************************/
1411 /****************************************************/
1412 #define BMA2x2_ORIENT_HYST_POS (4)
1413 #define BMA2x2_ORIENT_HYST_LEN (3)
1414 #define BMA2x2_ORIENT_HYST_MSK (0x70)
1415 #define BMA2x2_ORIENT_HYST_REG BMA2x2_ORIENT_PARAM_ADDR
1416 /****************************************************/
1418 /****************************************************/
1419 #define BMA2x2_ORIENT_UD_ENABLE_POS (6)
1420 #define BMA2x2_ORIENT_UD_ENABLE_LEN (1)
1421 #define BMA2x2_ORIENT_UD_ENABLE_MSK (0x40)
1422 #define BMA2x2_ORIENT_UD_ENABLE_REG BMA2x2_THETA_BLOCK_ADDR
1423 
1424 /****************************************************/
1426 /****************************************************/
1427 #define BMA2x2_THETA_BLOCK_POS (0)
1428 #define BMA2x2_THETA_BLOCK_LEN (6)
1429 #define BMA2x2_THETA_BLOCK_MSK (0x3F)
1430 #define BMA2x2_THETA_BLOCK_REG BMA2x2_THETA_BLOCK_ADDR
1431 /****************************************************/
1433 /****************************************************/
1434 #define BMA2x2_THETA_FLAT_POS (0)
1435 #define BMA2x2_THETA_FLAT_LEN (6)
1436 #define BMA2x2_THETA_FLAT_MSK (0x3F)
1437 #define BMA2x2_THETA_FLAT_REG BMA2x2_THETA_FLAT_ADDR
1438 /****************************************************/
1440 /****************************************************/
1441 #define BMA2x2_FLAT_HOLD_TIME_POS (4)
1442 #define BMA2x2_FLAT_HOLD_TIME_LEN (2)
1443 #define BMA2x2_FLAT_HOLD_TIME_MSK (0x30)
1444 #define BMA2x2_FLAT_HOLD_TIME_REG BMA2x2_FLAT_HOLD_TIME_ADDR
1445 /****************************************************/
1447 /****************************************************/
1448 #define BMA2x2_FLAT_HYST_POS (0)
1449 #define BMA2x2_FLAT_HYST_LEN (3)
1450 #define BMA2x2_FLAT_HYST_MSK (0x07)
1451 #define BMA2x2_FLAT_HYST_REG BMA2x2_FLAT_HOLD_TIME_ADDR
1452 /****************************************************/
1454 /****************************************************/
1455 #define BMA2x2_FIFO_WML_TRIG_RETAIN_POS (0)
1456 #define BMA2x2_FIFO_WML_TRIG_RETAIN_LEN (6)
1457 #define BMA2x2_FIFO_WML_TRIG_RETAIN_MSK (0x3F)
1458 #define BMA2x2_FIFO_WML_TRIG_RETAIN_REG BMA2x2_FIFO_WML_TRIG
1459 /****************************************************/
1461 /****************************************************/
1462 #define BMA2x2_ENABLE_SELFTEST_POS (0)
1463 #define BMA2x2_ENABLE_SELFTEST_LEN (2)
1464 #define BMA2x2_ENABLE_SELFTEST_MSK (0x03)
1465 #define BMA2x2_ENABLE_SELFTEST_REG BMA2x2_SELFTEST_ADDR
1466 /****************************************************/
1468 /****************************************************/
1469 #define BMA2x2_NEG_SELFTEST_POS (2)
1470 #define BMA2x2_NEG_SELFTEST_LEN (1)
1471 #define BMA2x2_NEG_SELFTEST_MSK (0x04)
1472 #define BMA2x2_NEG_SELFTEST_REG BMA2x2_SELFTEST_ADDR
1473 /****************************************************/
1475 /****************************************************/
1476 #define BMA2x2_UNLOCK_EE_PROG_MODE_POS (0)
1477 #define BMA2x2_UNLOCK_EE_PROG_MODE_LEN (1)
1478 #define BMA2x2_UNLOCK_EE_PROG_MODE_MSK (0x01)
1479 #define BMA2x2_UNLOCK_EE_PROG_MODE_REG BMA2x2_EEPROM_CTRL_ADDR
1480 /**********************************************************************/
1482 /*********************************************************************/
1483 #define BMA2x2_START_EE_PROG_TRIG_POS (1)
1484 #define BMA2x2_START_EE_PROG_TRIG_LEN (1)
1485 #define BMA2x2_START_EE_PROG_TRIG_MSK (0x02)
1486 #define BMA2x2_START_EE_PROG_TRIG_REG BMA2x2_EEPROM_CTRL_ADDR
1487 /****************************************************/
1489 /****************************************************/
1490 #define BMA2x2_EE_PROG_READY_POS (2)
1491 #define BMA2x2_EE_PROG_READY_LEN (1)
1492 #define BMA2x2_EE_PROG_READY_MSK (0x04)
1493 #define BMA2x2_EE_PROG_READY_REG BMA2x2_EEPROM_CTRL_ADDR
1494 /****************************************************/
1496 /****************************************************/
1497 #define BMA2x2_UPDATE_IMAGE_POS (3)
1498 #define BMA2x2_UPDATE_IMAGE_LEN (1)
1499 #define BMA2x2_UPDATE_IMAGE_MSK (0x08)
1500 #define BMA2x2_UPDATE_IMAGE_REG BMA2x2_EEPROM_CTRL_ADDR
1501 
1502 #define BMA2x2_EE_REMAIN_POS (4)
1503 #define BMA2x2_EE_REMAIN_LEN (4)
1504 #define BMA2x2_EE_REMAIN_MSK (0xF0)
1505 #define BMA2x2_EE_REMAIN_REG BMA2x2_EEPROM_CTRL_ADDR
1506 /****************************************************/
1508 /***************************************************/
1509 #define BMA2x2_ENABLE_SPI_MODE_3_POS (0)
1510 #define BMA2x2_ENABLE_SPI_MODE_3_LEN (1)
1511 #define BMA2x2_ENABLE_SPI_MODE_3_MSK (0x01)
1512 #define BMA2x2_ENABLE_SPI_MODE_3_REG BMA2x2_SERIAL_CTRL_ADDR
1513 /****************************************************/
1515 /***************************************************/
1516 #define BMA2x2_I2C_WDT_PERIOD_POS (1)
1517 #define BMA2x2_I2C_WDT_PERIOD_LEN (1)
1518 #define BMA2x2_I2C_WDT_PERIOD_MSK (0x02)
1519 #define BMA2x2_I2C_WDT_PERIOD_REG BMA2x2_SERIAL_CTRL_ADDR
1520 /****************************************************/
1522 /***************************************************/
1523 #define BMA2x2_ENABLE_I2C_WDT_POS (2)
1524 #define BMA2x2_ENABLE_I2C_WDT_LEN (1)
1525 #define BMA2x2_ENABLE_I2C_WDT_MSK (0x04)
1526 #define BMA2x2_ENABLE_I2C_WDT_REG BMA2x2_SERIAL_CTRL_ADDR
1527 /****************************************************/
1529 /***************************************************/
1530 #define BMA2x2_UNLOCK_EE_WRITE_TRIM_POS (4)
1531 #define BMA2x2_UNLOCK_EE_WRITE_TRIM_LEN (4)
1532 #define BMA2x2_UNLOCK_EE_WRITE_TRIM_MSK (0xF0)
1533 #define BMA2x2_UNLOCK_EE_WRITE_TRIM_REG BMA2x2_CTRL_UNLOCK_REG
1534 /******************************************************************/
1536 /*****************************************************************/
1537 #define BMA2x2_ENABLE_SLOW_COMP_X_POS (0)
1538 #define BMA2x2_ENABLE_SLOW_COMP_X_LEN (1)
1539 #define BMA2x2_ENABLE_SLOW_COMP_X_MSK (0x01)
1540 #define BMA2x2_ENABLE_SLOW_COMP_X_REG BMA2x2_OFFSET_CTRL_ADDR
1541 
1542 #define BMA2x2_ENABLE_SLOW_COMP_Y_POS (1)
1543 #define BMA2x2_ENABLE_SLOW_COMP_Y_LEN (1)
1544 #define BMA2x2_ENABLE_SLOW_COMP_Y_MSK (0x02)
1545 #define BMA2x2_ENABLE_SLOW_COMP_Y_REG BMA2x2_OFFSET_CTRL_ADDR
1546 
1547 #define BMA2x2_ENABLE_SLOW_COMP_Z_POS (2)
1548 #define BMA2x2_ENABLE_SLOW_COMP_Z_LEN (1)
1549 #define BMA2x2_ENABLE_SLOW_COMP_Z_MSK (0x04)
1550 #define BMA2x2_ENABLE_SLOW_COMP_Z_REG BMA2x2_OFFSET_CTRL_ADDR
1551 /****************************************************/
1553 /***************************************************/
1554 #define BMA2x2_FAST_CAL_RDY_STAT_POS (4)
1555 #define BMA2x2_FAST_CAL_RDY_STAT_LEN (1)
1556 #define BMA2x2_FAST_CAL_RDY_STAT_MSK (0x10)
1557 #define BMA2x2_FAST_CAL_RDY_STAT_REG BMA2x2_OFFSET_CTRL_ADDR
1558 /****************************************************/
1560 /***************************************************/
1561 #define BMA2x2_CAL_TRIGGER_POS (5)
1562 #define BMA2x2_CAL_TRIGGER_LEN (2)
1563 #define BMA2x2_CAL_TRIGGER_MSK (0x60)
1564 #define BMA2x2_CAL_TRIGGER_REG BMA2x2_OFFSET_CTRL_ADDR
1565 /****************************************************/
1567 /***************************************************/
1568 #define BMA2x2_RST_OFFSET_POS (7)
1569 #define BMA2x2_RST_OFFSET_LEN (1)
1570 #define BMA2x2_RST_OFFSET_MSK (0x80)
1571 #define BMA2x2_RST_OFFSET_REG BMA2x2_OFFSET_CTRL_ADDR
1572 /****************************************************/
1574 /***************************************************/
1575 #define BMA2x2_COMP_CUTOFF_POS (0)
1576 #define BMA2x2_COMP_CUTOFF_LEN (1)
1577 #define BMA2x2_COMP_CUTOFF_MSK (0x01)
1578 #define BMA2x2_COMP_CUTOFF_REG BMA2x2_OFFSET_PARAMS_ADDR
1579 /****************************************************/
1581 /***************************************************/
1582 #define BMA2x2_COMP_TARGET_OFFSET_X_POS (1)
1583 #define BMA2x2_COMP_TARGET_OFFSET_X_LEN (2)
1584 #define BMA2x2_COMP_TARGET_OFFSET_X_MSK (0x06)
1585 #define BMA2x2_COMP_TARGET_OFFSET_X_REG BMA2x2_OFFSET_PARAMS_ADDR
1586 
1587 #define BMA2x2_COMP_TARGET_OFFSET_Y_POS (3)
1588 #define BMA2x2_COMP_TARGET_OFFSET_Y_LEN (2)
1589 #define BMA2x2_COMP_TARGET_OFFSET_Y_MSK (0x18)
1590 #define BMA2x2_COMP_TARGET_OFFSET_Y_REG BMA2x2_OFFSET_PARAMS_ADDR
1591 
1592 #define BMA2x2_COMP_TARGET_OFFSET_Z_POS (5)
1593 #define BMA2x2_COMP_TARGET_OFFSET_Z_LEN (2)
1594 #define BMA2x2_COMP_TARGET_OFFSET_Z_MSK (0x60)
1595 #define BMA2x2_COMP_TARGET_OFFSET_Z_REG BMA2x2_OFFSET_PARAMS_ADDR
1596 /****************************************************/
1598 /***************************************************/
1599 #define BMA2x2_FIFO_DATA_SELECT_POS (0)
1600 #define BMA2x2_FIFO_DATA_SELECT_LEN (2)
1601 #define BMA2x2_FIFO_DATA_SELECT_MSK (0x03)
1602 #define BMA2x2_FIFO_DATA_SELECT_REG BMA2x2_FIFO_MODE_ADDR
1603 /****************************************************/
1605 /***************************************************/
1606 #define BMA2x2_FIFO_MODE_POS (6)
1607 #define BMA2x2_FIFO_MODE_LEN (2)
1608 #define BMA2x2_FIFO_MODE_MSK (0xC0)
1609 #define BMA2x2_FIFO_MODE_REG BMA2x2_FIFO_MODE_ADDR
1610 
1611 /****************************************************/
1613 /***************************************************/
1614 #define BMA2x2_GET_BITSLICE(regvar, bitname)\
1615 ((regvar & bitname##_MSK) >> bitname##_POS)
1616 
1617 
1618 #define BMA2x2_SET_BITSLICE(regvar, bitname, val)\
1619 ((regvar & ~bitname##_MSK) | ((val<<bitname##_POS)&bitname##_MSK))
1620 
1621 /****************************************************/
1623 /***************************************************/
1624 /****************************************************/
1626 /***************************************************/
1627 /* Definitions used for accel resolution bit shifting*/
1628 #define BMA2x2_14_BIT_SHIFT (0xFC)
1629 
1630 #define BMA2x2_10_BIT_SHIFT (0xC0)
1631 
1632 #define BMA2x2_12_BIT_SHIFT (0xF0)
1633 
1634 #define BANDWIDTH_DEFINE (0xFB)
1635 
1637 /****************************************************/
1639 /***************************************************/
1640 #define INTR_ENABLE (0X01)
1641 
1642 #define INTR_DISABLE (0x00)
1643 
1645 /****************************************************/
1647 /***************************************************/
1648 #define OPEN_DRAIN (0x01)
1649 
1650 #define PUSS_PULL (0x01)
1651 
1653 /****************************************************/
1655 /***************************************************/
1656 #define ACTIVE_LOW (0x00)
1657 
1658 #define ACTIVE_HIGH (0x01)
1659 
1661 /****************************************************/
1663 /***************************************************/
1664 #define BMA2x2_STAT1 (0)
1665 
1666 #define BMA2x2_STAT2 (1)
1667 
1668 #define BMA2x2_STAT3 (2)
1669 
1670 #define BMA2x2_STAT4 (3)
1671 
1672 #define BMA2x2_STAT5 (4)
1673 
1675 /****************************************************/
1677 /***************************************************/
1678 #define BMA2x2_RANGE_2G (3)
1679 
1680 #define BMA2x2_RANGE_4G (5)
1681 
1682 #define BMA2x2_RANGE_8G (8)
1683 
1684 #define BMA2x2_RANGE_16G (12)
1685 
1688 #define BMA2x2_BW_7_81HZ (0x08)
1689 
1690 #define BMA2x2_BW_15_63HZ (0x09)
1691 
1692 #define BMA2x2_BW_31_25HZ (0x0A)
1693 
1694 #define BMA2x2_BW_62_50HZ (0x0B)
1695 
1696 #define BMA2x2_BW_125HZ (0x0C)
1697 
1698 #define BMA2x2_BW_250HZ (0x0D)
1699 
1700 #define BMA2x2_BW_500HZ (0x0E)
1701 
1702 #define BMA2x2_BW_1000HZ (0x0F)
1703 
1705 /******************************************/
1707 /******************************************/
1708 #define BMA2x2_SLEEP_DURN_0_5MS (0x05)
1709 /* sets sleep duration to 0.5 ms */
1710 #define BMA2x2_SLEEP_DURN_1MS (0x06)
1711 /* sets sleep duration to 1 ms */
1712 #define BMA2x2_SLEEP_DURN_2MS (0x07)
1713 /* sets sleep duration to 2 ms */
1714 #define BMA2x2_SLEEP_DURN_4MS (0x08)
1715 /* sets sleep duration to 4 ms */
1716 #define BMA2x2_SLEEP_DURN_6MS (0x09)
1717 /* sets sleep duration to 6 ms*/
1718 #define BMA2x2_SLEEP_DURN_10MS (0x0A)
1719 /* sets sleep duration to 10 ms */
1720 #define BMA2x2_SLEEP_DURN_25MS (0x0B)
1721 /* sets sleep duration to 25 ms */
1722 #define BMA2x2_SLEEP_DURN_50MS (0x0C)
1723 /* sets sleep duration to 50 ms */
1724 #define BMA2x2_SLEEP_DURN_100MS (0x0D)
1725 /* sets sleep duration to 100 ms */
1726 #define BMA2x2_SLEEP_DURN_500MS (0x0E)
1727 /* sets sleep duration to 500 ms */
1728 #define BMA2x2_SLEEP_DURN_1S (0x0F)
1729 /* sets sleep duration to 1 s */
1730 
1731 /******************************************/
1733 /******************************************/
1734 #define BMA2x2_LATCH_DURN_NON_LATCH (0x00)
1735 /* sets LATCH duration to NON LATCH */
1736 #define BMA2x2_LATCH_DURN_250MS (0x01)
1737 /* sets LATCH duration to 250 ms */
1738 #define BMA2x2_LATCH_DURN_500MS (0x02)
1739 /* sets LATCH duration to 500 ms */
1740 #define BMA2x2_LATCH_DURN_1S (0x03)
1741  /* sets LATCH duration to 1 s */
1742 #define BMA2x2_LATCH_DURN_2S (0x04)
1743  /* sets LATCH duration to 2 s*/
1744 #define BMA2x2_LATCH_DURN_4S (0x05)
1745  /* sets LATCH duration to 4 s */
1746 #define BMA2x2_LATCH_DURN_8S (0x06)
1747  /* sets LATCH duration to 8 s */
1748 #define BMA2x2_LATCH_DURN_LATCH (0x07)
1749  /* sets LATCH duration to LATCH */
1750 #define BMA2x2_LATCH_DURN_NON_LATCH1 (0x08)
1751  /* sets LATCH duration to NON LATCH1 */
1752 #define BMA2x2_LATCH_DURN_250US (0x09)
1753  /* sets LATCH duration to 250 Us */
1754 #define BMA2x2_LATCH_DURN_500US (0x0A)
1755  /* sets LATCH duration to 500 Us */
1756 #define BMA2x2_LATCH_DURN_1MS (0x0B)
1757  /* sets LATCH duration to 1 Ms */
1758 #define BMA2x2_LATCH_DURN_12_5MS (0x0C)
1759 /* sets LATCH duration to 12.5 Ms */
1760 #define BMA2x2_LATCH_DURN_25MS (0x0D)
1761 /* sets LATCH duration to 25 Ms */
1762 #define BMA2x2_LATCH_DURN_50MS (0x0E)
1763  /* sets LATCH duration to 50 Ms */
1764 #define BMA2x2_LATCH_DURN_LATCH1 (0x0F)
1765 /* sets LATCH duration to LATCH*/
1766 
1767 /******************************************/
1769 /******************************************/
1770 #define BMA2x2_MODE_NORMAL (0)
1771 #define BMA2x2_MODE_LOWPOWER1 (1)
1772 #define BMA2x2_MODE_SUSPEND (2)
1773 #define BMA2x2_MODE_DEEP_SUSPEND (3)
1774 #define BMA2x2_MODE_LOWPOWER2 (4)
1775 #define BMA2x2_MODE_STANDBY (5)
1776 
1777 /******************************************/
1779 /******************************************/
1780 #define BMA2x2_X_AXIS (0)
1781 
1782 #define BMA2x2_Y_AXIS (1)
1783 
1784 #define BMA2x2_Z_AXIS (2)
1785 
1787 /******************************************/
1789 /******************************************/
1790 #define BMA2x2_LOW_G_INTR (0)
1791 
1792 #define BMA2x2_HIGH_G_X_INTR (1)
1793 
1794 #define BMA2x2_HIGH_G_Y_INTR (2)
1795 
1796 #define BMA2x2_HIGH_G_Z_INTR (3)
1797 
1798 #define BMA2x2_DATA_ENABLE (4)
1799 
1800 #define BMA2x2_SLOPE_X_INTR (5)
1801 
1802 #define BMA2x2_SLOPE_Y_INTR (6)
1803 
1804 #define BMA2x2_SLOPE_Z_INTR (7)
1805 
1806 #define BMA2x2_SINGLE_TAP_INTR (8)
1807 
1808 #define BMA2x2_DOUBLE_TAP_INTR (9)
1809 
1810 #define BMA2x2_ORIENT_INTR (10)
1811 
1812 #define BMA2x2_FLAT_INTR (11)
1813 
1814 #define BMA2x2_FIFO_FULL_INTR (12)
1815 
1816 #define BMA2x2_FIFO_WM_INTR (13)
1817 
1819 /******************************************/
1821 /******************************************/
1822 #define BMA2x2_INTR1_LOW_G (0)
1823 
1824 #define BMA2x2_INTR2_LOW_G (1)
1825 
1826 #define BMA2x2_INTR1_HIGH_G (0)
1827 
1828 #define BMA2x2_INTR2_HIGH_G (1)
1829 
1830 #define BMA2x2_INTR1_SLOPE (0)
1831 
1832 #define BMA2x2_INTR2_SLOPE (1)
1833 
1834 #define BMA2x2_INTR1_SLOW_NO_MOTION (0)
1835 
1836 #define BMA2x2_INTR2_SLOW_NO_MOTION (1)
1837 
1838 #define BMA2x2_INTR1_DOUBLE_TAP (0)
1839 
1840 #define BMA2x2_INTR2_DOUBLE_TAP (1)
1841 
1842 #define BMA2x2_INTR1_SINGLE_TAP (0)
1843 
1844 #define BMA2x2_INTR2_SINGLE_TAP (1)
1845 
1846 #define BMA2x2_INTR1_ORIENT (0)
1847 
1848 #define BMA2x2_INTR2_ORIENT (1)
1849 
1850 #define BMA2x2_INTR1_FLAT (0)
1851 
1852 #define BMA2x2_INTR2_FLAT (1)
1853 
1854 #define BMA2x2_INTR1_NEWDATA (0)
1855 
1856 #define BMA2x2_INTR2_NEWDATA (1)
1857 
1858 #define BMA2x2_INTR1_FIFO_WM (0)
1859 
1860 #define BMA2x2_INTR2_FIFO_WM (1)
1861 
1862 #define BMA2x2_INTR1_FIFO_FULL (0)
1863 
1864 #define BMA2x2_INTR2_FIFO_FULL (1)
1865 
1867 /******************************************/
1869 /******************************************/
1870 #define BMA2x2_SOURCE_LOW_G (0)
1871 #define BMA2x2_SOURCE_HIGH_G (1)
1872 #define BMA2x2_SOURCE_SLOPE (2)
1873 #define BMA2x2_SOURCE_SLOW_NO_MOTION (3)
1874 #define BMA2x2_SOURCE_TAP (4)
1875 #define BMA2x2_SOURCE_DATA (5)
1876 
1877 #define BMA2x2_INTR1_OUTPUT (0)
1878 #define BMA2x2_INTR2_OUTPUT (1)
1879 #define BMA2x2_INTR1_LEVEL (0)
1880 #define BMA2x2_INTR2_LEVEL (1)
1881 
1882 /******************************************/
1884 /******************************************/
1885 #define BMA2x2_LOW_DURN (0)
1886 #define BMA2x2_HIGH_DURN (1)
1887 #define BMA2x2_SLOPE_DURN (2)
1888 #define BMA2x2_SLOW_NO_MOTION_DURN (3)
1889 
1890 /******************************************/
1892 /******************************************/
1893 #define BMA2x2_LOW_THRES (0)
1894 #define BMA2x2_HIGH_THRES (1)
1895 #define BMA2x2_SLOPE_THRES (2)
1896 #define BMA2x2_SLOW_NO_MOTION_THRES (3)
1897 
1898 
1899 #define BMA2x2_LOW_G_HYST (0)
1900 #define BMA2x2_HIGH_G_HYST (1)
1901 
1902 #define BMA2x2_ORIENT_THETA (0)
1903 #define BMA2x2_FLAT_THETA (1)
1904 
1905 #define BMA2x2_I2C_SELECT (0)
1906 #define BMA2x2_I2C_ENABLE (1)
1907 /******************************************/
1909 /******************************************/
1910 #define BMA2x2_SLOW_COMP_X (0)
1911 #define BMA2x2_SLOW_COMP_Y (1)
1912 #define BMA2x2_SLOW_COMP_Z (2)
1913 /******************************************/
1915 /******************************************/
1916 #define BMA2x2_CUT_OFF (0)
1917 #define BMA2x2_OFFSET_TRIGGER_X (1)
1918 #define BMA2x2_OFFSET_TRIGGER_Y (2)
1919 #define BMA2x2_OFFSET_TRIGGER_Z (3)
1920 /******************************************/
1922 /******************************************/
1923 #define BMA2x2_GP0 (0)
1924 #define BMA2x2_GP1 (1)
1925 /******************************************/
1927 /******************************************/
1928 #define BMA2x2_SLOW_NO_MOTION_ENABLE_X (0)
1929 #define BMA2x2_SLOW_NO_MOTION_ENABLE_Y (1)
1930 #define BMA2x2_SLOW_NO_MOTION_ENABLE_Z (2)
1931 #define BMA2x2_SLOW_NO_MOTION_ENABLE_SELECT (3)
1932 /******************************************/
1934 /******************************************/
1935 #define BMA2x2_WAKE_UP_DURN_20MS (0)
1936 #define BMA2x2_WAKE_UP_DURN_80MS (1)
1937 #define BMA2x2_WAKE_UP_DURN_320MS (2)
1938 #define BMA2x2_WAKE_UP_DURN_2560MS (3)
1939 
1940 
1941 /* LG/HG thresholds are in LSB and depend on RANGE setting */
1942 /* no range check on threshold calculation */
1943 
1944 #define BMA2x2_SELFTEST0_ON (1)
1945 #define BMA2x2_SELFTEST1_ON (2)
1946 
1947 #define BMA2x2_EE_W_OFF (0)
1948 #define BMA2x2_EE_W_ON (1)
1949 /******************************************/
1951 /******************************************/
1952 #define BMA2x2_RESOLUTION_12_BIT (0)
1953 #define BMA2x2_RESOLUTION_10_BIT (1)
1954 #define BMA2x2_RESOLUTION_14_BIT (3)
1955 
1956 /******************************************/
1958 /******************************************/
1959 #define BMA2x2 (0x16)
1960 #define BMA280 (0x17)
1961 #define BMA222E (0x18)
1962 #define BMA250E (0x19)
1963 /******************************************/
1965 /******************************************/
1966 #define LOW_G_SINGLE_AXIS_MODE (0x00)
1967 #define LOW_G_SUMMING_MODE (0x01)
1968 /******************************************/
1970 /******************************************/
1971 #define TAP_DURN_50_MS (0x00)
1972 #define TAP_DURN_100_MS (0x01)
1973 #define TAP_DURN_150_MS (0x02)
1974 #define TAP_DURN_200_MS (0x03)
1975 #define TAP_DURN_250_MS (0x04)
1976 #define TAP_DURN_375_MS (0x05)
1977 #define TAP_DURN_500_MS (0x06)
1978 #define TAP_DURN_700_MS (0x07)
1979 /******************************************/
1981 /******************************************/
1982 #define TAP_SHOCK_50_MS (0x00)
1983 #define TAP_SHOCK_75_MS (0x01)
1984 /******************************************/
1986 /******************************************/
1987 #define TAP_QUIET_30_MS (0x00)
1988 #define TAP_QUIET_20_MS (0x01)
1989 /****************************************************/
1991 /***************************************************/
1992 #define BMA2x2_ACCEL_DATA_SIZE (2)
1993 #define BMA2x2_ACCEL_XYZ_DATA_SIZE (6)
1994 #define BMA2x2_ACCEL_XYZ_TEMP_DATA_SIZE (7)
1995 /****************************************************/
1997 /***************************************************/
1998 
1999 #define BMA2x2_SENSOR_DATA_ACCEL_LSB (0)
2000 #define BMA2x2_SENSOR_DATA_ACCEL_MSB (1)
2001 
2002 #define BMA2x2_SENSOR_DATA_XYZ_X_LSB (0)
2003 #define BMA2x2_SENSOR_DATA_XYZ_X_MSB (1)
2004 #define BMA2x2_SENSOR_DATA_XYZ_Y_LSB (2)
2005 #define BMA2x2_SENSOR_DATA_XYZ_Y_MSB (3)
2006 #define BMA2x2_SENSOR_DATA_XYZ_Z_LSB (4)
2007 #define BMA2x2_SENSOR_DATA_XYZ_Z_MSB (5)
2008 #define BMA2x2_SENSOR_DATA_TEMP (6)
2009 
2010 #define BMA2x2_RESOLUTION_12_MASK (0xF0)
2011 #define BMA2x2_RESOLUTION_10_MASK (0xC0)
2012 #define BMA2x2_RESOLUTION_14_MASK (0xFC)
2013 
2014 #define BMA2x2_POWER_MODE_HEX_E_ZERO_MASK (0xE0)
2015 #define BMA2x2_POWER_MODE_HEX_4_ZERO_MASK (0x40)
2016 #define BMA2x2_POWER_MODE_HEX_ZERO_ZERO_MASK (0x00)
2017 #define BMA2x2_POWER_MODE_HEX_ZERO_ONE_MASK (0x01)
2018 #define BMA2x2_POWER_MODE_HEX_ZERO_TWO_MASK (0x02)
2019 #define BMA2x2_POWER_MODE_HEX_ZERO_FOUR_MASK (0x04)
2020 #define BMA2x2_POWER_MODE_HEX_ZERO_SIX_MASK (0x06)
2021 
2028 #define BMA2x2_LOW_THRES_IN_G(gthres, range) ((256 * gthres) / range)
2029 
2036 #define BMA2x2_HIGH_THRES_IN_G(gthres, range) ((256 * gthres) / range)
2037 
2044 #define BMA2x2_LOW_HYST_IN_G(ghyst, range) ((32 * ghyst) / range)
2045 
2052 #define BMA2x2_HIGH_HYST_IN_G(ghyst, range) ((32 * ghyst) / range)
2053 
2054 
2062 #define BMA2x2_SLOPE_THRES_IN_G(gthres, range) ((128 * gthres) / range)
2063 /******************************************/
2065 /******************************************/
2066 /******************************************/
2068 /******************************************/
2086 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_burst_read(u8 addr_u8,
2087 u8 *data_u8, u32 len_u32);
2088 /******************************************/
2090 /******************************************/
2114 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_init(struct bma2x2_t *bma2x2);
2133 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_write_reg(u8 adr_u8,
2134 u8 *data_u8, u8 len_u8);
2152 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_reg(u8 adr_u8,
2153 u8 *data_u8, u8 len_u8);
2154 /******************************************/
2156 /******************************************/
2177 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_accel_x(s16 *accel_x_s16);
2194 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_accel_eight_resolution_x(
2195 s8 *accel_x_s8);
2215 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_accel_y(s16 *accel_y_s16);
2233 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_accel_eight_resolution_y(
2234 s8 *accel_y_s8);
2254 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_accel_z(s16 *accel_z_s16);
2272 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_accel_eight_resolution_z(
2273 s8 *accel_z_s8);
2291 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_accel_xyz(
2292 struct bma2x2_accel_data *accel);
2311 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_accel_eight_resolution_xyz(
2312 struct bma2x2_accel_eight_resolution *accel);
2313 /******************************************/
2315 /******************************************/
2331 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_tap_stat(
2332 u8 *stat_tap_u8);
2348 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_orient_stat(
2349 u8 *stat_orient_u8);
2364 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_fifo_stat(
2365 u8 *stat_fifo_u8);
2381 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_fifo_frame_count(
2382 u8 *frame_count_u8);
2398 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_fifo_overrun(
2399 u8 *fifo_overrun_u8);
2400 /******************************************/
2402 /******************************************/
2419 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_stat(
2420 u8 *intr_stat_u8);
2442 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_range(u8 *range_u8);
2464 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_range(u8 range_u8);
2465 /******************************************/
2467 /******************************************/
2493 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_bw(u8 *bw_u8);
2519 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_bw(u8 bw_u8);
2520 /******************************************/
2522 /******************************************/
2548 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_power_mode(
2549 u8 *power_mode_u8);
2575 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_power_mode(u8 power_mode_u8);
2601 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_mode_value(u8 power_mode_u8);
2602 /******************************************/
2604 /******************************************/
2636 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_sleep_durn(u8 *sleep_durn_u8);
2668 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_sleep_durn(u8 sleep_durn_u8);
2689 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_sleep_timer_mode(
2690 u8 *sleep_timer_u8);
2711 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_sleep_timer_mode(u8 sleep_timer_u8);
2712 /******************************************/
2714 /******************************************/
2732 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_high_bw(u8 *high_bw_u8);
2750 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_high_bw(u8 high_bw_u8);
2769 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_shadow_dis(u8 *shadow_dis_u8);
2788 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_shadow_dis(u8 shadow_dis_u8);
2789 /******************************************/
2791 /******************************************/
2805 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_soft_rst(void);
2822 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_update_image(void);
2823 /******************************************/
2825 /******************************************/
2870 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_enable(u8 intr_type_u8,
2871 u8 *value_u8);
2916 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_enable(u8 intr_type_u8,
2917 u8 value_u8);
2938 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_fifo_full(u8 *fifo_full_u8);
2959 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_fifo_full(u8 fifo_full_u8);
2982 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_fifo_wm(u8 *fifo_wm_u8);
3005 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_fifo_wm(u8 fifo_wm_u8);
3034 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_slow_no_motion(u8 channel_u8,
3035 u8 *slow_no_motion_u8);
3063 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_slow_no_motion(u8 channel_u8,
3064 u8 slow_no_motion_u8);
3094 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_low_g(u8 channel_u8,
3095 u8 *intr_low_g_u8);
3125 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_low_g(u8 channel_u8,
3126 u8 intr_low_u8);
3153 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_high_g(u8 channel_u8,
3154 u8 *intr_high_g_u8);
3181 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_high_g(u8 channel_u8,
3182 u8 intr_high_g_u8);
3211 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_slope(u8 channel_u8,
3212 u8 *intr_slope_u8);
3241 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_slope(u8 channel_u8,
3242 u8 intr_slope_u8);
3272 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_slow_no_motion(u8 channel_u8,
3273 u8 *intr_slow_no_motion_u8);
3303 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_slow_no_motion(u8 channel_u8,
3304 u8 intr_slow_no_motion_u8);
3333 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_double_tap(u8 channel_u8,
3334 u8 *intr_double_tap_u8);
3363 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_double_tap(u8 channel_u8,
3364 u8 intr_double_tap_u8);
3392 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_single_tap(u8 channel_u8,
3393 u8 *intr_single_tap_u8);
3421 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_single_tap(u8 channel_u8,
3422 u8 intr_single_tap_u8);
3449 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_orient(u8 channel_u8,
3450 u8 *intr_orient_u8);
3477 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_orient(u8 channel_u8,
3478 u8 intr_orient_u8);
3507 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_flat(u8 channel_u8,
3508 u8 *intr_flat_u8);
3537 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_flat(u8 channel_u8,
3538 u8 intr_flat_u8);
3566 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_new_data(u8 channel_u8,
3567 u8 *intr_newdata_u8);
3595 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_new_data(u8 channel_u8,
3596 u8 intr_newdata_u8);
3597 /******************************************/
3599 /******************************************/
3618 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr1_fifo_wm(u8 *intr1_fifo_wm_u8);
3637 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr1_fifo_wm(u8 intr1_fifo_wm_u8);
3656 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr2_fifo_wm(u8 *intr2_fifo_wm_u8);
3675 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr2_fifo_wm(u8 intr2_fifo_wm_u8);
3696 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr1_fifo_full(
3697 u8 *intr1_fifo_full_u8);
3718 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr1_fifo_full(u8 intr1_fifo_full_u8);
3740 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr2_fifo_full(
3741 u8 *intr2_fifo_full_u8);
3763 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr2_fifo_full(u8 intr2_fifo_full_u8);
3764 /******************************************/
3766 /******************************************/
3796 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_source(u8 channel_u8,
3797 u8 *intr_source_u8);
3827 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_source(u8 channel_u8,
3828 u8 intr_source_u8);
3829 /******************************************/
3831 /******************************************/
3858 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_output_type(u8 channel_u8,
3859 u8 *intr_output_type_u8);
3886 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_output_type(u8 channel_u8,
3887 u8 intr_output_type_u8);
3913 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_level(u8 channel_u8,
3914 u8 *intr_level_u8);
3940 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_level(u8 channel_u8,
3941 u8 intr_level_u8);
3942 /******************************************/
3944 /******************************************/
3964 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_rst_intr(u8 rst_intr_u8);
3965 /******************************************/
3967 /******************************************/
4000 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_latch_intr(u8 *latch_intr_u8);
4033 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_latch_intr(u8 latch_intr_u8);
4034 /******************************************/
4036 /******************************************/
4076 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_durn(u8 channel_u8,
4077 u8 *durn_u8);
4117 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_durn(u8 channel_u8,
4118 u8 durn_u8);
4119 /******************************************/
4121 /******************************************/
4182 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_thres(u8 channel_u8,
4183 u8 *thres_u8);
4244 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_thres(u8 channel_u8,
4245 u8 thres_u8);
4246 /******************************************/
4248 /******************************************/
4281 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_low_high_g_hyst(u8 channel_u8,
4282 u8 *hyst_u8);
4315 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_low_high_g_hyst(u8 channel_u8,
4316 u8 hyst_u8);
4317 /******************************************/
4319 /******************************************/
4338 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_low_g_mode(u8 *low_g_mode_u8);
4357 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_low_g_mode(u8 low_g_mode_u8);
4358 /******************************************/
4360 /******************************************/
4386 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_tap_durn(u8 *tap_durn_u8);
4412 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_tap_durn(u8 tap_durn_u8);
4413 /******************************************/
4415 /******************************************/
4435 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_tap_shock(u8 *tap_shock_u8);
4455 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_tap_shock(u8 tap_shock_u8);
4456 /******************************************/
4458 /******************************************/
4477 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_tap_quiet(u8 *tap_quiet_u8);
4496 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_tap_quiet(u8 tap_quiet_u8);
4497 /******************************************/
4499 /******************************************/
4523 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_tap_thres(u8 *tap_thres_u8);
4547 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_tap_thres(u8 tap_thres_u8);
4548 /******************************************/
4550 /******************************************/
4572 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_tap_sample(u8 *tap_sample_u8);
4594 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_tap_sample(u8 tap_sample_u8);
4595 /******************************************/
4597 /******************************************/
4620 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_orient_mode(u8 *orient_mode_u8);
4643 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_orient_mode(u8 orient_mode_u8);
4644 /******************************************/
4646 /******************************************/
4674 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_orient_block(
4675 u8 *orient_block_u8);
4703 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_orient_block(u8 orient_block_u8);
4704 /******************************************/
4706 /******************************************/
4723 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_orient_hyst(u8 *orient_hyst_u8);
4740 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_orient_hyst(u8 orient_hyst_u8);
4741 /******************************************/
4743 /******************************************/
4768 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_theta(u8 channel_u8,
4769 u8 *theta_u8);
4794 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_theta(u8 channel_u8,
4795 u8 theta_u8);
4796 /******************************************/
4798 /******************************************/
4818 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_orient_enable(
4819 u8 *orient_enable_u8);
4839 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_orient_enable(u8 orient_enable_u8);
4840 /******************************************/
4842 /******************************************/
4861 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_flat_hyst(u8 *flat_hyst_u8);
4880 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_flat_hyst(u8 flat_hyst_u8);
4881 /******************************************/
4883 /******************************************/
4906 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_flat_hold_time(
4907 u8 *flat_hold_time_u8);
4930 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_flat_hold_time(
4931 u8 flat_hold_time_u8);
4932 /******************************************/
4934 /******************************************/
4952 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_fifo_wml_trig(
4953 u8 *fifo_wml_trig);
4971 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_fifo_wml_trig(
4972 u8 fifo_wml_trig);
4973 /******************************************/
4975 /******************************************/
4997 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_selftest_axis(
4998 u8 *selftest_axis_u8);
5020 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_selftest_axis(
5021 u8 selftest_axis_u8);
5041 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_selftest_sign(
5042 u8 *selftest_sign_u8);
5062 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_selftest_sign(
5063 u8 selftest_sign_u8);
5064 /******************************************/
5066 /******************************************/
5084 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_nvmprog_mode(
5085 u8 *nvmprog_mode_u8);
5103 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_nvmprog_mode(u8 nvmprog_mode_u8);
5124 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_nvprog_trig(u8 nvprog_trig_u8);
5144 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_nvmprog_ready(u8 *nvprog_ready_u8);
5164 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_nvmprog_remain(u8 *nvprog_remain_u8);
5165 /******************************************/
5167 /******************************************/
5188 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_spi3(u8 *spi3_u8);
5209 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_spi3(u8 spi3_u8);
5241 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_i2c_wdt(u8 channel_u8,
5242 u8 *i2c_wdt_u8);
5274 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_i2c_wdt(u8 channel_u8,
5275 u8 i2c_wdt_u8);
5276 /******************************************/
5278 /******************************************/
5308 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_slow_comp(u8 channel_u8,
5309 u8 *slow_comp_u8);
5339 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_slow_comp(u8 channel_u8,
5340 u8 slow_comp_u8);
5359 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_cal_rdy(u8 *cal_rdy_u8);
5378 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_cal_trigger(u8 cal_trigger_u8);
5396 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_offset_rst(u8 offset_rst_u8);
5435 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_offset_target(u8 channel_u8,
5436 u8 *offset_u8);
5475 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_offset_target(u8 channel_u8,
5476 u8 offset_u8);
5502 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_offset(u8 channel_u8,
5503 s8 *offset_u8);
5529 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_offset(u8 channel_u8,
5530 s8 offset_u8);
5531 /******************************************/
5533 /******************************************/
5555 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_fifo_mode(u8 *fifo_mode_u8);
5577 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_fifo_mode(u8 fifo_mode_u8);
5599 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_fifo_data_select(
5600 u8 *fifo_data_select_u8);
5622 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_fifo_data_select(
5623 u8 fifo_data_select_u8);
5639 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_fifo_data_output_reg(
5640 u8 *output_reg_u8);
5641 /******************************************/
5643 /******************************************/
5660 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_temp(s8 *temp_s8);
5661 /******************************************/
5663 /******************************************/
5679 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_accel_xyzt(
5680 struct bma2x2_accel_data_temp *accel);
5696 BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_accel_eight_resolution_xyzt(
5697 struct bma2x2_accel_eight_resolution_temp *accel);
5698 #endif
5699 
bma2x2_get_shadow_dis
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_shadow_dis(u8 *shadow_dis_u8)
This API is used to get shadow dis in the register 0x13 bit 6.
Definition: bma2x2.c:1927
bma2x2_get_intr_low_g
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_low_g(u8 channel_u8, u8 *intr_low_g_u8)
This API is used to get the interrupt enable of low_g interrupt in the register 0x19 and 0x1B...
Definition: bma2x2.c:2760
bma2x2_get_fifo_mode
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_fifo_mode(u8 *fifo_mode_u8)
This API is used to get the status of fifo (fifo_mode) in the register 0x3E bit 6 and 7...
Definition: bma2x2.c:8158
bma2x2_set_shadow_dis
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_shadow_dis(u8 shadow_dis_u8)
This API is used to set shadow dis in the register 0x13 bit 6.
Definition: bma2x2.c:1965
bma2x2_read_accel_eight_resolution_xyzt
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_accel_eight_resolution_xyzt(struct bma2x2_accel_eight_resolution_temp *accel)
This API reads accelerometer data X,Y,Z values and temperature data from location 0x02 to 0x08...
Definition: bma2x2.c:8555
bma2x2_set_intr1_fifo_full
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr1_fifo_full(u8 intr1_fifo_full_u8)
This API is used to set the fifo full interrupt1 in the register 0x1A bit 2.
Definition: bma2x2.c:4223
bma2x2_set_fifo_wml_trig
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_fifo_wml_trig(u8 fifo_wml_trig)
This API is used to set the fifo water mark level trigger in the register 0x30 bit from 0 to 5...
Definition: bma2x2.c:6862
bma2x2_get_theta
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_theta(u8 channel_u8, u8 *theta_u8)
This API is used to get the theta value of orient and flat interrupts.
Definition: bma2x2.c:6448
bma2x2_get_intr_flat
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_flat(u8 channel_u8, u8 *intr_flat_u8)
This API is used to get the interrupt enable of flat interrupt in the register 0x19 and 0x1B...
Definition: bma2x2.c:3736
bma2x2_set_durn
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_durn(u8 channel_u8, u8 durn_u8)
This API is used to set the duration of Low, High, Slope and slow no motion interrupts in the registe...
Definition: bma2x2.c:5205
bma2x2_set_slow_comp
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_slow_comp(u8 channel_u8, u8 slow_comp_u8)
This API is used to set slow compensation(hp_x_enable, hp_y_enable and hp_z_enable) enable in the reg...
Definition: bma2x2.c:7617
bma2x2_set_intr_high_g
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_high_g(u8 channel_u8, u8 intr_high_g_u8)
This API is used to set the interrupt enable of high_g interrupt in the register 0x19 and 0x1B...
Definition: bma2x2.c:2960
bma2x2_set_thres
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_thres(u8 channel_u8, u8 thres_u8)
This API is used to set the threshold of Low, High, Slope and slow no motion interrupts in the regist...
Definition: bma2x2.c:5439
u64
unsigned long long int u64
Definition: bma2x2.h:195
bma2x2_accel_eight_resolution::z
s8 z
Definition: bma2x2.h:575
bma2x2_get_intr_single_tap
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_single_tap(u8 channel_u8, u8 *intr_single_tap_u8)
This API is used to get the interrupt enable of single tap interrupt in the register 0x19 and 0x1B...
Definition: bma2x2.c:3460
bma2x2_get_fifo_data_output_reg
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_fifo_data_output_reg(u8 *output_reg_u8)
This API is used to get the fifo data in the register 0x3F bit 0 to 7.
Definition: bma2x2.c:8351
bma2x2_t::low_mode_reg
u8 low_mode_reg
Definition: bma2x2.h:604
bma2x2_get_high_bw
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_high_bw(u8 *high_bw_u8)
This API is used to get high bandwidth in the register 0x13 bit 7.
Definition: bma2x2.c:1850
bma2x2_set_power_mode
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_power_mode(u8 power_mode_u8)
This API is used to set the operating modes of the sensor in the register 0x11 and 0x12...
Definition: bma2x2.c:1420
bma2x2_get_selftest_axis
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_selftest_axis(u8 *selftest_axis_u8)
This API is for to get the self test axis(self_test_axis) in the register ox32 bit 0 to 2...
Definition: bma2x2.c:6914
bma2x2_accel_eight_resolution_temp::temp
s8 temp
Definition: bma2x2.h:586
bma2x2_set_intr_slow_no_motion
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_slow_no_motion(u8 channel_u8, u8 intr_slow_no_motion_u8)
This API is used to set the interrupt enable of slow/no motion interrupt in the register 0x19 and 0x1...
Definition: bma2x2.c:3242
bma2x2_get_orient_enable
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_orient_enable(u8 *orient_enable_u8)
This API is used to get the interrupt enable of orient ud_enable in the register 0x2D bit 6...
Definition: bma2x2.c:6571
bma2x2_get_intr_stat
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_stat(u8 *intr_stat_u8)
This API read interrupt status of flat, orient, single tap, double tap, slow no motion, slope, highg and lowg from location 09h.
Definition: bma2x2.c:951
bma2x2_get_tap_sample
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_tap_sample(u8 *tap_sample_u8)
This API is used to get the tap sample in the register 0x2B bit 6 and 7.
Definition: bma2x2.c:6091
bma2x2_accel_data::y
s16 y
Definition: bma2x2.h:556
bma2x2_get_selftest_sign
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_selftest_sign(u8 *selftest_sign_u8)
This API is for to get the Self Test sign(selftest_sign) in the register 0x32 bit 2...
Definition: bma2x2.c:7006
bma2x2_set_intr_fifo_full
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_fifo_full(u8 fifo_full_u8)
This API is used to set the interrupt fifo full enable interrupt status in the register 0x17 bit 5...
Definition: bma2x2.c:2420
bma2x2_get_intr_level
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_level(u8 channel_u8, u8 *intr_level_u8)
This API is used to get Active Level status in the register 0x20.
Definition: bma2x2.c:4732
bma2x2_get_fifo_data_select
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_fifo_data_select(u8 *fifo_data_select_u8)
This API is used to get the axis enable of fifo data select in the register 0x3E bit 0 and 1...
Definition: bma2x2.c:8256
bma2x2_set_tap_quiet
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_tap_quiet(u8 tap_quiet_u8)
This API is used to set the tap quiet in the register 0x2A bit 7.
Definition: bma2x2.c:5955
bma2x2_get_range
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_range(u8 *range_u8)
This API is used to get the ranges(g values) of the sensor in the register 0x0F bit from 0 to 3...
Definition: bma2x2.c:991
bma2x2_get_intr_slow_no_motion
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_slow_no_motion(u8 channel_u8, u8 *intr_slow_no_motion_u8)
This API is used to get the interrupt enable of slow/no motion interrupt in the register 0x19 and 0x1...
Definition: bma2x2.c:3176
bma2x2_get_bw
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_bw(u8 *bw_u8)
This API is used to get the bandwidth of the sensor in the register 0x10 bit from 0 to 4...
Definition: bma2x2.c:1111
bma2x2_t
bma2x2 initialization struct struct bma2x2_t is used for assigning the following parameters.
Definition: bma2x2.h:600
BMA2x2_MDELAY_DATA_TYPE
#define BMA2x2_MDELAY_DATA_TYPE
Definition: bma2x2.h:546
bma2x2_get_sleep_timer_mode
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_sleep_timer_mode(u8 *sleep_timer_u8)
This API is used to get the sleep timer mode in the register 0x12 bit 5.
Definition: bma2x2.c:1765
bma2x2_t::BMA2x2_WR_FUNC_PTR
BMA2x2_WR_FUNC_PTR
Definition: bma2x2.h:607
bma2x2_get_intr_fifo_wm
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_fifo_wm(u8 *fifo_wm_u8)
This API is used to get the interrupt fifo watermark enable interrupt status in the register 0x17 bit...
Definition: bma2x2.c:2472
bma2x2_get_intr2_fifo_wm
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr2_fifo_wm(u8 *intr2_fifo_wm_u8)
This API is used to get the fifo watermark interrupt2 data in the register 0x1A bit 6...
Definition: bma2x2.c:4092
bma2x2_set_orient_enable
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_orient_enable(u8 orient_enable_u8)
This API is used to set the interrupt enable of orient ud_enable in the register 0x2D bit 6...
Definition: bma2x2.c:6610
bma2x2_get_slow_comp
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_slow_comp(u8 channel_u8, u8 *slow_comp_u8)
This API is used to get slow compensation(hp_x_enable, hp_y_enable and hp_z_enable) enable in the reg...
Definition: bma2x2.c:7541
s64
signed long long int s64
Definition: bma2x2.h:189
bma2x2_get_intr_enable
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_enable(u8 intr_type_u8, u8 *value_u8)
This API is used to get interrupt enable bits of the sensor in the registers 0x16 and 0x17...
Definition: bma2x2.c:2104
bma2x2_read_accel_eight_resolution_y
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_accel_eight_resolution_y(s8 *accel_y_s8)
This API reads acceleration data Y values of 8bit resolution from location 05h.
Definition: bma2x2.c:430
bma2x2_accel_data_temp
read accel xyz data for 10,14 and 12 bit resolution and temperature output
Definition: bma2x2.h:564
bma2x2_get_nvmprog_mode
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_nvmprog_mode(u8 *nvmprog_mode_u8)
This API is used to get the nvm program mode(nvm_prog_mode)in the register 0x33 bit 0...
Definition: bma2x2.c:7095
bma2x2_set_offset_rst
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_offset_rst(u8 offset_rst_u8)
This API is used to set the offset reset(offset_reset) in the register 0x36 bit 7(Write only possible...
Definition: bma2x2.c:7776
bma2x2_set_tap_durn
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_tap_durn(u8 tap_durn_u8)
This API is used to set the tap duration in the register 0x2A bit form 0 to 2.
Definition: bma2x2.c:5789
bma2x2_get_tap_quiet
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_tap_quiet(u8 *tap_quiet_u8)
This API is used to get the tap quiet in the register 0x2A bit 7.
Definition: bma2x2.c:5916
bma2x2_read_accel_xyzt
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_accel_xyzt(struct bma2x2_accel_data_temp *accel)
This API reads accelerometer data X,Y,Z values and temperature data from location 02h to 08h...
Definition: bma2x2.c:8422
bma2x2_get_tap_shock
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_tap_shock(u8 *tap_shock_u8)
This API is used to get the tap shock form the register 0x2A bit 6.
Definition: bma2x2.c:5833
bma2x2_set_selftest_axis
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_selftest_axis(u8 selftest_axis_u8)
This API is for to set the self test axis(self_test_axis) in the register ox32 bit 0 to 2...
Definition: bma2x2.c:6957
bma2x2_t::ctrl_mode_reg
u8 ctrl_mode_reg
Definition: bma2x2.h:603
bma2x2_get_low_g_mode
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_low_g_mode(u8 *low_g_mode_u8)
This API is used to get low_g mode in the registers 0x24 bit 2.
Definition: bma2x2.c:5655
bma2x2_get_orient_hyst
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_orient_hyst(u8 *orient_hyst_u8)
This API is used to get the orient hysteresis in the register 0x2C bit 4 to 6.
Definition: bma2x2.c:6362
bma2x2_read_accel_eight_resolution_z
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_accel_eight_resolution_z(s8 *accel_z_s8)
This API reads acceleration data Z values of 8bit resolution from location 07h.
Definition: bma2x2.c:552
bma2x2_set_low_high_g_hyst
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_low_high_g_hyst(u8 channel_u8, u8 hyst_u8)
This API is used to set the low high hysteresis in the registers 0x24.
Definition: bma2x2.c:5593
bma2x2_set_nvmprog_mode
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_nvmprog_mode(u8 nvmprog_mode_u8)
This API is used to set the nvm program mode(nvm_prog_mode)in the register 0x33 bit 0...
Definition: bma2x2.c:7133
bma2x2_read_accel_eight_resolution_xyz
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_accel_eight_resolution_xyz(struct bma2x2_accel_eight_resolution *accel)
This API reads acceleration of 8 bit resolution data of X,Y,Z values from location 03h ...
Definition: bma2x2.c:727
bma2x2_set_nvprog_trig
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_nvprog_trig(u8 nvprog_trig_u8)
This API is used to set the value of nvm program trig in the register 0x33 bit 1. ...
Definition: bma2x2.c:7178
bma2x2_get_offset
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_offset(u8 channel_u8, s8 *offset_u8)
This API is used to get the status of offset (offset_x, offset_y and offset_z) in the registers 0x38...
Definition: bma2x2.c:8030
bma2x2_accel_eight_resolution
read accel xyz data for 8 bit resolution
Definition: bma2x2.h:574
bma2x2_accel_data::z
s16 z
Definition: bma2x2.h:556
bma2x2_read_accel_x
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_accel_x(s16 *accel_x_s16)
This API reads acceleration data X values from location 02h and 03h.
Definition: bma2x2.c:227
bma2x2_get_source
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_source(u8 channel_u8, u8 *intr_source_u8)
This API is used to get the source data status of source data, source slow no motion, source slope, source high and source low in the register 0x1E bit from 0 to 5.
Definition: bma2x2.c:4378
bma2x2_burst_read
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_burst_read(u8 addr_u8, u8 *data_u8, u32 len_u32)
This API reads the data from the given register continuously.
Definition: bma2x2.c:77
bma2x2_t::dev_addr
u8 dev_addr
Definition: bma2x2.h:605
bma2x2_set_intr_low_g
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_low_g(u8 channel_u8, u8 intr_low_u8)
This API is used to set the interrupt enable of low_g interrupt in the register 0x19 and 0x1B...
Definition: bma2x2.c:2826
bma2x2_read_temp
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_temp(s8 *temp_s8)
This API is used to read the temp from register 0x08.
Definition: bma2x2.c:8388
bma2x2_get_intr_orient_stat
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_orient_stat(u8 *stat_orient_u8)
This API read orient, high-sign and high-first-xyz status register byte from location 0Ch...
Definition: bma2x2.c:810
bma2x2_set_fifo_data_select
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_fifo_data_select(u8 fifo_data_select_u8)
This API is used to set the axis enable of fifo data select in the register 0x3E bit 0 and 1...
Definition: bma2x2.c:8298
bma2x2_get_flat_hyst
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_flat_hyst(u8 *flat_hyst_u8)
This API is used to get the interrupt enable of flat hysteresis("flat_hy) in the register 0x2F bit 0 ...
Definition: bma2x2.c:6652
bma2x2_get_latch_intr
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_latch_intr(u8 *latch_intr_u8)
This API is used to get the latch duration in the register 0x21 bit from 0 to 3.
Definition: bma2x2.c:4912
bma2x2_read_accel_xyz
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_accel_xyz(struct bma2x2_accel_data *accel)
This API reads acceleration data X,Y,Z values from location 02h to 07h.
Definition: bma2x2.c:590
bma2x2_set_high_bw
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_high_bw(u8 high_bw_u8)
This API is used to write high bandwidth in the register 0x13 bit 7.
Definition: bma2x2.c:1886
bma2x2_get_fifo_frame_count
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_fifo_frame_count(u8 *frame_count_u8)
This API read fifo frame count from location 0Eh bit position 0 to 6.
Definition: bma2x2.c:876
bma2x2_t::chip_id
u8 chip_id
Definition: bma2x2.h:602
bma2x2_set_intr2_fifo_full
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr2_fifo_full(u8 intr2_fifo_full_u8)
This API is used to set the fifo full interrupt2 in the register 0x1A bit 5.
Definition: bma2x2.c:4317
bma2x2_set_flat_hold_time
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_flat_hold_time(u8 flat_hold_time_u8)
This API is used to set the interrupt enable of flat hold time(flat_hold_time) in the register 0x2F b...
Definition: bma2x2.c:6780
bma2x2_get_spi3
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_spi3(u8 *spi3_u8)
This API is used to get the enable status of spi3 in the register 0x34 bit 0.
Definition: bma2x2.c:7302
bma2x2_set_tap_shock
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_tap_shock(u8 tap_shock_u8)
This API is used to set the tap shock form the register 0x2A bit 6.
Definition: bma2x2.c:5873
bma2x2_set_tap_thres
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_tap_thres(u8 tap_thres_u8)
This API is used to set the tap threshold in the register 0x2B bit from 0 to 4.
Definition: bma2x2.c:6046
bma2x2_t::BMA2x2_RD_FUNC_PTR
BMA2x2_RD_FUNC_PTR
Definition: bma2x2.h:608
bma2x2_get_fifo_wml_trig
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_fifo_wml_trig(u8 *fifo_wml_trig)
This API is used to get the fifo water mark level trigger in the register 0x30 bit from 0 to 5...
Definition: bma2x2.c:6823
bma2x2_set_flat_hyst
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_flat_hyst(u8 flat_hyst_u8)
This API is used to set the interrupt enable of flat hysteresis("flat_hy) in the register 0x2F bit 0 ...
Definition: bma2x2.c:6690
bma2x2_get_sleep_durn
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_sleep_durn(u8 *sleep_durn_u8)
This API is used to get the sleep duration of the sensor in the register 0x11 Register 0x11 - bit fro...
Definition: bma2x2.c:1606
bma2x2_set_spi3
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_spi3(u8 spi3_u8)
This API is used to set the enable status of spi3 in the register 0x34 bit 0.
Definition: bma2x2.c:7343
bma2x2_set_latch_intr
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_latch_intr(u8 latch_intr_u8)
This API is used to set the latch duration in the register 0x21 bit from 0 to 3.
Definition: bma2x2.c:4964
bma2x2_get_intr1_fifo_wm
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr1_fifo_wm(u8 *intr1_fifo_wm_u8)
This API is used to get the fifo watermark interrupt1 data in the register 0x1A bit 1...
Definition: bma2x2.c:4004
bma2x2_read_accel_eight_resolution_x
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_accel_eight_resolution_x(s8 *accel_x_s8)
This API reads acceleration data X values from location 02h and 03h bit resolution support 8bit...
Definition: bma2x2.c:307
BMA2x2_RETURN_FUNCTION_TYPE
#define BMA2x2_RETURN_FUNCTION_TYPE
Definition: bma2x2.h:462
bma2x2_get_cal_rdy
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_cal_rdy(u8 *cal_rdy_u8)
This API is used to get the status of fast offset compensation(cal_rdy) in the register 0x36 bit 4(Re...
Definition: bma2x2.c:7697
bma2x2_set_intr_enable
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_enable(u8 intr_type_u8, u8 value_u8)
This API is used to set interrupt enable bits of the sensor in the registers 0x16 and 0x17...
Definition: bma2x2.c:2264
bma2x2_set_intr_slope
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_slope(u8 channel_u8, u8 intr_slope_u8)
This API is used to set the interrupt enable of slope interrupt in the register 0x19 and 0x1B...
Definition: bma2x2.c:3100
bma2x2_get_nvmprog_ready
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_nvmprog_ready(u8 *nvprog_ready_u8)
This API is used to get the nvm program ready in the register bit 2.
Definition: bma2x2.c:7222
bma2x2_set_intr_output_type
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_output_type(u8 channel_u8, u8 intr_output_type_u8)
This API is used to set the interrupt output type in the register 0x20.
Definition: bma2x2.c:4661
bma2x2_get_orient_mode
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_orient_mode(u8 *orient_mode_u8)
This API is used to get the orient mode in the register 0x2C bit 0 and 1.
Definition: bma2x2.c:6179
bma2x2_get_low_high_g_hyst
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_low_high_g_hyst(u8 channel_u8, u8 *hyst_u8)
This API is used to get the low high hysteresis in the registers 0x24.
Definition: bma2x2.c:5524
bma2x2_set_intr_level
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_level(u8 channel_u8, u8 intr_level_u8)
This API is used to set Active Level status in the register 0x20.
Definition: bma2x2.c:4793
bma2x2_read_accel_y
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_accel_y(s16 *accel_y_s16)
This API reads acceleration data Y values from location 04h and 05h.
Definition: bma2x2.c:348
bma2x2_write_reg
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_write_reg(u8 adr_u8, u8 *data_u8, u8 len_u8)
This API gives data to the given register and the data is written in the corresponding register addre...
Definition: bma2x2.c:156
bma2x2_soft_rst
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_soft_rst(void)
This function is used for the soft reset The soft reset register will be written with 0xB6 in the reg...
Definition: bma2x2.c:2002
bma2x2_get_tap_durn
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_tap_durn(u8 *tap_durn_u8)
This API is used to get the tap duration in the register 0x2A bit form 0 to 2.
Definition: bma2x2.c:5743
bma2x2_set_intr_fifo_wm
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_fifo_wm(u8 fifo_wm_u8)
This API is used to set the interrupt fifo watermark enable interrupt status in the register 0x17 bit...
Definition: bma2x2.c:2515
bma2x2_get_nvmprog_remain
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_nvmprog_remain(u8 *nvprog_remain_u8)
This API is used to set the nvm program ready in the register bit 2.
Definition: bma2x2.c:7262
bma2x2_set_i2c_wdt
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_i2c_wdt(u8 channel_u8, u8 i2c_wdt_u8)
This API is used to set the i2c watch dog timer period and I2C interface mode is selected in the regi...
Definition: bma2x2.c:7466
bma2x2_get_intr_tap_stat
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_tap_stat(u8 *stat_tap_u8)
This API read tap-sign, tap-first-xyz slope-sign, slope-first-xyz status register byte from location ...
Definition: bma2x2.c:777
bma2x2_accel_data::x
s16 x
Definition: bma2x2.h:556
bma2x2_t::fifo_config
u8 fifo_config
Definition: bma2x2.h:606
bma2x2_set_new_data
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_new_data(u8 channel_u8, u8 intr_newdata_u8)
This API is used to set the interrupt status of new data in the register 0x19.
Definition: bma2x2.c:3939
s16
signed short int s16
Definition: bma2x2.h:187
bma2x2_set_intr_orient
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_orient(u8 channel_u8, u8 intr_orient_u8)
This API is used to set the interrupt status of orient interrupt in the register 0x19 and 0x1B...
Definition: bma2x2.c:3661
bma2x2_get_intr_slope
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_slope(u8 channel_u8, u8 *intr_slope_u8)
This API is used to get the interrupt enable of slope interrupt in the register 0x19 and 0x1B...
Definition: bma2x2.c:3035
u8
unsigned char u8
Definition: bma2x2.h:192
bma2x2_get_power_mode
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_power_mode(u8 *power_mode_u8)
This API is used to get the operating modes of the sensor in the register 0x11 and 0x12...
Definition: bma2x2.c:1316
bma2x2_set_tap_sample
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_tap_sample(u8 tap_sample_u8)
This API is used to set the tap sample in the register 0x2B bit 6 and 7.
Definition: bma2x2.c:6133
bma2x2_t::BMA2x2_BRD_FUNC_PTR
BMA2x2_BRD_FUNC_PTR
Definition: bma2x2.h:609
bma2x2_get_intr1_fifo_full
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr1_fifo_full(u8 *intr1_fifo_full_u8)
This API is used to get the fifo full interrupt1 in the register 0x1A bit 2.
Definition: bma2x2.c:4182
bma2x2_get_intr_fifo_full
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_fifo_full(u8 *fifo_full_u8)
This API is used to get the interrupt fifo full enable interrupt status in the register 0x17 bit 5...
Definition: bma2x2.c:2379
bma2x2_get_offset_target
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_offset_target(u8 channel_u8, u8 *offset_u8)
This API is used to get the status of offset target axis(offset_target_x, offset_target_y and offset_...
Definition: bma2x2.c:7839
bma2x2_set_orient_hyst
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_orient_hyst(u8 orient_hyst_u8)
This API is used to set the orient hysteresis in the register 0x2C bit 4 to 6.
Definition: bma2x2.c:6399
bma2x2_set_mode_value
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_mode_value(u8 power_mode_u8)
This API is used to assign the power mode values modes of the sensor in the register 0x11 and 0x12...
Definition: bma2x2.c:1526
bma2x2_set_source
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_source(u8 channel_u8, u8 intr_source_u8)
This API is used to set the source data status of source data, source slow no motion, source slope, source high and source low in the register 0x1E bit from 0 to 5.
Definition: bma2x2.c:4475
bma2x2_get_intr_orient
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_orient(u8 channel_u8, u8 *intr_orient_u8)
This API is used to get the interrupt status of orient interrupt in the register 0x19 and 0x1B...
Definition: bma2x2.c:3598
bma2x2_get_tap_thres
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_tap_thres(u8 *tap_thres_u8)
This API is used to get the tap threshold in the register 0x2B bit from 0 to 4.
Definition: bma2x2.c:6003
bma2x2_get_fifo_overrun
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_fifo_overrun(u8 *fifo_overrun_u8)
This API read fifo overrun from location 0Eh bit position 7.
Definition: bma2x2.c:913
bma2x2_set_fifo_mode
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_fifo_mode(u8 fifo_mode_u8)
This API is used to set the status of fifo (fifo_mode) in the register 0x3E bit 6 and 7...
Definition: bma2x2.c:8199
bma2x2_get_intr_output_type
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_output_type(u8 channel_u8, u8 *intr_output_type_u8)
This API is used to get the interrupt output type in the register 0x20.
Definition: bma2x2.c:4599
bma2x2_get_intr_high_g
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_high_g(u8 channel_u8, u8 *intr_high_g_u8)
This API is used to get the interrupt enable of high_g interrupt in the register 0x19 and 0x1B...
Definition: bma2x2.c:2897
u32
unsigned int u32
Definition: bma2x2.h:194
bma2x2_read_accel_z
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_accel_z(s16 *accel_z_s16)
This API reads acceleration data Z values from location 06h and 07h.
Definition: bma2x2.c:470
bma2x2_t::power_mode_u8
u8 power_mode_u8
Definition: bma2x2.h:601
bma2x2_accel_eight_resolution_temp
read accel xyz data for 8 bit resolution and temperature
Definition: bma2x2.h:582
bma2x2_accel_data
read accel xyz data for 10,14 and 12 bit resolution
Definition: bma2x2.h:555
bma2x2_read_reg
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_read_reg(u8 adr_u8, u8 *data_u8, u8 len_u8)
This API reads the data from the given register address.
Definition: bma2x2.c:190
bma2x2_get_thres
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_thres(u8 channel_u8, u8 *thres_u8)
This API is used to get the threshold of Low, High, Slope and slow no motion interrupts in the regist...
Definition: bma2x2.c:5327
bma2x2_get_durn
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_durn(u8 channel_u8, u8 *durn_u8)
This API is used to get the duration of Low, High, Slope and slow no motion interrupts in the registe...
Definition: bma2x2.c:5114
bma2x2_set_intr2_fifo_wm
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr2_fifo_wm(u8 intr2_fifo_wm_u8)
This API is used to set the fifo watermark interrupt2 data in the register 0x1A bit 6...
Definition: bma2x2.c:4131
bma2x2_set_slow_no_motion
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_slow_no_motion(u8 channel_u8, u8 slow_no_motion_u8)
This API is used to set the interrupt status of slow/no motion select and slow no motion enable xyz i...
Definition: bma2x2.c:2654
bma2x2_get_i2c_wdt
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_i2c_wdt(u8 channel_u8, u8 *i2c_wdt_u8)
This API is used to get the i2c watch dog timer period and I2C interface mode is selected in the regi...
Definition: bma2x2.c:7399
bma2x2_set_orient_block
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_orient_block(u8 orient_block_u8)
This API is used to set the orient block in the register 0x2C bit 2 and 3.
Definition: bma2x2.c:6321
bma2x2_set_selftest_sign
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_selftest_sign(u8 selftest_sign_u8)
This API is for to set the Self Test sign(selftest_sign) in the register 0x32 bit 2...
Definition: bma2x2.c:7047
bma2x2_rst_intr
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_rst_intr(u8 rst_intr_u8)
This API is used to set the reset interrupt in the register 0x21 bit 7.
Definition: bma2x2.c:4858
bma2x2_set_low_g_mode
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_low_g_mode(u8 low_g_mode_u8)
This API is used to set low_g mode in the registers 0x24 bit 2.
Definition: bma2x2.c:5693
bma2x2_set_bw
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_bw(u8 bw_u8)
This API is used to set the bandwidth of the sensor in the register 0x10 bit from 0 to 4...
Definition: bma2x2.c:1158
bma2x2_get_intr_double_tap
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr_double_tap(u8 channel_u8, u8 *intr_double_tap_u8)
This API is used to get the interrupt enable of double tap interrupt in the register 0x19 and 0x1B...
Definition: bma2x2.c:3319
bma2x2_set_offset
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_offset(u8 channel_u8, s8 offset_u8)
This API is used to set the status of offset (offset_x, offset_y and offset_z) in the registers 0x38...
Definition: bma2x2.c:8096
bma2x2_set_sleep_timer_mode
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_sleep_timer_mode(u8 sleep_timer_u8)
This API is used to set the sleep timer mode in the register 0x12 bit 5.
Definition: bma2x2.c:1806
bma2x2_set_offset_target
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_offset_target(u8 channel_u8, u8 offset_u8)
This API is used to set the status of offset target axis(offset_target_x, offset_target_y and offset_...
Definition: bma2x2.c:7933
bma2x2_set_intr_flat
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_flat(u8 channel_u8, u8 intr_flat_u8)
This API is used to set the interrupt enable of flat interrupt in the register 0x19 and 0x1B...
Definition: bma2x2.c:3801
s32
signed int s32
Definition: bma2x2.h:188
bma2x2_set_intr_double_tap
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_double_tap(u8 channel_u8, u8 intr_double_tap_u8)
This API is used to set the interrupt enable of double tap interrupt in the register 0x19 and 0x1B...
Definition: bma2x2.c:3384
bma2x2_get_fifo_stat
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_fifo_stat(u8 *stat_fifo_u8)
This API reads fifo overrun and fifo frame counter status register byte from location 0Eh...
Definition: bma2x2.c:842
bma2x2_get_flat_hold_time
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_flat_hold_time(u8 *flat_hold_time_u8)
This API is used to get the interrupt enable of flat hold time(flat_hold_time) in the register 0x2F b...
Definition: bma2x2.c:6736
s8
signed char s8
If your machine support 16 bit define the MACHINE_16_BIT.
Definition: bma2x2.h:186
bma2x2_accel_eight_resolution_temp::z
s8 z
Definition: bma2x2.h:583
bma2x2_accel_data_temp::temp
s8 temp
Definition: bma2x2.h:568
bma2x2_update_image
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_update_image(void)
This API is used to update the register values.
Definition: bma2x2.c:2037
bma2x2_set_intr1_fifo_wm
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr1_fifo_wm(u8 intr1_fifo_wm_u8)
This API is used to set the fifo watermark interrupt1 data in the register 0x1A bit 1...
Definition: bma2x2.c:4043
bma2x2_set_theta
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_theta(u8 channel_u8, u8 theta_u8)
This API is used to set the theta value of orient and flat interrupts.
Definition: bma2x2.c:6510
bma2x2_get_intr2_fifo_full
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_intr2_fifo_full(u8 *intr2_fifo_full_u8)
This API is used to get the fifo full interrupt2 in the register 0x1A bit 5.
Definition: bma2x2.c:4275
bma2x2_accel_data_temp::z
s16 z
Definition: bma2x2.h:565
bma2x2_set_orient_mode
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_orient_mode(u8 orient_mode_u8)
This API is used to set the orient mode in the register 0x2C bit 0 and 1.
Definition: bma2x2.c:6221
bma2x2_set_cal_trigger
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_cal_trigger(u8 cal_trigger_u8)
This API is used to set the status of fast offset compensation(cal_rdy) in the register 0x36 bit 4(Re...
Definition: bma2x2.c:7735
bma2x2_set_sleep_durn
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_sleep_durn(u8 sleep_durn_u8)
This API is used to set the sleep duration of the sensor in the register 0x11 Register 0x11 - bit fro...
Definition: bma2x2.c:1657
u16
unsigned short int u16
Definition: bma2x2.h:193
bma2x2_get_slow_no_motion
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_slow_no_motion(u8 channel_u8, u8 *slow_no_motion_u8)
This API is used to get the interrupt status of slow/no motion select and slow no motion enable xyz i...
Definition: bma2x2.c:2572
bma2x2_init
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_init(struct bma2x2_t *bma2x2)
This function is used for initialize bus read and bus write functions assign the chip id and device a...
Definition: bma2x2.c:117
bma2x2_get_orient_block
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_orient_block(u8 *orient_block_u8)
This API is used to get the orient block in the register 0x2C bit 2 and 3.
Definition: bma2x2.c:6272
bma2x2_set_intr_single_tap
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_intr_single_tap(u8 channel_u8, u8 intr_single_tap_u8)
This API is used to set the interrupt enable of single tap interrupt in the register 0x19 and 0x1B...
Definition: bma2x2.c:3524
bma2x2_set_range
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_set_range(u8 range_u8)
This API is used to set the ranges(g values) of the sensor in the register 0x0F bit from 0 to 3...
Definition: bma2x2.c:1032
bma2x2_get_new_data
BMA2x2_RETURN_FUNCTION_TYPE bma2x2_get_new_data(u8 channel_u8, u8 *intr_newdata_u8)
This API is used to get the interrupt status of new data in the register 0x19.
Definition: bma2x2.c:3875
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