59 #include <drivers/hw_include/cslr.h>
60 #include <drivers/hw_include/cslr_soc.h>
61 #include <drivers/hw_include/cslr_lin.h>
62 #include <drivers/hw_include/hw_types.h>
74 #define LIN_IO_DFT_KEY (0xAU)
78 #define LIN_WAKEUP_KEY (0xF0U)
88 #define LIN_ID0 (0x1U)
89 #define LIN_ID1 (0x2U)
90 #define LIN_ID2 (0x4U)
91 #define LIN_ID3 (0x8U)
92 #define LIN_ID4 (0x10U)
93 #define LIN_ID5 (0x20U)
106 #define LIN_INT_WAKEUP (0x00000002U)
107 #define LIN_INT_TO (0x00000010U)
108 #define LIN_INT_TOAWUS (0x00000040U)
109 #define LIN_INT_TOA3WUS (0x00000080U)
110 #define LIN_INT_TX (0x00000100U)
111 #define LIN_INT_RX (0x00000200U)
112 #define LIN_INT_ID (0x00002000U)
113 #define LIN_INT_PE (0x01000000U)
114 #define LIN_INT_OE (0x02000000U)
115 #define LIN_INT_FE (0x04000000U)
116 #define LIN_INT_NRE (0x08000000U)
117 #define LIN_INT_ISFE (0x10000000U)
118 #define LIN_INT_CE (0x20000000U)
119 #define LIN_INT_PBE (0x40000000U)
120 #define LIN_INT_BE (0x80000000U)
121 #define LIN_INT_ALL (0xFF0023D2U)
132 #define LIN_FLAG_BREAK (CSL_APP_LIN_SCIFLR_BRKDT_MASK)
133 #define LIN_FLAG_WAKEUP (CSL_APP_LIN_SCIFLR_WAKEUP_MASK)
134 #define LIN_FLAG_IDLE (CSL_APP_LIN_SCIFLR_BUSY_MASK)
135 #define LIN_FLAG_TO (CSL_APP_LIN_SCIFLR_TIMEOUT_MASK)
136 #define LIN_FLAG_TOAWUS (CSL_APP_LIN_SCIFLR_TOAWUS_MASK)
137 #define LIN_FLAG_TOA3WUS (CSL_APP_LIN_SCIFLR_TOA3WUS_MASK)
138 #define LIN_FLAG_TXRDY (CSL_APP_LIN_SCIFLR_TXRDY_MASK)
139 #define LIN_FLAG_RXRDY (CSL_APP_LIN_SCIFLR_RXRDY_MASK)
140 #define LIN_FLAG_TXWAKE (CSL_APP_LIN_SCIFLR_TXWAKE_MASK)
141 #define LIN_FLAG_TXEMPTY (CSL_APP_LIN_SCIFLR_TXEMPTY_MASK)
142 #define LIN_FLAG_RXWAKE (CSL_APP_LIN_SCIFLR_RXWAKE_MASK)
143 #define LIN_FLAG_TXID (CSL_APP_LIN_SCIFLR_IDTXFLAG_MASK)
144 #define LIN_FLAG_RXID (CSL_APP_LIN_SCIFLR_IDRXFLAG_MASK)
145 #define LIN_FLAG_PE (CSL_APP_LIN_SCIFLR_PE_MASK)
146 #define LIN_FLAG_OE (CSL_APP_LIN_SCIFLR_OE_MASK)
147 #define LIN_FLAG_FE (CSL_APP_LIN_SCIFLR_FE_MASK)
148 #define LIN_FLAG_NRE (CSL_APP_LIN_SCIFLR_NRE_MASK)
149 #define LIN_FLAG_ISFE (CSL_APP_LIN_SCIFLR_ISFE_MASK)
150 #define LIN_FLAG_CE (CSL_APP_LIN_SCIFLR_CE_MASK)
151 #define LIN_FLAG_PBE (CSL_APP_LIN_SCIFLR_PBE_MASK)
152 #define LIN_FLAG_BE (CSL_APP_LIN_SCIFLR_BE_MASK)
164 #define LIN_VECT_NONE (0x00)
165 #define LIN_VECT_WAKEUP (0x01)
166 #define LIN_VECT_ISFE (0x02)
167 #define LIN_VECT_PE (0x03)
168 #define LIN_VECT_ID (0x04)
169 #define LIN_VECT_PBE (0x05)
170 #define LIN_VECT_FE (0x06)
171 #define LIN_VECT_BREAK (0x07)
172 #define LIN_VECT_CE (0x08)
173 #define LIN_VECT_OE (0x09)
174 #define LIN_VECT_BE (0x0A)
175 #define LIN_VECT_RX (0x0B)
176 #define LIN_VECT_TX (0x0C)
177 #define LIN_VECT_NRE (0x0D)
178 #define LIN_VECT_TOAWUS (0x0E)
179 #define LIN_VECT_TOA3WUS (0x0F)
180 #define LIN_VECT_TO (0x10)
192 #define LIN_ALL_ERRORS (0xF0000000U)
193 #define LIN_BIT_ERROR (0x80000000U)
194 #define LIN_BUS_ERROR (0x40000000U)
195 #define LIN_CHECKSUM_ERROR (0x20000000U)
196 #define LIN_ISF_ERROR (0x10000000U)
208 #define LIN_SCI_ALL_ERRORS (0x7000000U)
209 #define LIN_SCI_FRAME_ERROR (0x4000000U)
210 #define LIN_SCI_PARITY_ERROR (0x2000000U)
211 #define LIN_SCI_BREAK_ERROR (0x1000000U)
224 #define LIN_SCI_INT_BREAK (0x1U)
225 #define LIN_SCI_INT_WAKEUP (0x2U)
226 #define LIN_SCI_INT_TX (0x100U)
227 #define LIN_SCI_INT_RX (0x200U)
228 #define LIN_SCI_INT_TX_DMA (0x10000U)
229 #define LIN_SCI_INT_RX_DMA (0x20000U)
230 #define LIN_SCI_INT_PARITY (0x1000000U)
231 #define LIN_SCI_INT_OVERRUN (0x2000000U)
232 #define LIN_SCI_INT_FRAME (0x4000000U)
233 #define LIN_SCI_INT_ALL (0x7000303U)
402 return(base == CSL_APP_LIN_U_BASE);
424 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCIGCR1), CSL_APP_LIN_SCIGCR1_CLK_COMMANDER_MASK, CSL_APP_LIN_SCIGCR1_CLK_COMMANDER_SHIFT, mode);
450 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_MBRSR), CSL_APP_LIN_MBRSR_MBR_MASK, CSL_APP_LIN_MBRSR_MBR_SHIFT, (clock / 20000U));
472 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCIGCR1), CSL_APP_LIN_SCIGCR1_HGENCTRL_MASK, CSL_APP_LIN_SCIGCR1_HGENCTRL_SHIFT, type);
490 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCIGCR1), CSL_APP_LIN_SCIGCR1_PARITYENA_MASK, CSL_APP_LIN_SCIGCR1_PARITYENA_SHIFT, CSL_TRUE);
508 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCIGCR1), CSL_APP_LIN_SCIGCR1_PARITYENA_MASK, CSL_APP_LIN_SCIGCR1_PARITYENA_SHIFT, CSL_FALSE);
526 static inline uint16_t
529 uint16_t p0, p1, parityIdentifier;
534 p1 = ((((identifier &
LIN_ID1) >> 1U) ^ ((identifier &
LIN_ID3) >> 3U) ^ ((identifier &
LIN_ID4) >> 4U) ^ ((identifier &
LIN_ID5) >> 5U)) == 0U) ? 1U : 0U;
535 parityIdentifier = identifier | ((p0 << 6U) | (p1 << 7U));
537 return(parityIdentifier);
557 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_LINID), CSL_APP_LIN_LINID_IDBYTE_MASK, CSL_APP_LIN_LINID_IDBYTE_SHIFT, identifier);
577 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_LINID), CSL_APP_LIN_LINID_IDRESPONDERTASKBYTE_MASK, CSL_APP_LIN_LINID_IDRESPONDERTASKBYTE_SHIFT, identifier);
592 volatile uint8_t timeout = 0x10;
598 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCIGCR2), CSL_APP_LIN_SCIGCR2_POWERDOWN_MASK, CSL_APP_LIN_SCIGCR2_POWERDOWN_SHIFT, CSL_TRUE);
601 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_LINTD0), CSL_APP_LIN_LINTD0_TD3_MASK, CSL_APP_LIN_LINTD0_TD3_SHIFT, (uint16_t)
LIN_WAKEUP_KEY);
604 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCIGCR2), CSL_APP_LIN_SCIGCR2_GENWU_MASK, CSL_APP_LIN_SCIGCR2_GENWU_SHIFT, CSL_TRUE);
606 while((HW_RD_FIELD32_RAW((base + CSL_APP_LIN_SCIGCR2), CSL_APP_LIN_SCIGCR2_POWERDOWN_MASK, CSL_APP_LIN_SCIGCR2_POWERDOWN_SHIFT) == CSL_TRUE))
610 timeout = timeout- 1U;
640 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCIGCR2), CSL_APP_LIN_SCIGCR2_POWERDOWN_MASK, CSL_APP_LIN_SCIGCR2_POWERDOWN_SHIFT, CSL_TRUE);
659 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCIGCR2), CSL_APP_LIN_SCIGCR2_SC_MASK, CSL_APP_LIN_SCIGCR2_SC_SHIFT, CSL_TRUE);
678 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCIGCR2), CSL_APP_LIN_SCIGCR2_CC_MASK, CSL_APP_LIN_SCIGCR2_CC_SHIFT, CSL_TRUE);
699 return((HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIFLR) & CSL_APP_LIN_SCIFLR_TXRDY_MASK) ==
700 CSL_APP_LIN_SCIFLR_TXRDY_MASK);
723 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCIFORMAT), CSL_APP_LIN_SCIFORMAT_LENGTH_MASK, CSL_APP_LIN_SCIFORMAT_LENGTH_SHIFT, ((uint32_t)length - (uint32_t)1U));
747 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCIGCR1), CSL_APP_LIN_SCIGCR1_COMMMODE_MASK, CSL_APP_LIN_SCIGCR1_COMMMODE_SHIFT, (uint16_t)mode);
767 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_LINMASK), CSL_APP_LIN_LINMASK_TXIDMASK_MASK, CSL_APP_LIN_LINMASK_TXIDMASK_SHIFT, mask);
787 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_LINMASK), CSL_APP_LIN_LINMASK_RXIDMASK_MASK, CSL_APP_LIN_LINMASK_RXIDMASK_SHIFT, (uint32_t)mask);
799 static inline uint16_t
806 return(HW_RD_FIELD32_RAW((base + CSL_APP_LIN_LINMASK), CSL_APP_LIN_LINMASK_TXIDMASK_MASK, CSL_APP_LIN_LINMASK_TXIDMASK_SHIFT));
820 static inline uint16_t
827 return(HW_RD_FIELD32_RAW((base + CSL_APP_LIN_LINMASK), CSL_APP_LIN_LINMASK_RXIDMASK_MASK, CSL_APP_LIN_LINMASK_RXIDMASK_SHIFT));
848 return(HW_RD_FIELD32_RAW((base + CSL_APP_LIN_SCIFLR), CSL_APP_LIN_SCIFLR_RXRDY_MASK, CSL_APP_LIN_SCIFLR_RXRDY_SHIFT));
861 static inline uint16_t
868 return(HW_RD_FIELD32_RAW((base + CSL_APP_LIN_LINID), CSL_APP_LIN_LINID_RECEIVEDID_MASK, CSL_APP_LIN_LINID_RECEIVEDID_SHIFT));
889 return(HW_RD_FIELD32_RAW((base + CSL_APP_LIN_SCIFLR), CSL_APP_LIN_SCIFLR_IDTXFLAG_MASK, CSL_APP_LIN_SCIFLR_IDTXFLAG_SHIFT));
910 return(HW_RD_FIELD32_RAW((base + CSL_APP_LIN_SCIFLR), CSL_APP_LIN_SCIFLR_IDRXFLAG_MASK, CSL_APP_LIN_SCIFLR_IDRXFLAG_SHIFT));
953 HW_WR_REG32_RAW((base + CSL_APP_LIN_SCISETINT), HW_RD_REG32_RAW(base + CSL_APP_LIN_SCISETINT)|intFlags);
996 HW_WR_REG32_RAW((base + CSL_APP_LIN_SCICLEARINT), intFlags);
1038 HW_WR_REG32_RAW((base + CSL_APP_LIN_SCIFLR), intFlags);
1081 HW_WR_REG32_RAW((base + CSL_APP_LIN_SCICLEARINTLVL), intFlags);
1124 HW_WR_REG32_RAW((base + CSL_APP_LIN_SCISETINTLVL), HW_RD_REG32_RAW(base + CSL_APP_LIN_SCISETINTLVL)|intFlags);
1151 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_IODFTCTRL), CSL_APP_LIN_IODFTCTRL_IODFTENA_MASK, CSL_APP_LIN_IODFTCTRL_IODFTENA_SHIFT, (uint32_t)
LIN_IO_DFT_KEY);
1154 HW_WR_REG32_RAW((base + CSL_APP_LIN_IODFTCTRL), HW_RD_REG32_RAW(base + CSL_APP_LIN_IODFTCTRL)|errors);
1157 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_IODFTCTRL), CSL_APP_LIN_IODFTCTRL_IODFTENA_MASK, CSL_APP_LIN_IODFTCTRL_IODFTENA_SHIFT, (uint32_t)CSL_FALSE);
1182 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_IODFTCTRL), CSL_APP_LIN_IODFTCTRL_IODFTENA_MASK, CSL_APP_LIN_IODFTCTRL_IODFTENA_SHIFT, (uint32_t)
LIN_IO_DFT_KEY);
1185 HW_WR_REG32_RAW((base + CSL_APP_LIN_IODFTCTRL), HW_RD_REG32_RAW(base + CSL_APP_LIN_IODFTCTRL)&~(errors));
1188 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_IODFTCTRL), CSL_APP_LIN_IODFTCTRL_IODFTENA_MASK, CSL_APP_LIN_IODFTCTRL_IODFTENA_SHIFT, (uint32_t)CSL_FALSE);
1210 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCIGCR1), CSL_APP_LIN_SCIGCR1_ADAPT_MASK, CSL_APP_LIN_SCIGCR1_ADAPT_SHIFT, CSL_TRUE);
1229 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCIGCR1), CSL_APP_LIN_SCIGCR1_ADAPT_MASK, CSL_APP_LIN_SCIGCR1_ADAPT_SHIFT, CSL_FALSE);
1250 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCIGCR1), CSL_APP_LIN_SCIGCR1_STOPEXTFRAME_MASK, CSL_APP_LIN_SCIGCR1_STOPEXTFRAME_SHIFT, CSL_TRUE);
1272 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCIGCR1), CSL_APP_LIN_SCIGCR1_CTYPE_MASK, CSL_APP_LIN_SCIGCR1_CTYPE_SHIFT, type);
1307 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_LINCOMP), (CSL_APP_LIN_LINCOMP_SDEL_MASK|CSL_APP_LIN_LINCOMP_SBREAK_MASK),
1308 CSL_APP_LIN_LINCOMP_SDEL_SHIFT, (syncBreak | (delimiter - (uint32_t)1U)));
1325 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCIGCR1), CSL_APP_LIN_SCIGCR1_LINMODE_MASK,
1326 CSL_APP_LIN_SCIGCR1_LINMODE_SHIFT, CSL_FALSE);
1328 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCIGCR1), CSL_APP_LIN_SCIGCR1_CLK_COMMANDER_MASK,
1329 CSL_APP_LIN_SCIGCR1_CLK_COMMANDER_SHIFT, CSL_TRUE);
1331 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCIGCR1), CSL_APP_LIN_SCIGCR1_TIMINGMODE_MASK,
1332 CSL_APP_LIN_SCIGCR1_TIMINGMODE_SHIFT, CSL_TRUE);
1350 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCIGCR1), CSL_APP_LIN_SCIGCR1_CLK_COMMANDER_MASK,
1351 CSL_APP_LIN_SCIGCR1_CLK_COMMANDER_SHIFT, CSL_FALSE);
1353 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCIGCR1), CSL_APP_LIN_SCIGCR1_TIMINGMODE_MASK,
1354 CSL_APP_LIN_SCIGCR1_TIMINGMODE_SHIFT, CSL_FALSE);
1356 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCIGCR1), CSL_APP_LIN_SCIGCR1_LINMODE_MASK,
1357 CSL_APP_LIN_SCIGCR1_LINMODE_SHIFT, CSL_TRUE);
1378 DebugP_assert((HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIGCR1) & CSL_APP_LIN_SCIGCR1_LINMODE_MASK) ==
1381 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCIGCR1), CSL_APP_LIN_SCIGCR1_COMMMODE_MASK,
1382 CSL_APP_LIN_SCIGCR1_COMMMODE_SHIFT, mode);
1402 DebugP_assert((HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIGCR1) & CSL_APP_LIN_SCIGCR1_LINMODE_MASK) ==
1405 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCIGCR1), CSL_APP_LIN_SCIGCR1_PARITYENA_MASK,
1406 CSL_APP_LIN_SCIGCR1_PARITYENA_SHIFT, 1U);
1408 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCIGCR1), CSL_APP_LIN_SCIGCR1_PARITY_MASK,
1409 CSL_APP_LIN_SCIGCR1_PARITY_SHIFT, parity);
1425 DebugP_assert((HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIGCR1) & CSL_APP_LIN_SCIGCR1_LINMODE_MASK) ==
1428 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCIGCR1), CSL_APP_LIN_SCIGCR1_PARITYENA_MASK,
1429 CSL_APP_LIN_SCIGCR1_PARITYENA_SHIFT, 0U);
1449 DebugP_assert((HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIGCR1) & CSL_APP_LIN_SCIGCR1_LINMODE_MASK) ==
1452 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCIGCR1), CSL_APP_LIN_SCIGCR1_STOP_MASK,
1453 CSL_APP_LIN_SCIGCR1_STOP_SHIFT, number);
1474 DebugP_assert((HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIGCR1) & CSL_APP_LIN_SCIGCR1_LINMODE_MASK) ==
1477 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCIGCR1), CSL_APP_LIN_SCIGCR1_SLEEP_MASK,
1478 CSL_APP_LIN_SCIGCR1_SLEEP_SHIFT, CSL_TRUE);
1495 DebugP_assert((HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIGCR1) & CSL_APP_LIN_SCIGCR1_LINMODE_MASK) ==
1498 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCIGCR1), CSL_APP_LIN_SCIGCR1_SLEEP_MASK,
1499 CSL_APP_LIN_SCIGCR1_SLEEP_SHIFT, CSL_FALSE);
1519 DebugP_assert((HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIGCR1) & CSL_APP_LIN_SCIGCR1_LINMODE_MASK) ==
1522 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCIGCR2), CSL_APP_LIN_SCIGCR2_POWERDOWN_MASK,
1523 CSL_APP_LIN_SCIGCR2_POWERDOWN_SHIFT, CSL_TRUE);
1539 DebugP_assert((HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIGCR1) & CSL_APP_LIN_SCIGCR1_LINMODE_MASK) ==
1542 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCIGCR2), CSL_APP_LIN_SCIGCR2_POWERDOWN_MASK,
1543 CSL_APP_LIN_SCIGCR2_POWERDOWN_SHIFT, CSL_FALSE);
1562 DebugP_assert((HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIGCR1) & CSL_APP_LIN_SCIGCR1_LINMODE_MASK) ==
1566 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCIFORMAT), CSL_APP_LIN_SCIFORMAT_CHAR_MASK,
1567 CSL_APP_LIN_SCIFORMAT_CHAR_SHIFT, (numBits - (uint32_t)1U));
1587 DebugP_assert((HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIGCR1) & CSL_APP_LIN_SCIGCR1_LINMODE_MASK) ==
1591 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCIFORMAT), CSL_APP_LIN_SCIFORMAT_LENGTH_MASK,
1592 CSL_APP_LIN_SCIFORMAT_LENGTH_SHIFT, (length - (uint32_t)1U));
1611 DebugP_assert((HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIGCR1) & CSL_APP_LIN_SCIGCR1_LINMODE_MASK) ==
1614 return((HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIFLR) & CSL_APP_LIN_SCIFLR_RXRDY_MASK) == CSL_APP_LIN_SCIFLR_RXRDY_MASK);
1633 DebugP_assert((HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIGCR1) & CSL_APP_LIN_SCIGCR1_LINMODE_MASK) ==
1636 return((HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIFLR) & CSL_APP_LIN_SCIFLR_TXRDY_MASK) == CSL_APP_LIN_SCIFLR_TXRDY_MASK);
1660 static inline uint16_t
1665 DebugP_assert((HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIGCR1) & CSL_APP_LIN_SCIGCR1_LINMODE_MASK) ==
1669 return((emulation > 0U) ? (HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIED) & CSL_APP_LIN_SCIED_ED_MASK) :
1670 (HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIRD) & CSL_APP_LIN_SCIRD_RD_MASK));
1692 static inline uint16_t
1697 DebugP_assert((HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIGCR1) & CSL_APP_LIN_SCIGCR1_LINMODE_MASK) ==
1706 return((emulation > 0U) ? (HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIED) & CSL_APP_LIN_SCIED_ED_MASK) :
1707 (HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIRD) & CSL_APP_LIN_SCIRD_RD_MASK));
1729 DebugP_assert((HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIGCR1) & CSL_APP_LIN_SCIGCR1_LINMODE_MASK) ==
1734 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCITD), CSL_APP_LIN_SCITD_TD_MASK, CSL_APP_LIN_SCITD_TD_SHIFT, data);
1753 DebugP_assert((HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIGCR1) & CSL_APP_LIN_SCIGCR1_LINMODE_MASK) ==
1763 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCITD), CSL_APP_LIN_SCITD_TD_MASK, CSL_APP_LIN_SCITD_TD_SHIFT, data);
1789 DebugP_assert((HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIGCR1) & CSL_APP_LIN_SCIGCR1_LINMODE_MASK) ==
1793 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_IODFTCTRL), CSL_APP_LIN_IODFTCTRL_IODFTENA_MASK, CSL_APP_LIN_IODFTCTRL_IODFTENA_SHIFT,
LIN_IO_DFT_KEY);
1796 HW_WR_REG32_RAW((base + CSL_APP_LIN_IODFTCTRL), (HW_RD_REG32_RAW(base + CSL_APP_LIN_IODFTCTRL)|errors));
1799 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_IODFTCTRL), CSL_APP_LIN_IODFTCTRL_IODFTENA_MASK, CSL_APP_LIN_IODFTCTRL_IODFTENA_SHIFT, CSL_FALSE);
1822 DebugP_assert((HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIGCR1) & CSL_APP_LIN_SCIGCR1_LINMODE_MASK) ==
1826 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_IODFTCTRL), CSL_APP_LIN_IODFTCTRL_IODFTENA_MASK, CSL_APP_LIN_IODFTCTRL_IODFTENA_SHIFT,
LIN_IO_DFT_KEY);
1829 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_IODFTCTRL), errors, 0U, CSL_FALSE);
1832 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_IODFTCTRL), CSL_APP_LIN_IODFTCTRL_IODFTENA_MASK, CSL_APP_LIN_IODFTCTRL_IODFTENA_SHIFT, CSL_FALSE);
1867 DebugP_assert((HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIGCR1) & CSL_APP_LIN_SCIGCR1_LINMODE_MASK) ==
1871 HW_WR_REG32_RAW((base + CSL_APP_LIN_SCISETINT), (HW_RD_REG32_RAW(base + CSL_APP_LIN_SCISETINT)|intFlags));
1906 DebugP_assert((HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIGCR1) & CSL_APP_LIN_SCIGCR1_LINMODE_MASK) ==
1910 HW_WR_REG32_RAW((base + CSL_APP_LIN_SCICLEARINT), (HW_RD_REG32_RAW(base + CSL_APP_LIN_SCICLEARINT)|intFlags));
1944 DebugP_assert((HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIGCR1) & CSL_APP_LIN_SCIGCR1_LINMODE_MASK) ==
1948 HW_WR_REG32_RAW((base + CSL_APP_LIN_SCIFLR), (HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIFLR)|intFlags));
1983 DebugP_assert((HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIGCR1) & CSL_APP_LIN_SCIGCR1_LINMODE_MASK) ==
1987 HW_WR_REG32_RAW((base + CSL_APP_LIN_SCICLEARINTLVL), (HW_RD_REG32_RAW(base + CSL_APP_LIN_SCICLEARINTLVL)|intFlags));
2021 DebugP_assert((HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIGCR1) & CSL_APP_LIN_SCIGCR1_LINMODE_MASK) ==
2025 HW_WR_REG32_RAW((base + CSL_APP_LIN_SCISETINTLVL), HW_RD_REG32_RAW(base + CSL_APP_LIN_SCISETINTLVL)|intFlags);
2044 DebugP_assert((HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIGCR1) & CSL_APP_LIN_SCIGCR1_LINMODE_MASK) ==
2048 return((HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIFLR) & CSL_APP_LIN_SCIFLR_IDLE_MASK) == 0U);
2068 DebugP_assert((HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIGCR1) & CSL_APP_LIN_SCIGCR1_LINMODE_MASK) ==
2072 return((HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIFLR) & CSL_APP_LIN_SCIFLR_WAKEUP_MASK) == CSL_APP_LIN_SCIFLR_WAKEUP_MASK);
2092 DebugP_assert((HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIGCR1) & CSL_APP_LIN_SCIGCR1_LINMODE_MASK) ==
2096 return((HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIFLR) & CSL_APP_LIN_SCIFLR_RXWAKE_MASK) == CSL_APP_LIN_SCIFLR_RXWAKE_MASK);
2115 DebugP_assert((HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIGCR1) & CSL_APP_LIN_SCIGCR1_LINMODE_MASK) ==
2119 return((HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIFLR) & CSL_APP_LIN_SCIFLR_BRKDT_MASK) == CSL_APP_LIN_SCIFLR_BRKDT_MASK);
2140 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCIGCR0), CSL_APP_LIN_SCIGCR0_RESET_MASK, CSL_APP_LIN_SCIGCR0_RESET_SHIFT, CSL_TRUE);
2143 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCIPIO0), CSL_APP_LIN_SCIPIO0_RXFUNC_MASK, CSL_APP_LIN_SCIPIO0_RXFUNC_SHIFT, CSL_TRUE);
2144 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCIPIO0), CSL_APP_LIN_SCIPIO0_TXFUNC_MASK, CSL_APP_LIN_SCIPIO0_TXFUNC_SHIFT, CSL_TRUE);
2165 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCIPIO0), CSL_APP_LIN_SCIPIO0_RXFUNC_MASK, CSL_APP_LIN_SCIPIO0_RXFUNC_SHIFT, CSL_FALSE);
2166 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCIPIO0), CSL_APP_LIN_SCIPIO0_TXFUNC_MASK, CSL_APP_LIN_SCIPIO0_TXFUNC_SHIFT, CSL_FALSE);
2169 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCIGCR0), CSL_APP_LIN_SCIGCR0_RESET_MASK, CSL_APP_LIN_SCIGCR0_RESET_SHIFT, CSL_FALSE);
2193 DebugP_assert(prescaler <= (CSL_APP_LIN_BRSR_SCI_LIN_PSL_MASK | CSL_APP_LIN_BRSR_SCI_LIN_PSH_MASK));
2194 DebugP_assert(divider <= (CSL_APP_LIN_BRSR_M_MASK >> CSL_APP_LIN_BRSR_M_SHIFT));
2197 HW_WR_REG32_RAW((base + CSL_APP_LIN_BRSR), (prescaler | (divider << CSL_APP_LIN_BRSR_M_SHIFT)));
2216 HW_WR_REG32_RAW((base + CSL_APP_LIN_SCIGCR1), HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIGCR1)|CSL_APP_LIN_SCIGCR1_TXENA_MASK);
2235 HW_WR_REG32_RAW((base + CSL_APP_LIN_SCIGCR1), HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIGCR1)&~(CSL_APP_LIN_SCIGCR1_TXENA_MASK));
2254 HW_WR_REG32_RAW((base + CSL_APP_LIN_SCIGCR1), HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIGCR1)|CSL_APP_LIN_SCIGCR1_RXENA_MASK);
2273 HW_WR_REG32_RAW((base + CSL_APP_LIN_SCIGCR1), HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIGCR1)&~(CSL_APP_LIN_SCIGCR1_RXENA_MASK));
2295 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCIGCR1), CSL_APP_LIN_SCIGCR1_SWNRST_MASK, CSL_APP_LIN_SCIGCR1_SWNRST_SHIFT, CSL_FALSE);
2296 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCIGCR1), CSL_APP_LIN_SCIGCR1_SWNRST_MASK, CSL_APP_LIN_SCIGCR1_SWNRST_SHIFT, CSL_TRUE);
2319 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCIGCR1), CSL_APP_LIN_SCIGCR1_SWNRST_MASK, CSL_APP_LIN_SCIGCR1_SWNRST_SHIFT, CSL_FALSE);
2340 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCIGCR1), CSL_APP_LIN_SCIGCR1_SWNRST_MASK, CSL_APP_LIN_SCIGCR1_SWNRST_SHIFT, CSL_TRUE);
2360 return((HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIFLR) & CSL_APP_LIN_SCIFLR_BUSY_MASK) == CSL_APP_LIN_SCIFLR_BUSY_MASK);
2380 return((HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIFLR) & CSL_APP_LIN_SCIFLR_TXEMPTY_MASK) == CSL_APP_LIN_SCIFLR_TXEMPTY_MASK);
2412 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_IODFTCTRL), CSL_APP_LIN_IODFTCTRL_IODFTENA_MASK, CSL_APP_LIN_IODFTCTRL_IODFTENA_SHIFT,
LIN_IO_DFT_KEY);
2415 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_IODFTCTRL), CSL_APP_LIN_IODFTCTRL_LPBENA_MASK, CSL_APP_LIN_IODFTCTRL_LPBENA_SHIFT, loopbackType);
2418 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_IODFTCTRL), CSL_APP_LIN_IODFTCTRL_RXPENA_MASK, CSL_APP_LIN_IODFTCTRL_RXPENA_SHIFT, path);
2439 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_IODFTCTRL), CSL_APP_LIN_IODFTCTRL_LPBENA_MASK, CSL_APP_LIN_IODFTCTRL_LPBENA_SHIFT, CSL_FALSE);
2442 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_IODFTCTRL), CSL_APP_LIN_IODFTCTRL_RXPENA_MASK, CSL_APP_LIN_IODFTCTRL_RXPENA_SHIFT, CSL_FALSE);
2461 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCIGCR1), CSL_APP_LIN_SCIGCR1_LOOPBACK_MASK, CSL_APP_LIN_SCIGCR1_LOOPBACK_SHIFT, CSL_TRUE);
2480 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCIGCR1), CSL_APP_LIN_SCIGCR1_LOOPBACK_MASK, CSL_APP_LIN_SCIGCR1_LOOPBACK_SHIFT, CSL_FALSE);
2516 static inline uint32_t
2523 return(HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIFLR));
2537 static inline uint32_t
2544 return(HW_RD_REG32_RAW(base + CSL_APP_LIN_SCISETINTLVL));
2582 static inline uint16_t
2589 return(HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIINTVECT0) & CSL_APP_LIN_SCIINTVECT0_INTVECT0_MASK);
2627 static inline uint16_t
2634 return(HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIINTVECT1) & CSL_APP_LIN_SCIINTVECT1_INTVECT1_MASK);
2652 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCIGCR1), CSL_APP_LIN_SCIGCR1_MBUFMODE_MASK, CSL_APP_LIN_SCIGCR1_MBUFMODE_SHIFT, CSL_TRUE);
2670 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCIGCR1), CSL_APP_LIN_SCIGCR1_MBUFMODE_MASK, CSL_APP_LIN_SCIGCR1_MBUFMODE_SHIFT, CSL_FALSE);
2694 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_IODFTCTRL), CSL_APP_LIN_IODFTCTRL_IODFTENA_MASK, CSL_APP_LIN_IODFTCTRL_IODFTENA_SHIFT,
LIN_IO_DFT_KEY);
2697 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_IODFTCTRL), CSL_APP_LIN_IODFTCTRL_TXSHIFT_MASK, CSL_APP_LIN_IODFTCTRL_TXSHIFT_SHIFT, delay);
2700 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_IODFTCTRL), CSL_APP_LIN_IODFTCTRL_IODFTENA_MASK, CSL_APP_LIN_IODFTCTRL_IODFTENA_SHIFT, CSL_FALSE);
2726 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_IODFTCTRL), CSL_APP_LIN_IODFTCTRL_IODFTENA_MASK, CSL_APP_LIN_IODFTCTRL_IODFTENA_SHIFT,
LIN_IO_DFT_KEY);
2729 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_IODFTCTRL), CSL_APP_LIN_IODFTCTRL_PINSAMPLEMASK_MASK, CSL_APP_LIN_IODFTCTRL_PINSAMPLEMASK_SHIFT, mask);
2732 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_IODFTCTRL), CSL_APP_LIN_IODFTCTRL_IODFTENA_MASK, CSL_APP_LIN_IODFTCTRL_IODFTENA_SHIFT, CSL_FALSE);
2757 HW_WR_FIELD32_RAW((base + CSL_APP_LIN_SCIGCR1), CSL_APP_LIN_SCIGCR1_CONT_MASK, CSL_APP_LIN_SCIGCR1_CONT_SHIFT, mode);
2779 return((HW_RD_REG32_RAW(base + CSL_APP_LIN_SCIPIO2) & (uint32_t)pin) == (uint32_t)pin);