xWRL1432 MMWAVE-L-SDK
05.03.00
cslr_soc_defines.h
Go to the documentation of this file.
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/*
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* Copyright (C) 2020-23 Texas Instruments Incorporated
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the
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* distribution.
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*
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* Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#ifndef CSLR_SOC_DEFINES_H_
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#define CSLR_SOC_DEFINES_H_
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/* ========================================================================== */
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/* Include Files */
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/* ========================================================================== */
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/* None */
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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/* ========================================================================== */
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/* Macros & Typedefs */
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/* ========================================================================== */
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#define CSL_CORE_ID_M4FSS0_0 (0U)
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#define CSL_CORE_ID_MAX (1U)
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#define CSL_APSS_UART_PER_CNT (2U)
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#define CSL_APPSS_MCSPI_PER_CNT (1U)
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#define CSL_APPSS_I2C_CNT (1U)
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#define CSL_APPSS_LIN_CNT (1U)
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#define CSL_APPSS_QSPI_CNT (1U)
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#define CSL_APPSS_MCAN_CNT (1U)
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#define CSL_APPSS_PWM_CNT (1U)
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/*
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* This represents the maximum supported in a SOC across all instances of EDMA
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*/
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#define SOC_EDMA_NUM_DMACH (64U)
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#define SOC_EDMA_NUM_QDMACH (8U)
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#define SOC_EDMA_NUM_PARAMSETS (128U)
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#define SOC_EDMA_NUM_EVQUE (2U)
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#define SOC_EDMA_CHMAPEXIST (1U)
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#define SOC_EDMA_NUM_REGIONS (8)
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#define SOC_EDMA_MEMPROTECT (1U)
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#define MCAN_MSG_RAM_MAX_WORD_COUNT (4352U)
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#define MCAN_MAX_RX_DMA_BUFFERS (3U)
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#define MCAN_MAX_TX_DMA_BUFFERS (3U)
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/* ESM number of groups */
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#define ESM_NUM_GROUP_MAX (3U)
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#define ESM_NUM_INTR_PER_GROUP (128U)
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#define EDMA_APPSS_TPCC_A_EVT_SPI1_DMA_RX_REQ 0
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#define EDMA_APPSS_TPCC_A_EVT_SPI1_DMA_TX_REQ 1
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#define EDMA_APPSS_TPCC_A_EVT_SPI2_DMA_RX_REQ 2
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#define EDMA_APPSS_TPCC_A_EVT_SPI2_DMA_TX_REQ 3
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#define EDMA_APPSS_TPCC_A_EVT_SCI1_DMA_RX_REQ 4
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#define EDMA_APPSS_TPCC_A_EVT_SCI1_DMA_TX_REQ 5
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#define EDMA_APPSS_TPCC_A_EVT_LIN_DMA_RX_REQ 6
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#define EDMA_APPSS_TPCC_A_EVT_LIN_DMA_TX_REQ 7
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#define EDMA_APPSS_TPCC_A_EVT_MCAN_DMA_REQ0 8
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#define EDMA_APPSS_TPCC_A_EVT_MCAN_DMA_REQ1 9
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#define EDMA_APPSS_TPCC_A_EVT_MCAN_FE_INT1 10
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#define EDMA_APPSS_TPCC_A_EVT_MCAN_FE_INT2 11
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#define EDMA_APPSS_TPCC_A_EVT_MCAN_FE_INT3 12
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#define EDMA_APPSS_TPCC_A_EVT_MCAN_FE_INT4 13
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#define EDMA_APPSS_TPCC_A_EVT_MCAN_FE_INT5 14
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#define EDMA_APPSS_TPCC_A_EVT_MCAN_FE_INT6 15
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#define EDMA_APPSS_TPCC_A_EVT_MCAN_FE_INT7 16
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#define EDMA_APPSS_TPCC_A_EVT_I2C_DMA_REQ0 17
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#define EDMA_APPSS_TPCC_A_EVT_I2C_DMA_REQ1 18
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#define EDMA_APPSS_TPCC_A_GIO_INT0 19
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#define EDMA_APPSS_TPCC_A_GIO_INT1 20
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#define EDMA_APPSS_TPCC_A_APP_RTI1_DMA_REQ0 21
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#define EDMA_APPSS_TPCC_A_APP_RTI1_DMA_REQ1 22
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#define EDMA_APPSS_TPCC_A_APP_RTI1_DMA_REQ2 23
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#define EDMA_APPSS_TPCC_A_APP_RTI1_DMA_REQ3 24
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#define EDMA_APPSS_TPCC_A_APP_RTI2_DMA_REQ0 25
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#define EDMA_APPSS_TPCC_A_APP_RTI2_DMA_REQ1 26
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#define EDMA_APPSS_TPCC_A_APP_RTI2_DMA_REQ2 27
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#define EDMA_APPSS_TPCC_A_APP_RTI2_DMA_REQ3 28
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#define EDMA_APPSS_TPCC_A_MCRC_DMA_REQ0 29
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#define EDMA_APPSS_TPCC_A_MCRC_DMA_REQ1 30
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#define EDMA_APPSS_TPCC_A_QSPI_DMA_REQ 31
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#define EDMA_APPSS_TPCC_A_PWM_DMA_REQ0 32
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#define EDMA_APPSS_TPCC_A_PWM_DMA_REQ1 33
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#define EDMA_APPSS_TPCC_A_SCI2_DMA_RX_REQ 34
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#define EDMA_APPSS_TPCC_A_SCI2_DMA_TX_REQ 35
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#define EDMA_APPSS_TPCC_A_FRAMETIMER_FRAME_START 36
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#define EDMA_APPSS_TPCC_A_CHIP_AVAIL_IRQ 37
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#define EDMA_APPSS_TPCC_A_CHIRPTIMER_CHIRP_END 38
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#define EDMA_APPSS_TPCC_A_CHIRPTIMER_CHIRP_START 39
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#define EDMA_APPSS_TPCC_A_CHIRPTIMER_FRAME_END 40
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#define EDMA_APPSS_TPCC_A_ADC_VALID_START 41
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#define EDMA_APPSS_TPCC_A_DTHE_SHA_DMA_REQ0 42
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#define EDMA_APPSS_TPCC_A_DTHE_SHA_DMA_REQ1 43
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#define EDMA_APPSS_TPCC_A_DTHE_SHA_DMA_REQ2 44
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#define EDMA_APPSS_TPCC_A_DTHE_SHA_DMA_REQ3 45
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#define EDMA_APPSS_TPCC_A_DTHE_SHA_DMA_REQ4 46
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#define EDMA_APPSS_TPCC_A_DTHE_SHA_DMA_REQ5 47
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#define EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ0 48
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#define EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ1 49
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#define EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ2 50
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#define EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ3 51
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#define EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ4 52
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#define EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ5 53
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#define EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ6 54
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#define EDMA_APPSS_TPCC_A_DTHE_AES_DMA_REQ7 55
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#define EDMA_APPSS_TPCC_A_EVT_FREE_0 56
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#define EDMA_APPSS_TPCC_A_FEC_INTR0 57
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#define EDMA_APPSS_TPCC_A_FEC_INTR1 58
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#define EDMA_APPSS_TPCC_A_FEC_INTR2 59
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#define EDMA_APPSS_TPCC_A_FEC_INTR3 60
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#define EDMA_APPSS_TPCC_A_EVT_FREE_1 61
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#define EDMA_APPSS_TPCC_A_SP1_SPI2_DMA_RX_REQ 62
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#define EDMA_APPSS_TPCC_A_SP1_SPI2_DMA_TX_REQ 63
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#define EDMA_APPSS_TPCC_B_EVT_FRAMETIMER_FRAME_START 0
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#define EDMA_APPSS_TPCC_B_EVT_CHIRP_AVAIL_IRQ 1
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#define EDMA_APPSS_TPCC_B_EVT_CHIRPTIMER_CHIRP_END 2
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#define EDMA_APPSS_TPCC_B_EVT_CHIRPTIMER_CHIRP_START 3
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#define EDMA_APPSS_TPCC_B_EVT_CHIRPTIMER_FRAME_END 4
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#define EDMA_APPSS_TPCC_B_EVT_ADC_VALID_START 5
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#define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ0 6
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#define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ1 7
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#define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ2 8
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#define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ3 9
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#define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ4 10
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#define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ5 11
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#define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ6 12
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#define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ7 13
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#define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ8 14
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#define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ9 15
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#define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ10 16
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#define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ11 17
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#define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ12 18
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#define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ13 19
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#define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ14 20
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#define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ15 21
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#define EDMA_APPSS_TPCC_B_EVT_HWA_LOOP_INT 22
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#define EDMA_APPSS_TPCC_B_EVT_HWA_PARAMDONE_INT 23
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#define EDMA_APPSS_TPCC_B_EVT_SPI1_DMA_RX_REQ 24
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#define EDMA_APPSS_TPCC_B_EVT_SPI1_DMA_TX_REQ 25
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#define EDMA_APPSS_TPCC_B_EVT_SPI2_DMA_RX_REQ 26
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#define EDMA_APPSS_TPCC_B_EVT_SPI2_DMA_TX_REQ 27
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#define EDMA_APPSS_TPCC_B_EVT_FREE_0 28
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#define EDMA_APPSS_TPCC_B_EVT_FREE_1 29
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#define EDMA_APPSS_TPCC_B_EVT_FREE_2 30
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#define EDMA_APPSS_TPCC_B_EVT_FREE_3 31
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#define EDMA_APPSS_TPCC_B_EVT_FREE_4 32
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#define EDMA_APPSS_TPCC_B_EVT_FREE_5 33
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#define EDMA_APPSS_TPCC_B_EVT_FREE_6 34
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#define EDMA_APPSS_TPCC_B_EVT_FREE_7 35
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#define EDMA_APPSS_TPCC_B_EVT_FREE_8 36
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#define EDMA_APPSS_TPCC_B_EVT_FREE_9 37
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#define EDMA_APPSS_TPCC_B_EVT_FREE_10 38
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#define EDMA_APPSS_TPCC_B_EVT_FREE_11 39
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#define EDMA_APPSS_TPCC_B_EVT_FREE_12 40
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#define EDMA_APPSS_TPCC_B_EVT_FREE_13 41
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#define EDMA_APPSS_TPCC_B_EVT_FREE_14 42
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#define EDMA_APPSS_TPCC_B_EVT_FREE_15 43
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#define EDMA_APPSS_TPCC_B_EVT_FREE_16 44
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#define EDMA_APPSS_TPCC_B_EVT_FREE_17 45
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#define EDMA_APPSS_TPCC_B_EVT_FREE_18 46
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#define EDMA_APPSS_TPCC_B_EVT_FREE_19 47
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#define EDMA_APPSS_TPCC_B_EVT_FREE_20 48
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#define EDMA_APPSS_TPCC_B_EVT_FREE_21 49
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#define EDMA_APPSS_TPCC_B_EVT_FREE_22 50
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#define EDMA_APPSS_TPCC_A_NUM_PARAM_SETS (128U)
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#define EDMA_APPSS_TPCC_A_NUM_DMA_CHANS (64U)
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#define EDMA_APPSS_TPCC_A_NUM_TC (2U)
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#define EDMA_APPSS_TPCC_B_NUM_PARAM_SETS (128U)
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#define EDMA_APPSS_TPCC_B_NUM_DMA_CHANS (64U)
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#define EDMA_APPSS_TPCC_B_NUM_TC (2U)
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#define EDMA_TPCC_ERRAGG_TPCC_EERINT__POS (0U)
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#define EDMA_TPCC_INTAGG_TPCC_INTG__POS (0U)
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#define EDMA_TPCC_ERRAGG_TPTC_MIN_ERR__POS (2U)
/* position of the lowest TC Id, others are higher */
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#define EDMA_APPSS_NUM_CC 4
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#define EDMA_APPSS_MAX_NUM_TC CSL_MAX(EDMA_APPSS_TPCC_A_NUM_TC, \
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CSL_MAX(EDMA_APPSS_TPCC_B_NUM_TC, \
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CSL_MAX(EDMA_APPSS_TPCC_C_NUM_TC, \
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EDMA_RCSS_TPCC_A_NUM_TC)))
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#define EDMA_MSS_NUM_CC 6
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#define EDMA_MSS_MAX_NUM_TC CSL_MAX(EDMA_MSS_TPCC_A_NUM_TC, \
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CSL_MAX(EDMA_MSS_TPCC_B_NUM_TC, \
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CSL_MAX(EDMA_APPSS_TPCC_A_NUM_TC, \
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CSL_MAX(EDMA_APPSS_TPCC_B_NUM_TC, \
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CSL_MAX(EDMA_APPSS_TPCC_C_NUM_TC, \
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EDMA_RCSS_TPCC_A_NUM_TC)))))
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/***********************************************************************
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* Peripheral number of instance definition
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***********************************************************************/
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#define HWA_NUM_INSTANCES (1U)
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#define SOC_HWA_NUM_MEM_BANKS (4U)
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#define SOC_HWA_NUM_PARAM_SETS (32U)
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#define SOC_HWA_NUM_DMA_CHANNEL (16U)
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#define SOC_HWA_MEM_SIZE (CSL_APP_HWA_BANK_SIZE * SOC_HWA_NUM_MEM_BANKS)
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/***********************************************************************
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* HWA Hardware trigger source definitions
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***********************************************************************/
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#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_0_LINE_END (0U)
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#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_1_LINE_END (1U)
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#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_2_LINE_END (2U)
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#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_3_LINE_END (3U)
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#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_4_LINE_END (4U)
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#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_5_LINE_END (5U)
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#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_6_LINE_END (6U)
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#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_7_LINE_END (7U)
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#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_FRAME_START_0 (8U)
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#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_FRAME_START_1 (9U)
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#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_0_LINE_END (10U)
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#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_1_LINE_END (11U)
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#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_2_LINE_END (12U)
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#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_3_LINE_END (13U)
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#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_4_LINE_END (14U)
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#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_5_LINE_END (15U)
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#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_6_LINE_END (16U)
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#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_7_LINE_END (17U)
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#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_FRAME_START_0 (18U)
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#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_FRAME_START_1 (19U)
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/***********************************************************************
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* MSS - CLOCK settings
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***********************************************************************/
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/* Sys_vclk : 160MHz */
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#define APPSS_SYS_VCLK 160000000U
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/* ========================================================================== */
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/* Structures and Enums */
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/* ========================================================================== */
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//#define ADDR_TRANSLATE_CPU_TO_HWA(x) (uint16_t)(((uint32_t)(x) - SOC_XWR18XX_MSS_HWA_MEM0_BASE_ADDRESS) & 0x0000FFFFU)
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/* None */
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/* ========================================================================== */
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/* Global Variables */
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/* ========================================================================== */
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/* None */
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/* ========================================================================== */
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/* Function Declarations */
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/* ========================================================================== */
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/* None */
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#ifdef __cplusplus
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}
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#endif
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#endif
/* CSLR_SOC_DEFINES_H_ */
source
drivers
hw_include
xwrL64xx
cslr_soc_defines.h
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