mmwavelink.h
1 /*************************************************************************************************
2  * FileName : mmwavelink.h
3  *
4  * Description : This file includes all the header files which needs to be included by application
5  *
6  *************************************************************************************************
7  * (C) Copyright 2014, Texas Instruments Incorporated. - TI web address www.ti.com
8  *------------------------------------------------------------------------------------------------
9  *
10  * Redistribution and use in source and binary forms, with or without modification, are permitted
11  * provided that the following conditions are met:
12  *
13  * Redistributions of source code must retain the above copyright notice, this list of
14  * conditions and the following disclaimer.
15  *
16  * Redistributions in binary form must reproduce the above copyright notice, this list of
17  * conditions and the following disclaimer in the documentation and/or other materials provided
18  * with the distribution.
19  *
20  * Neither the name of Texas Instruments Incorporated nor the names of its contributors may be
21  * used to endorse or promote products derived from this software without specific prior
22  * written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
25  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
26  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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33  *
34  */
35 
36 /*************************************************************************************************
37  * FILE INCLUSION PROTECTION
38  *************************************************************************************************
39  */
40 #ifndef MMWAVELINK_H
41 #define MMWAVELINK_H
42 /*LDRA_NOANALYSIS*/
356 /*LDRA_ANALYSIS*/
357 
358  /****************************************************************************************
359  * INCLUDE FILES
360  *****************************************************************************************
361  */
362 #include <stdint.h>
363 #include <stdio.h>
364 #include <ti/control/mmwavelink/include/rl_datatypes.h>
365 
366 #ifdef __cplusplus
367 extern "C" {
368 #endif
369 
370 /*****************************************************************************************
371  * MACRO DEFINITIONS
372  *****************************************************************************************
373  */
374 
375 /* Export Macro for DLL */
376 #if defined(WIN32) || defined(WIN32_) || defined(_MSC_VER)
377 #define MMWL_EXPORT __declspec(dllexport)
378 #else
379 #define MMWL_EXPORT
380 #endif
381 
383 #define RL_MMWAVELINK_VERSION "2.2.3.1.13.5.21"
384 #define RL_MMWAVELINK_VERSION_MAJOR (2U)
385 #define RL_MMWAVELINK_VERSION_MINOR (2U)
386 #define RL_MMWAVELINK_VERSION_BUILD (3U)
387 #define RL_MMWAVELINK_VERSION_DEBUG (1U)
388 #define RL_MMWAVELINK_VERSION_DAY (13U)
389 #define RL_MMWAVELINK_VERSION_MONTH (5U)
390 #define RL_MMWAVELINK_VERSION_YEAR (21U)
391 
393 #define RL_RET_CODE_OK ((rlReturnVal_t)0) /* no-error */
394 #define RL_RET_CODE_PROTOCOL_ERROR (-1) /* mmWaveLink Protocol error */
395 #define RL_RET_CODE_INVALID_INPUT (-2) /* invalid input from the application */
396 #define RL_RET_CODE_SELF_ERROR (-3) /* error in mmWaveLink itself */
397 #define RL_RET_CODE_RADAR_IF_ERROR (-4) /* Radar HW/SW interface error */
398 #define RL_RET_CODE_MALLOC_ERROR (-5) /* memory allocation error */
399 #define RL_RET_CODE_CRC_FAILED (-6) /* CRC value mismatched wrt
400  received data */
401 #define RL_RET_CODE_CHKSUM_FAILED (-7) /* Checksum value mismatched wrt to
402  received data */
403 #define RL_RET_CODE_RESP_TIMEOUT (-8) /* device failed to send response
404  within time */
405 #define RL_RET_CODE_FATAL_ERROR (-9) /* Fatal error internal to
406  mmWaveLink APIs */
407 #define RL_RET_CODE_RADAR_OSIF_ERROR (-10) /* OS interface failure */
408 #define RL_RET_CODE_INVALID_STATE_ERROR (-11) /* Invalid state within mmWaveLink */
409 #define RL_RET_CODE_API_NOT_SUPPORTED (-12) /* API called is not supported */
410 #define RL_RET_CODE_MSGID_MISMATCHED (-13) /* Message-ID mismatched in
411  response data */
412 #define RL_RET_CODE_NULL_PTR (-14) /* Null pointer error */
413 #define RL_RET_CODE_INTERFACE_CB_NULL (-15) /* Interface callback passed as NULL */
414 #define RL_RET_CODE_NACK_ERROR (-16) /* If device sends NACK message */
415 #define RL_RET_CODE_HOSTIRQ_TIMEOUT (-17) /* If post writing CNYS HostIRQ is not
416  down within time limit and re-writing
417  CNYS also has same result */
418 #define RL_RET_CODE_RX_SEQ_NUM_NOT_MATCH (-18) /* ACK sequence number is not matching with
419  CMD sequence number */
420 
422 #define RL_RET_CODE_INVLD_OPCODE (1U) /* Incorrect opcode/Msg ID */
423 #define RL_RET_CODE_INVLD_NUM_SB (2U) /* Incorrect no. of Sub-Block */
424 #define RL_RET_CODE_INVLD_SB_ID (3U) /* Incorrect Sub-Block ID */
425 #define RL_RET_CODE_INVLD_SB_LEN (4U) /* Incorrect Sub-Block Length */
426 #define RL_RET_CODE_SB_INVL_DATA (5U) /* Incorrect Sub-Block Data */
427 #define RL_RET_CODE_SB_PROCESS_ERR (6U) /* Error in Sub Block processing */
428 #define RL_RET_CODE_MISMATCH_FILE_CRC (7U) /* Mismatch in File CRC */
429 #define RL_RET_CODE_MISMATCH_FILE_TYPE (8U) /* Mismatch in File Type */
430 
432 #define RL_RET_CODE_FRAME_ALREADY_STARTED (20U) /* Frames are already started when the
433  FRAME_START command was issued */
434 #define RL_RET_CODE_FRAME_ALREADY_ENDED (21U) /* Frames are already stopped when the
435  FRAME_STOP command was issued */
436 #define RL_RET_CODE_FRAME_CFG_NOT_RECVD (22U) /* No valid frame configuration API was
437  issued and frames are started */
438 #define RL_RET_CODE_FRAME_TRIG_INVL_IN (23U) /* START_STOP_CMD parameter is out of
439  range*/
440 
442 #define RL_RET_CODE_CH_CFG_RX_INVAL_IN (24U) /* RX_CHAN_EN parameter is out of range
443  may vary based on device */
444 #define RL_RET_CODE_CH_CFG_TX_INVAL_IN (25U) /* TX_CHAN_EN parameter is out of range
445  may vary based on device */
446 #define RL_RET_CODE_CH_CFG_CASC_INVAL_IN (26U) /* CASCADING_CFG parameter is out of
447  range [0, 2] */
448 
450 #define RL_RET_CODE_ADC_BITS_INVAL_IN (27U) /* NUM_ADC_BITS parameter is out of
451  range [0, 2] */
452 #define RL_RET_CODE_ADC_FORM_INVAL_IN (28U) /* ADC_OUT_FMT parameter is out of
453  range [0, 3] */
454 
456 #define RL_RET_CODE_LP_ADC_INVAL_IN (29U) /* LP_ADC_MODE parameter is out of
457  range [0, 1] */
458 
460 #define RL_RET_CODE_DYN_PS_INVAL_IN (30U) /* BLOCK_CFG parameter is out of
461  range [0, 7] */
462 
464 #define RL_RET_CODE_HSI_DIV_INVAL_IN (31U) /* HSI clock rate code[1:0] is 0 */
465 #define RL_RET_CODE_RESERVED0 (32U)
466 #define RL_RET_CODE_HSI_DIV_INVAL_1IN (33U) /* HSI clock rate code[3:2] is 3 &
467  HSI clock rate code[1:0] is 2 */
468 #define RL_RET_CODE_HSI_DIV_INVAL_2IN (34U) /* HSI clock rate code[3:2] is 3 &
469  HSI clock rate code[1:0] is 2 */
470 
472 #define RL_RET_CODE_PF_IND_INVAL_IN (35U) /* PF indx >= 4 */
473 #define RL_RET_CODE_PF_START_FREQ_INVAL_IN (36U) /* PF freq const is not
474  with[76GHz,81GHz] in limit */
475 #define RL_RET_CODE_PF_IDLE_TIME_INVAL_IN (37U) /* PF idle time const > 5.24ms */
476 #define RL_RET_CODE_PF_IDLE_TIME_1INVAL_IN (38U) /* Maximum DFE spill time (refer
477  rampgen calculator in mmWaveStudio
478  for more details) > PF idle
479  time const */
480 #define RL_RET_CODE_PF_ADC_START_INVAL_IN (39U) /* PF ADC start time const > 4095 */
481 #define RL_RET_CODE_PF_RAMP_END_INVAL_IN (40U) /* PF ramp end time > 524287 */
482 #define RL_RET_CODE_PF_RAMP_END_1INVAL_IN (41U) /* PF ramp end time < PF ADC start
483  time const + ADC sampling time */
484 #define RL_RET_CODE_PF_TX0_INVAL_IN (42U) /* PF_TX_OUTPUT_POWER_BACKOFF for
485  TX0 > 30 */
486 #define RL_RET_CODE_PF_TX1_INVAL_IN (43U) /* PF_TX_OUTPUT_POWER_BACKOFF for
487  TX1 > 30 */
488 #define RL_RET_CODE_PF_TX2_INVAL_IN (44U) /* PF_TX_OUTPUT_POWER_BACKOFF for
489  TX2 > 30 */
490 #define RL_RET_CODE_RESERVED1 (45U)
491 #define RL_RET_CODE_PF_FREQ_SLOPE_1INVAL_IN (46U) /* Ramp end freq is not
492  with[76GHz,81GHz] in limits */
493 #define RL_RET_CODE_PF_TX_START_INVAL_IN (47U) /* Absolute value of TX_START_TIME
494  is > 38.45us */
495 #define RL_RET_CODE_PF_NUM_ADC_SMAP_INVAL_IN (48U) /* Number of ADC samples is not
496  within [2,8192] */
497 #define RL_RET_CODE_PF_DFE_SAMP_RATE_INVAL_IN (49U) /* Output sampling rate is not
498  within [2, 37.5]Msps */
499 #define RL_RET_CODE_PF_HPF1_CF_INVAL_IN (50U) /* HPF1 corner frequency > 700 kHz */
500 #define RL_RET_CODE_PF_HPF2_CF_INVAL_IN (51U) /* HPF2 corner frequency > 2.8 MHz */
501 #define RL_RET_CODE_PF_RX_GAIN_INVAL_IN (52U) /* PF_RX_GAIN is not within [24, 52] dB
502  orPF_RX_GAIN is an odd number */
503 #define RL_RET_CODE_RESERVED2 (53U)
504 #define RL_RET_CODE_RESERVED3 (54U)
505 #define RL_RET_CODE_RESERVED4 (55U)
506 #define RL_RET_CODE_RESERVED5 (56U)
507 #define RL_RET_CODE_RESERVED6 (57U)
508 #define RL_RET_CODE_RESERVED7 (58U)
509 
511 #define RL_RET_CODE_CHIRP_START_INVAL_IN (59U) /* Chirp Start indx >= 512 */
512 #define RL_RET_CODE_CHIRP_END_INVAL_IN (60U) /* Chirp End indx >= 512 */
513 #define RL_RET_CODE_CHIRP_END_1INVAL_IN (61U) /* Chirp Start indx > Chirp End indx */
514 #define RL_RET_CODE_CHIRP_PF_IND_INVAL_IN (62U) /* PF indx >= 4 */
515 #define RL_RET_CODE_CHIRP_PF_IND_1INVAL_IN (63U) /* PF corresponding to PF indx is not
516  defined */
517 #define RL_RET_CODE_CHIRP_START_FREQ_INVAL_IN (64U) /* Chirp freq start > 8388607 */
518 #define RL_RET_CODE_CHIRP_SLOPE_INVAL_IN (65U) /* Chirp freq slope > 63 */
519 #define RL_RET_CODE_CHIRP_SLOPE_1INVAL_IN (66U) /* Chirp start or end
520  freq[76GHz,81GHz] is outside */
521 #define RL_RET_CODE_CHIRP_IDLE_TIME_INVAL_IN (67U) /* Chirp Idle time > 4095 */
522 #define RL_RET_CODE_CHIRP_ADC_START_INVAL_IN (68U) /* Chirp ADC start time > 4095 */
523 #define RL_RET_CODE_CHIRP_ADC_START_1INVAL_IN (69U) /* Ramp end time < ADC start time +
524  ADC sampling time */
525 #define RL_RET_CODE_CHIRP_TX_ENA_INVAL_IN (70U) /* Chirp TX enable > 7 */
526 #define RL_RET_CODE_CHIRP_TX_ENA_1INVAL_IN (71U) /* Chirp TX enable indicates to enable
527  a TX which is not enabled in
528  Channel config */
529 
531 #define RL_RET_CODE_FRAME_CHIRP_STR_INVAL_IN (72U) /* Chirp Start indx >= 512 */
532 #define RL_RET_CODE_FRAME_CHIRP_END_INVAL_IN (73U) /* Chirp End indx >= 512 */
533 #define RL_RET_CODE_FRAME_CHIRP_END_1INVAL_IN (74U) /* Chirp Start indx > Chirp End indx */
534 #define RL_RET_CODE_FRAME_CHIRP_END_2INVAL_IN (75U) /* Chirp used in frame is not
535  configured by Chirp config */
536 #define RL_RET_CODE_FRAME_CHIRP_PF_INVAL_IN (76U) /* Profile used in frame is not
537  configured by PF config */
538 #define RL_RET_CODE_FRAME_CHIRP_LOOPS_INVAL_IN (77U) /* No. of loops is outside[1,255] */
539 #define RL_RET_CODE_RESERVED8 (78U)
540 #define RL_RET_CODE_FRAME_PERIOD_INVAL_IN (79U) /* Frame periodicity is
541  outside[100us,1.342s] */
542 #define RL_RET_CODE_FRAME_PERIOD_1INVAL_IN (80U) /* Frame ON time > Frame periodicity */
543 #define RL_RET_CODE_FRAME_TRIG_SEL_INVAL_IN (81U) /* Trigger select is outside[1,2] */
544 #define RL_RET_CODE_FRAME_TRIG_DELAY_INVAL_IN (82U) /* Frame Trigger delay > 100us */
545 #define RL_RET_CODE_FRAME_IS_ONGOING (83U) /* API issued when frame is ongoing */
546 #define RL_RET_CODE_FRAME_DUMMY_CHIRPS_INVAL_IN (160U) /* The Dummy chirps at end of frame
547  is not supported */
548 
550 #define RL_RET_CODE_AFRAME_NUM_SUBF_INVAL_IN (84U) /* No. Sub Frames is outside[1,4] */
551 #define RL_RET_CODE_AFRAME_FORCE_PF_INVAL_IN (85U) /* Force single Profile is
552  outside[1,4] */
553 #define RL_RET_CODE_AFRAME_PF_IND_INVAL_IN (86U) /* Force single Profile >= 4 */
554 #define RL_RET_CODE_AFRAME_PF_IND_1INVAL_IN (87U) /* Profile defined by Force Single
555  Profile is not defined */
556 #define RL_RET_CODE_AFRAME_CHIRP_STR_INVAL_IN (88U) /* Sub Frame Chirp Start indx >= 512 */
557 #define RL_RET_CODE_AFRAME_NCHIRP_INVAL_IN (89U) /* Sub Frame NO. of unique chirps per
558  Burst is outside[1,512] */
559 #define RL_RET_CODE_AFRAME_NCHIRP_1INVAL_IN (90U) /* Chirp used in frame is not
560  configured by Chirp config */
561 #define RL_RET_CODE_AFRAME_CHIRP_PF_INVAL_IN (91U) /* Profie used in the frame is not
562  configured by profile config */
563 #define RL_RET_CODE_AFRAME_CHIRP_LOOPS_INVAL_IN (92U) /* Sub Frame No. of loops is
564  outside[1,225] */
565 #define RL_RET_CODE_AFRAME_BURST_PERIOD_INVAL_IN (93U) /* Sub Frame burst period is
566  outside[100us,1.342s] */
567 #define RL_RET_CODE_AFRAME_BURST_PER_1INVAL_IN (94U) /* Burst ON time > Burst period */
568 #define RL_RET_CODE_AFRAME_BURST_STIND_INVAL_IN (95U) /* Sub Frame Chirp start indx
569  offset >= 512 */
570 #define RL_RET_CODE_AFRAME_BURST_SIND_1INVAL_IN (96U) /* Sub Frame Chirp start indx >= 512
571  or (Sub Frame Chirp start indx +
572  Sub Frame No. unique Chirps per
573  burst - 1) >= 512*/
574 #define RL_RET_CODE_AFRAME_NUM_BURSTS_INVAL_IN (97U) /* Sub Frame No. bursts is
575  outside[1,512] */
576 #define RL_RET_CODE_AFRAME_BURST_LOOPS_INVAL_IN (98U) /* Sub Frame No. outer loops is
577  outside[1,64] */
578 #define RL_RET_CODE_AFRAME_SF_PERIOD_INVAL_IN (99U) /* Sub Frame period is
579  outside[100us,1.342s] */
580 #define RL_RET_CODE_AFRAME_SF_PERIOD_1INVAL_IN (100U) /* Sub Frame ontime > Sub Frame period
581  or when test source enabled, Sub
582  Frame idale time < 150us */
583 #define RL_RET_CODE_RESERVED9 (101U)
584 #define RL_RET_CODE_AFRAME_TRIG_SEL_INVAL_IN (102U) /* Trigger select is outside[1,2] */
585 #define RL_RET_CODE_AFRAME_TRIG_DELAY_INVAL_IN (103U) /* Frame trigger delay is > 100us */
586 #define RL_RET_CODE_AFRAME_IS_ONGOING (104U) /* API issued when frame is ongoing */
587 
589 #define RL_RET_CODE_TS_POS_VECY_INVAL_IN (105U) /* position vector x[y] < 0 */
590 #define RL_RET_CODE_RESERVED10 (106U)
591 #define RL_RET_CODE_TS_VEL_VECXYZ_INVAL_IN (107U) /* position vector x[x] < 5000 or
592  position vector x[y] < 5000 or
593  position vector x[x] < 5000 */
594 #define RL_RET_CODE_TS_SIG_LEVEL_INVAL_IN (108U) /* SIG_LEV_VECx > 950 */
595 #define RL_RET_CODE_TS_RX_ANT_POS_INVAL_IN (109U) /* RX_ANT_POS_XZ[Bytex] > 120 */
596 #define RL_RET_CODE_RESERVED11 (110U)
597 
599 #define RL_RET_CODE_PROG_FILT_STARTINDX_INVALID (111U) /* Prog. Filter coefficient start
600  indx is odd number */
601 #define RL_RET_CODE_PROG_FILT_PROFILE_INVALID (112U) /* Pro indx >= 4 */
602 #define RL_RET_CODE_PROG_FILT_UNSUPPORTED_DEV (113U) /* API issued for non AWR1642 device*/
603 
605 #define RL_RET_CODE_PERCHIRPPHSHIFT_UNSUPPORTED_DEV (114U) /* API issued for non AWR1243/AWR2243
606  device */
607 #define RL_RET_CODE_PERCHIRPPHSHIFT_STIND (115U) /* Chirp Start indx >= 512 */
608 #define RL_RET_CODE_PERCHIRPPHSHIFT_ENIND (116U) /* Chirp End indx >= 512 */
609 #define RL_RET_CODE_PERCHIRPPHSHIFT_WRONG_STIND (117U) /* Chirp Start indx > End indx */
610 
612 #define RL_RET_CODE_RF_INIT_NOT_DONE (118U) /* Boot time calibrations are not
613  done so cannot run runtime calibrations */
614 #define RL_RET_CODE_FORCE_TEMP_BIN_IDX_INVALID (286U) /* The forced temperature bin index
615  is invalid */
616 #define RL_RET_CODE_FREQ_LIMIT_OUT_RANGE (119U) /* Freq. is outside[76GHz,81GHz] or
617  Freq. low limit > high limit */
618 #define RL_RET_CODE_CAL_MON_TIME_INVALID (120U) /* CALIB_MON_TIME_UNIT <= 0 */
619 #define RL_RET_CODE_RUN_CAL_PERIOD_INVALID (121U) /* CALIBRATION_ PERIODICITY = 0 */
620 #define RL_RET_CODE_CONT_STREAM_MODE_EN (122U) /* API is issued when continuous
621  streaming mode is on */
622 #define RL_RET_CODE_RX_GAIN_BOOT_CAL_NOT_DONE (123U) /* RX gain run time calibration was
623  requested but boot time calibration
624  was not performed */
625 #define RL_RET_CODE_LO_DIST_BOOT_CAL_NOT_DONE (124U) /* LO distribution run time
626  calibration was requested but boot time
627  calibration was not performed */
628 #define RL_RET_CODE_TX_PWR_BOOT_CAL_NOT_DONE (125U) /* TX power run time calibration was
629  requested but boot time calibration
630  was not performed */
631 #define RL_RET_CODE_PROG_FILTR_UNSUPPORTED_DFEMODE (126U) /* DFE mode is pseudo real */
632 #define RL_RET_CODE_ADC_BITS_FULL_SCALE_REDUC_INVAL (127U) /* FULL_SCALE_REDUCTION_FACTOR is > 0
633  for 16 bit ADC, or > 2 for 14 bit
634  ADC mode or > 4 for 12 bit ADC mode */
635 #define RL_RET_CODE_CAL_MON_NUM_CASC_DEV_INVALID (128U) /* NUM_OF_CASCADED_DEV <= 0 */
636 #define RL_RET_CODE_FRAME_TRIG_INVL_STOP_IN (129U)/* Frame stop option-4 cannot be used
637  in SW Triggered mode */
638 #define RL_RET_CODE_RF_FREQBAND_INVALID (130U) /* Minimum RF frequency is < 200MHz */
639 
641 #define RL_RET_CODE_INVAL_LOOPBACK_TYPE (132U)
642 #define RL_RET_CODE_INVAL_LOOPBACK_BURST_IND (133U)
643 #define RL_RET_CODE_INVAL_LOOPBACK_CONFIG (134U)
644 #define RL_RET_CODE_DYN_CHIRP_INVAL_SEG (135U)
645 #define RL_RET_CODE_DYN_PERCHIRP_PHSHFT_INVA_SEG (136U)
646 #define RL_RET_CODE_INVALID_CAL_CHUNK_ID (137U)
647 #define RL_RET_CODE_INVALID_CAL_CHUNK_DATA (138U)
648 
650 #define RL_RET_CODE_RX02_RF_TURN_OFF_TIME_INVALID (139U) /* RX02_RF_TURN_OFF_TIME is not
651  within the range [-1024, 1023] */
652 #define RL_RET_CODE_RX13_RF_TURN_OFF_TIME_INVALID (140U) /* RX13_RF_TURN_OFF_TIME is not
653  within the range [-1024, 1023] */
654 #define RL_RET_CODE_RX02_BB_TURN_OFF_TIME_INVALID (141U) /* RX02_BB_TURN_OFF_TIME is not
655  within the range [-1024, 1023] */
656 #define RL_RET_CODE_RX13_BB_TURN_OFF_TIME_INVALID (142U) /* RX13_BB_TURN_OFF_TIME is not
657  within the range [-1024, 1023] */
658 #define RL_RET_CODE_RX02_RF_PREENABLE_TIME_INVALID (143U) /* RX02_RF_PREENABLE_TIME is not
659  within the range [-1024, 1023] */
660 #define RL_RET_CODE_RX13_RF_PREENABLE_TIME_INVALID (144U) /* RX13_RF_PREENABLE_TIME is not
661  within the range [-1024, 1023] */
662 #define RL_RET_CODE_RX02_BB_PREENABLE_TIME_INVALID (145U) /* RX02_BB_PREENABLE_TIME is not
663  within the range [-1024, 1023] */
664 #define RL_RET_CODE_RX13_BB_PREENABLE_TIME_INVALID (146U) /* RX13_BB_PREENABLE_TIME is not
665  within the range [-1024, 1023] */
666 #define RL_RET_CODE_RX02_RF_TURN_ON_TIME_INVALID (147U) /* RX02_RF_TURN_ON_TIME is not
667  within the range [-1024, 1023] */
668 #define RL_RET_CODE_RX13_RF_TURN_ON_TIME_INVALID (148U) /* RX13_RF_TURN_ON_TIME is not
669  within the range [-1024, 1023] */
670 #define RL_RET_CODE_RX02_BB_TURN_ON_TIME_INVALID (149U) /* RX02_BB_TURN_ON_TIME is not
671  within the range [-1024, 1023] */
672 #define RL_RET_CODE_RX13_BB_TURN_ON_TIME_INVALID (150U) /* RX13_BB_TURN_ON_TIME is not
673  within the range [-1024, 1023] */
674 #define RL_RET_CODE_RX_LO_TURN_OFF_TIME_INVALID (151U) /* RX_LO_TURN_OFF_TIME is not
675  within the range [-1024, 1023] */
676 #define RL_RET_CODE_TX_LO_TURN_OFF_TIME_INVALID (152U) /* TX_LO_TURN_OFF_TIME is not
677  within the range [-1024, 1023] */
678 #define RL_RET_CODE_RX_LO_TURN_ON_TIME_INVALID (153U) /* RX_LO_TURN_ON_TIME is not
679  within the range [-1024, 1023] */
680 #define RL_RET_CODE_TX_LO_TURN_ON_TIME_INVALID (154U) /* TX_LO_TURN_ON_TIME is not
681  within the range [-1024, 1023] */
682 #define RL_RET_CODE_SUBFRAME_TRIGGER_INVALID (155U) /* Sub frame trigger option is not
683  enabled but sub frame trigger API
684  is issued or frame is configured
685  for software trigger mode and
686  sub-frame trigger API is issued */
687 #define RL_RET_CODE_REGULAR_ADC_MODE_INVALID (156U) /* Regular ADC mode is issued on a
688  5 MHz part variant */
689 #define RL_RET_CODE_CHIRP_ROW_SELECT_INVAL_IN (159U) /* Chirp row select is not with in
690  the range [0x00, 0x30] */
691 
692 #define RL_RET_CODE_DEVICE_NOT_ASILB_TYPE (250U) /* Device type is not ASILB */
693 #define RL_RET_CODE_FRAME_ONGOING (251U) /* Fault injection API or Digital
694  latent fault API is issued when
695  frames are ongoing */
696 #define RL_RET_CODE_INVLD_REPO_MODE (252U) /* Invalid reporting mode */
697 #define RL_RET_CODE_INVLD_PROFILE_ID (253U) /* Configured profile ID is not
698  within [0,3] */
699 #define RL_RET_CODE_INVLD_PROFILE (254U) /* Monitoring profile ID is not
700  configured yet */
701 #define RL_RET_CODE_INVLD_EXTSIG_SETLTIME (255U) /* Settling time is configured is
702  more than 12us */
703 #define RL_RET_CODE_INVLD_NO_RX_ENABLED (256U) /* None of the RXs are enabled */
704 #define RL_RET_CODE_INVLD_TX0_NOT_ENABLED (257U) /* TX0 is not enabled */
705 #define RL_RET_CODE_INVLD_TX1_NOT_ENABLED (258U) /* TX1 is not enabled */
706 #define RL_RET_CODE_INVLD_TX2_NOT_ENABLED (259U) /* TX2 is not enabled */
707 #define RL_RET_CODE_MON_INVALID_RF_BIT_MASK (260U) /* Invalid RF bit mask */
708 #define RL_RET_CODE_RESERVED12 (261U)
709 #define RL_RET_CODE_RESERVED13 (262U)
710 #define RL_RET_CODE_MON_TX_EN_CHK_FAIL (263U) /* Monitored TX is not enabled */
711 #define RL_RET_CODE_MON_RX_CH_EN_CHK_FAIL (264U) /* Monitored RX is not enabled */
712 #define RL_RET_CODE_MON_TX_CH_PS_LB (265U) /* TX selected for RX gain phase
713  monitor is TX2 (Only TX0 or TX1 is
714  allowed) */
715 #define RL_RET_CODE_INVLD_SAT_MON_SEL (266U) /* SAT_MON_SEL is not in [0, 3] */
716 #define RL_RET_CODE_INVLD_SAT_MON_PRI_SLICE_DUR (267U) /* SAT_MON_PRIMARY_TIME_SLICE_DURATION
717  is less than 0.64us or greater
718  than ADC sampling time */
719 #define RL_RET_CODE_INVLD_SAT_MON_NUM_SLICES (268U) /* SAT_MON_NUM_SLICES is 0 or
720  greater than 127 */
721 #define RL_RET_CODE_INVLD_SIG_IMG_SLICENUM (269U) /* SIG_IMG_MON_NUM_SLICES is 0 or
722  greater than 127 */
723 #define RL_RET_CODE_INVLD_SIG_IMG_NUMSAMPPERSLICE (270U) /* NUM_SAMPLES_ PER_PRIMARY_TIME_SLICE
724  is odd, or less than 4 in Complex1x
725  mode or less than 8 in non-Complex1x
726  modes or greater than NUM_ADC_SAMPLES*/
727 #define RL_RET_CODE_INVLD_SYNTH_L1_LIN (271U)
728 #define RL_RET_CODE_INVLD_SYNTH_L2_LIN (272U)
729 #define RL_RET_CODE_INVLD_SYNTH_N_LIN (273U)
730 #define RL_RET_CODE_INVLD_SYNTH_MON_START_TIME (274U) /* MONITOR_START_TIME is outside the
731  specified range. */
732 #define RL_RET_CODE_INVLD_SYNTH_MON_LIN_RAM_ADDR (275U)
733 #define RL_RET_CODE_LDO_BYPASSED (279U) /* LDO fault inject is requested but
734  LDOs are bypassed */
735 #define RL_RET_CODE_INVLD_SIG_IMG_BAND_MONTR (280U) /* Signal and image band monitor is
736  not supported */
737 #define RL_RET_CODE_ANALOG_MONITOR_NOT_SUPPORTED (281U)
738 #define RL_RET_CODE_ISSUE_TO_ENABLE_CASCASE_MODE (282U) /* Device variant does not allow
739  cascading but API is issued to
740  enable cascading mode */
741 #define RL_RET_CODE_RX_SAT_MON_NOT_SUPPORTED (283U)
742 #define RL_API_NRESP_ANA_MON_MODE_NOT_API_BASED (284U) /* Monitoring trigger API is not
743  supported in autonomous mode
744  of operation */
745 #define RL_API_NRESP_ANA_MON_TRIG_TYPE_INVALID (285U) /* Monitoring trigger bit masks
746  are all zeros in
747  AWR_MONITOR_TYPE_TRIG_CONF_SB */
748 
749 #define RL_RET_CODE_CHIRP_FAIL (290U) /* Monitoring chirp error */
750 #define RL_RET_CODE_PD_PWR_LVL (291U) /* Loopback power measured by PD
751  is below -40 dBm */
752 #define RL_RET_CODE_ADC_PWR_LVL (292U) /* ADC power is higher than 7 dBm */
753 #define RL_RET_CODE_NOISE_FIG_LOW (293U) /* Noise figure is less than 0 */
754 #define RL_RET_CODE_PD_CDS_ON_FAIL (294U) /* PD measurement with RF on is less
755  than with RF off */
756 #define RL_RET_CODE_PGA_GAIN_FAIL (295U) /* Incorrect PGA gain for monitoring*/
757 #define RL_RET_CODE_20G_MONITOR_NOT_SUPPORTED (296U) /* The 20G monitor is not supported
758  in single chip configuration */
759 #define RL_RET_CODE_MONITOR_CONFIG_MODE_INVALID (297U) /* MONITOR_CONFIG_MODE is invalid. */
760 #define RL_RET_CODE_LIVE_NONLIVE_TOGETHER_INVALID (298U) /* Both Live and Non-live synth
761  frequency monitors are cannot be
762  enabled together. */
763 
764 /* Advanced Chirp config API */
765 #define RL_RET_CODE_CHIRP_PARAM_IND_INVALID (300U) /* Invalid CHIRP_PARAM_INDEX */
766 #define RL_RET_CODE_RESET_MODE_INVALID (301U) /* Invalid GLOBAL_RESET_MODE */
767 #define RL_RET_CODE_DEL_LUT_PAR_UPT_PER_INVALID (303U) /* Invalid update period
768  DELTA_PARAM_UPDATE_PERIOD or
769  LUT_PARAM_UPDATE_PERIOD */
770 #define RL_RET_CODE_SF_CHIRP_PAR_DEL_INVALID (304U) /* Invalid fixed delta parameter
771  SFn_CHIRP_PARAM_DELTA */
772 #define RL_RET_CODE_DEL_LUT_RESET_PERIOD_INVALID (305U) /* Invalid reset period
773  DELTA_RESET_PERIOD or
774  LUT_RESET_PERIOD*/
775 #define RL_RET_CODE_LUT_PAT_ADD_OFF_INVALID (306U) /* Invalid LUT address
776  LUT_PATTERN_ADDRESS_OFFSET */
777 #define RL_RET_CODE_LUT_NUM_PATTERNS_INVALID (307U) /* Invalid number of patterns in
778  LUT NUM_OF_PATTERNS */
779 #define RL_RET_CODE_LUT_SF_BURST_IND_OFF_INVALID (308U) /* Invalid LUT index offset value
780  BURST_LUT_INDEX_OFFSET or
781  SF_LUT_INDEX_OFFSET */
782 #define RL_RET_CODE_LUT_CHIRP_PAR_SCALE_SIZE_INVALID (309U) /* Invalid LUT_CHIRP_PARAM_SIZE and
783  LUT_CHIRP_PARAM_SCALE */
784 #define RL_RET_CODE_LEGACY_API_INPUTS_INVALID (310U) /* Invalid legacy APIs are issued
785  when advance chirp config API is
786  enabled or vice-versa */
787 #define RL_RET_CODE_ALL_CHIRP_PARAMS_NOT_DEFINED (311U) /* All chirp parameters are not
788  defined in advance chirp API */
789 #define RL_RET_CODE_TX_PHASE_SHIF_INT_INVALID (312U) /* Invalid TX phase shifter dither
790  value */
791 #define RL_RET_CODE_NUM_PATTERNS_PROGRAM_INVALID (313U) /* Insufficient number of
792  NUM_OF_PATTERNS programmed compared
793  to actual programmed chirps
794  (array out of bound error) */
795 #define RL_RET_CODE_NUM_CHIRPS_PROGRAM_INVALID (315U) /* Invalid num of chirps programmed
796  in frame config API */
797 #define RL_RET_CODE_TX_PH_SHIFT_PHASE_MASK_INVALID (316U) /* Invalid phase mask or at least one
798  of the phase should be enabled for
799  monitoring */
800 #define RL_RET_CODE_TX_PH_SHIFT_RX_MASK_INVALID (317U) /* Invalid RX mask or the RX mask is
801  not enabled in channel
802  configuration API */
803 
804 /* Advanced Chirp Generic LUT Load API */
805 #define RL_RET_CODE_NUM_BYTES_PROGRAM_INVALID (314U) /* Invalid num of bytes */
806 
807 #define RL_RET_CODE_TX_IND_PH_SHIFT_RESTORE_INVALID (318U) /* Invalid TX index in phase shifter
808  restore API */
809 #define RL_RET_CODE_INVLD_MON_START_FREQ (319U) /* Invalid monitoring start
810  frequency */
811 #define RL_RET_CODE_VCO3_MONITOR_UNSUPPORTED_DEV (320U) /* Synth VCO3 not suppported for the
812  device issued */
813 #define RL_RET_CODE_INVLD_STATE_TRANS_CMD (325U) /* Invalid state transition command
814  received */
815 
816 /* ADC Config API */
817 #define RL_RET_CODE_RX_CHAN_EN_OOR (1001U) /* numADCBits out of Range */
818 #define RL_RET_CODE_NUM_ADC_BITS_OOR (1002U) /* rxChannelEn out of Range */
819 #define RL_RET_CODE_ADC_OUT_FMT_OOR (1003U) /* adcOutFormat out of Range */
820 #define RL_RET_CODE_IQ_SWAP_SEL_OOR (1004U) /* sampleInterleave out of
821  Range */
822 #define RL_RET_CODE_CHAN_INTERLEAVE_OOR (1005U) /* channelInterleave out of
823  Range */
824 
825 /* Data Path Config API */
826 #define RL_RET_CODE_DATA_INTF_SEL_OOR (1006U) /* dataIntfSel out of Range */
827 #define RL_RET_CODE_DATA_FMT_PKT0_INVALID (1007U) /* dataTransPkt0Format
828  Unsupporetd */
829 #define RL_RET_CODE_DATA_FMT_PKT1_INVALID (1008U) /* dataTransPkt1Format
830  Unsupporetd */
831 
832 /* Lane Enable config API */
833 #define RL_RET_CODE_LANE_ENABLE_OOR (1009U) /* laneEnable is out of range */
834 #define RL_RET_CODE_LANE_ENABLE_INVALID (1010U) /* laneEnable is not supported */
835 
836 /* Lane Clock config API */
837 #define RL_RET_CODE_LANE_CLK_CFG_OOR (1011U) /* laneClkCfg is out of range */
838 #define RL_RET_CODE_LANE_CLK_CFG_INVALID (1012U) /* laneClkCfg is not supported */
839 #define RL_RET_CODE_DATA_RATE_OOR (1013U) /* dataRate is out of range */
840 
841 /* LVDS config API */
842 #define RL_RET_CODE_LANE_FMT_MAP_OOR (1014U) /* laneFmtMap is out of range */
843 #define RL_RET_CODE_LANE_PARAM_CFG_OOR (1015U) /* laneParamCfg is out of range */
844 
845 /* Continuous Streaming Mode API */
846 #define RL_RET_CODE_CONT_STREAM_MODE_OOR (1016U) /* contStreamMode is out of
847  range */
848 #define RL_RET_CODE_CONT_STREAM_MODE_INVALID (1017U) /* contStreamMode is already
849  in requested mode */
850 
851 /* CSI2 Lane Config API */
852 #define RL_RET_CODE_LANE0_POS_POL_OOR (1018U) /* lane0 pos is out of range */
853 #define RL_RET_CODE_LANE1_POS_POL_OOR (1019U) /* lane1 pos is out of range */
854 #define RL_RET_CODE_LANE2_POS_POL_OOR (1020U) /* lane2 pos is out of range */
855 #define RL_RET_CODE_LANE3_POS_POL_OOR (1021U) /* lane3 pos is out of range */
856 #define RL_RET_CODE_CLOCK_POS_OOR (1022U) /* ClockPos is out of range */
857 
858 /* Frame Config Apply API */
859 #define RL_RET_CODE_HALF_WORDS_PER_CHIRP_OOR (1023U) /* adcOutSize is out of range */
860 
861 /* Advanced Frame Config API */
862 #define RL_RET_CODE_NUM_SUBFRAMES_OOR (1024U) /* numSubFrames is out of range */
863 
864 #define RL_RET_CODE_SF1_TOT_NUM_CHIRPS_OOR (1025U) /* totNumChirps is out of range */
865 #define RL_RET_CODE_SF1_NUM_ADC_SAMP_OOR (1026U) /* numADCSamplesInPkt is out
866  of range */
867 #define RL_RET_CODE_SF1_NUM_CHIRPS_OOR (1027U) /* numChirpsInPkt is out of
868  range */
869 
870 #define RL_RET_CODE_SF2_TOT_NUM_CHIRPS_OOR (1028U) /* totNumChirps is out of
871  range */
872 #define RL_RET_CODE_SF2_NUM_ADC_SAMP_OOR (1029U) /* numADCSamplesInPkt is out
873  of range */
874 #define RL_RET_CODE_SF2_NUM_CHIRPS_OOR (1030U) /* numChirpsInPkt is out of
875  range */
876 
877 #define RL_RET_CODE_SF3_TOT_NUM_CHIRPS_OOR (1031U) /* totNumChirps is out of
878  range */
879 #define RL_RET_CODE_SF3_NUM_ADC_SAMP_OOR (1032U) /* numADCSamplesInPkt is out of
880  range */
881 #define RL_RET_CODE_SF3_NUM_CHIRPS_OOR (1033U) /* numChirpsInPkt is out of
882  range */
883 
884 #define RL_RET_CODE_SF4_TOT_NUM_CHIRPS_OOR (1034U) /* totNumChirps is out of
885  range */
886 #define RL_RET_CODE_SF4_NUM_ADC_SAMP_OOR (1035U) /* numADCSamplesInPkt is out of
887  range */
888 #define RL_RET_CODE_SF4_NUM_CHIRPS_OOR (1036U) /* numChirpsInPkt is out of range */
889 
890 #define RL_RET_CODE_MCUCLOCK_CTRL_OOR (1040U) /* mcuClkOutEn is out of range */
891 #define RL_RET_CODE_MCUCLOCK_SRC_OOR (1041U) /* mcuClkOutSrc is out of range */
892 
893 #define RL_RET_CODE_PMICCLOCK_CTRL_OOR (1042U) /* pmicClkOutEn is out of range */
894 #define RL_RET_CODE_PMICCLOCK_SRC_OOR (1043U) /* pmicClkOutSrc is out of range */
895 #define RL_RET_CODE_PMICMODE_SELECT_OOR (1044U) /* modeSel is out of range */
896 #define RL_RET_CODE_PMICFREQ_SLOPE_OOR (1045U) /* freqSlope is out of range */
897 #define RL_RET_CODE_PMICCLK_DITHER_EN_OOR (1046U) /* clkDitherEn is out of range */
898 
899 #define RL_RET_CODE_TESTPATTERN_EN_OOR (1047U) /* testPatternGenEn is out of
900  range */
901 #define RL_RET_CODE_LFAULTTEST_UNSUPPORTED_OOR (1048U) /* Data interface selected in
902  RL_DEV_RX_DATA_PATH_CONF_SET_SB
903  is SPI */
904 
905 #define RL_API_NRESP_LFAULTTEST_UNSUPPORTED_OOR (1051U) /* Unsupported Latent Fault test
906  selected in
907  RL_DEV_LATENTFAULT_TEST_CONF_SB */
908 #define RL_API_NRESP_DATACONFIG_NOTDONE (1052U) /* Invoking
909  AWR_DEV_ADV_FRAME_CONFIG_APPLY_SB
910  message without configuring
911  data path */
912 
918 #define RL_DISABLE_LOGGING 1
919 
920 /* mmwavelink MACROs for Error Checks */
921 #define RL_OSI_RET_CODE_OK (0)
922 #define RL_IF_RET_CODE_OK (0)
923 
924 #ifdef RL_EXTENDED_MESSAGE /* build time MACRO to change message size */
925 /* if mmWaveLink instance is running inside xWR1443/1642 device then Max size of packet can
926  be (2048 -4) bytes, where 4 bytes are reserved for mailbox header */
927 #define RL_MAX_SIZE_MSG (2044U)
928 #else
929 #define RL_MAX_SIZE_MSG (256U)
930 #endif
931 
932 
943 #define RL_DEVICE_MAP_NATIVE (0U)
944 #define RL_DEVICE_MAP_CASCADED_1 (1U)
945 #define RL_DEVICE_MAP_CASCADED_2 (2U)
946 #define RL_DEVICE_MAP_CASCADED_3 (4U)
947 #define RL_DEVICE_MAP_CASCADED_4 (8U)
949 /* AWR2243/xWR6243 Device Map - Max Cascading */
950 #define RL_DEVICE_MAP_CASCADED_ALL (RL_DEVICE_MAP_CASCADED_1 |\
951  RL_DEVICE_MAP_CASCADED_2 |\
952  RL_DEVICE_MAP_CASCADED_3 |\
953  RL_DEVICE_MAP_CASCADED_4)
954 
955 /* Device Index for SubSystem */
956 #define RL_DEVICE_INDEX_INTERNAL_BSS (0U)
957 #define RL_DEVICE_INDEX_INTERNAL_DSS_MSS (1U)
958 #define RL_DEVICE_INDEX_INTERNAL_HOST (2U)
961 #define RL_DEVICE_MAP_INTERNAL_BSS (RL_DEVICE_MAP_CASCADED_1)
963 #define RL_DEVICE_MAP_INTERNAL_DSS_MSS (RL_DEVICE_MAP_CASCADED_2)
964 #define RL_DEVICE_MAP_INTERNAL_HOST (RL_DEVICE_MAP_CASCADED_3)
967 #define RL_DEVICE_CONNECTED_MAX (4U)
968 
984 #ifndef RL_CASCADE_NUM_DEVICES
985 #define RL_CASCADE_NUM_DEVICES (1U)
986 #endif
987 
991 #define RL_CRC_TYPE_16BIT_CCITT (0U)
992 #define RL_CRC_TYPE_32BIT (1U)
993 #define RL_CRC_TYPE_64BIT_ISO (2U)
994 #define RL_CRC_TYPE_NO_CRC (3U)
999 #define RL_PLATFORM_HOST (0x0U)
1000 #define RL_PLATFORM_MSS (0x1U)
1001 #define RL_PLATFORM_DSS (0x2U)
1006 #define RL_AR_DEVICETYPE_12XX (0x0U)
1007 #define RL_AR_DEVICETYPE_14XX (0x1U)
1008 #define RL_AR_DEVICETYPE_16XX (0x2U)
1009 #define RL_AR_DEVICETYPE_18XX (0x3U)
1010 #define RL_AR_DEVICETYPE_68XX (0x4U)
1011 #define RL_AR_DEVICETYPE_22XX (0x5U)
1016 #define RL_DBG_LEVEL_NONE ((rlUInt8_t)0U)
1017 #define RL_DBG_LEVEL_DATABYTE ((rlUInt8_t)1U)
1018 #define RL_DBG_LEVEL_ERROR ((rlUInt8_t)2U)
1019 #define RL_DBG_LEVEL_WARNING ((rlUInt8_t)3U)
1020 #define RL_DBG_LEVEL_INFO ((rlUInt8_t)4U)
1021 #define RL_DBG_LEVEL_DEBUG ((rlUInt8_t)5U)
1022 #define RL_DBG_LEVEL_VERBOSE ((rlUInt8_t)6U)
1023 
1027 #define RL_SENSOR_ANALOGTEST_ONE (0U)
1028 #define RL_SENSOR_ANALOGTEST_TWO (1U)
1029 #define RL_SENSOR_ANALOGTEST_THREE (2U)
1030 #define RL_SENSOR_ANALOGTEST_FOUR (3U)
1031 #define RL_SENSOR_ANAMUX (4U)
1032 #define RL_SENSOR_VSENSE (5U)
1033 #define RL_MAX_GPADC_SENSORS (6U)
1034 
1038 #define RL_SWAP_32(x) (((x) & 0x0000FFFFU)<<16U)|(((x) & 0xFFFF0000U)>>16U);
1039 
1040 /******************************************************************************
1041  * TYPE-DEFINE STRUCT/ENUM/UNION DEFINITIONS
1042  ******************************************************************************
1043  */
1044 
1045 /* DesignId : MMWL_DesignId_001 */
1046 /* Requirements : AUTORADAR_REQ-697, AUTORADAR_REQ-698, AUTORADAR_REQ-699, AUTORADAR_REQ-700,
1047  AUTORADAR_REQ-701, AUTORADAR_REQ-702, AUTORADAR_REQ-703, AUTORADAR_REQ-704,
1048  AUTORADAR_REQ-705, AUTORADAR_REQ-706, AUTORADAR_REQ-830, AUTORADAR_REQ-831,
1049  AUTORADAR_REQ-832, AUTORADAR_REQ-888, AUTORADAR_REQ-889, AUTORADAR_REQ-890
1050 */
1051 
1055 typedef rlInt32_t rlReturnVal_t;
1056 
1060 typedef rlUInt8_t rlCrcType_t;
1061 
1062 /* Function pointers for spawn task function and event handlers*/
1063 
1067 typedef void (*RL_P_OSI_SPAWN_ENTRY)(const void* pValue);
1068 
1072 typedef void (*RL_P_EVENT_HANDLER)(rlUInt8_t deviceIndex, void* pValue);
1073 
1077 typedef struct rlComIfCbs
1078 {
1089  /* DesignId : MMWL_DesignId_004 */
1090  /* Requirements : AUTORADAR_REQ-785 */
1091  rlComIfHdl_t (*rlComIfOpen)(rlUInt8_t deviceIndex, rlUInt32_t flags);
1092 
1104  /* DesignId : MMWL_DesignId_004 */
1105  /* Requirements : AUTORADAR_REQ-785 */
1106  rlInt32_t (*rlComIfRead)(rlComIfHdl_t fd, rlUInt8_t *pBuff, rlUInt16_t len);
1107 
1119  /* DesignId : */
1120  /* Requirements : AUTORADAR_REQ-785 */
1121  rlInt32_t (*rlComIfWrite)(rlComIfHdl_t fd, rlUInt8_t *pBuff, rlUInt16_t len);
1122 
1132  /* DesignId : MMWL_DesignId_004 */
1133  /* Requirements : AUTORADAR_REQ-785 */
1134  rlInt32_t (*rlComIfClose)(rlComIfHdl_t fd);
1135 }rlComIfCbs_t;
1136 
1140 typedef struct rlOsiMutexCbs
1141 {
1152  /* DesignId : MMWL_DesignId_004 */
1153  /* Requirements : AUTORADAR_REQ-784 */
1154  rlInt32_t (*rlOsiMutexCreate)(rlOsiMutexHdl_t* mutexHdl, rlInt8_t* name);
1155 
1178  /* DesignId : MMWL_DesignId_004 */
1179  /* Requirements : AUTORADAR_REQ-784 */
1180  rlInt32_t (*rlOsiMutexLock)(rlOsiMutexHdl_t* mutexHdl, rlOsiTime_t timeout);
1181 
1192  /* DesignId : MMWL_DesignId_004 */
1193  /* Requirements : AUTORADAR_REQ-784 */
1194  rlInt32_t (*rlOsiMutexUnLock)(rlOsiMutexHdl_t* mutexHdl);
1195 
1205  /* DesignId : MMWL_DesignId_004 */
1206  /* Requirements : AUTORADAR_REQ-784 */
1207  rlInt32_t (*rlOsiMutexDelete)(rlOsiMutexHdl_t* mutexHdl);
1209 
1213 typedef struct rlOsiSemCbs
1214 {
1225  /* DesignId : MMWL_DesignId_004 */
1226  /* Requirements : AUTORADAR_REQ-784 */
1227  rlInt32_t (*rlOsiSemCreate)(rlOsiSemHdl_t* semHdl, rlInt8_t* name);
1228 
1239  /* DesignId : MMWL_DesignId_004 */
1240  /* Requirements : AUTORADAR_REQ-784 */
1241  rlInt32_t (*rlOsiSemWait)(rlOsiSemHdl_t* semHdl, rlOsiTime_t timeout);
1242 
1252  /* DesignId : MMWL_DesignId_004 */
1253  /* Requirements : AUTORADAR_REQ-784 */
1254  rlInt32_t (*rlOsiSemSignal)(rlOsiSemHdl_t* semHdl);
1255 
1265  /* DesignId : MMWL_DesignId_004 */
1266  /* Requirements : AUTORADAR_REQ-784 */
1267  rlInt32_t (*rlOsiSemDelete)(rlOsiSemHdl_t* semHdl);
1268 }rlOsiSemCbs_t;
1269 
1273 typedef struct rlOsiMsgQCbs
1274 {
1290  /* DesignId : MMWL_DesignId_004 */
1291  /* Requirements : AUTORADAR_REQ-784 */
1292  rlInt32_t (*rlOsiSpawn)(RL_P_OSI_SPAWN_ENTRY pEntry, const void* pValue, rlUInt32_t flags);
1294 
1295 
1299 typedef struct rlOsiCbs
1300 {
1304  rlOsiMutexCbs_t mutex;
1308  rlOsiSemCbs_t sem;
1312  rlOsiMsgQCbs_t queue;
1313 }rlOsiCbs_t;
1314 
1318 typedef struct rlEventCbs
1319 {
1333  /* DesignId : MMWL_DesignId_004 */
1334  /* Requirements : AUTORADAR_REQ-783 */
1335  void (*rlAsyncEvent)(rlUInt8_t devIndex, rlUInt16_t subId, rlUInt16_t subLen,
1336  rlUInt8_t *payload);
1337 }rlEventCbs_t;
1342 typedef struct rlTimerCbs
1343 {
1344  rlInt32_t (*rlDelay)(rlUInt32_t delay);
1346 
1350 typedef struct rlCmdParserCbs
1351 {
1352  rlInt32_t (*rlCmdParser)(rlUInt8_t rxMsgClass, rlInt32_t inVal);
1353  rlInt32_t (*rlPostCnysStep)(rlUInt8_t devIndex);
1355 
1362 typedef struct rlCrcCbs
1363 {
1378  /* DesignId : */
1379  /* Requirements : */
1380  rlInt32_t (*rlComputeCRC)(rlUInt8_t* data, rlUInt32_t dataLen, rlUInt8_t crcType,
1381  rlUInt8_t* crc);
1382 }rlCrcCbs_t;
1383 
1387 typedef struct rlDeviceCtrlCbs
1388 {
1399  /* DesignId : MMWL_DesignId_004 */
1400  /* Requirements : AUTORADAR_REQ-786 */
1401  rlInt32_t (*rlDeviceEnable)(rlUInt8_t deviceIndex);
1402 
1413  /* DesignId : MMWL_DesignId_004 */
1414  /* Requirements : AUTORADAR_REQ-786 */
1415  rlInt32_t (*rlDeviceDisable)(rlUInt8_t deviceIndex);
1416 
1425  /* DesignId : MMWL_DesignId_004 */
1426  /* Requirements : AUTORADAR_REQ-787 */
1427  void (*rlDeviceMaskHostIrq)(rlComIfHdl_t fd);
1428 
1437  /* DesignId : MMWL_DesignId_004 */
1438  /* Requirements : AUTORADAR_REQ-787 */
1439  void (*rlDeviceUnMaskHostIrq)(rlComIfHdl_t fd);
1440 
1456  /* DesignId :MMWL_DesignId_004 */
1457  /* Requirements : AUTORADAR_REQ-787 */
1458  rlInt32_t (*rlDeviceWaitIrqStatus)(rlComIfHdl_t fd, rlUInt8_t highLow);
1459 
1469  /* DesignId : MMWL_DesignId_004 */
1470  /* Requirements : AUTORADAR_REQ-787 */
1471  rlUInt16_t (*rlCommIfAssertIrq)(rlUInt8_t highLow);
1472 
1488  /* DesignId : MMWL_DesignId_026 */
1489  /* Requirements : AUTORADAR_REQ-777 */
1490  rlInt32_t (*rlRegisterInterruptHandler)(rlUInt8_t deviceIndex,
1491  RL_P_EVENT_HANDLER pHandler, void* pValue);
1496 typedef rlInt32_t (*rlPrintFptr)(const rlInt8_t* format, ...);
1497 
1501 typedef struct rlDbgCb
1502 {
1514  /* DesignId : */
1515  /* Requirements : */
1516  rlPrintFptr rlPrint;
1520  rlUInt8_t dbgLevel;
1521 }rlDbgCb_t;
1522 
1526 typedef struct rlClientCbs
1527 {
1531  rlComIfCbs_t comIfCb;
1535  rlOsiCbs_t osiCb;
1539  rlEventCbs_t eventCb;
1543  rlDeviceCtrlCbs_t devCtrlCb;
1547  rlTimerCbs_t timerCb;
1552  rlCmdParserCbs_t cmdParserCb;
1556  rlCrcCbs_t crcCb;
1560  rlCrcType_t crcType;
1566  rlUInt32_t ackTimeout;
1572  rlUInt8_t platform;
1577  rlUInt8_t arDevType;
1581  rlDbgCb_t dbgCb;
1582 }rlClientCbs_t;
1583 
1591 /* Sub block ID: 0x5000, ICD API: AWR_AE_DEV_MSSPOWERUPDONE_SB */
1592 typedef struct rlInitComplete
1593 {
1597  rlUInt32_t powerUpTime;
1634  rlUInt32_t powerUpStatus1;
1658  rlUInt32_t powerUpStatus2;
1695  rlUInt32_t bootTestStatus1;
1706  rlUInt32_t bootTestStatus2;
1708 
1713  /* Sub block ID: 0x5001, ICD API: AWR_AE_DEV_RFPOWERUPDONE_SB */
1714 typedef struct rlStartComplete
1715 {
1748  rlUInt32_t status;
1752  rlUInt32_t powerUpTime;
1756  rlUInt32_t reserved0;
1760  rlUInt32_t reserved1;
1762 
1769  /* Sub block ID: 0x5003, ICD API: AWR_AE_MSS_ESMFAULT_STATUS_SB */
1770 typedef struct rlMssEsmFault
1771 {
1807  rlUInt32_t esmGrp1Err;
1843  rlUInt32_t esmGrp2Err;
1847  rlUInt32_t reserved0;
1851  rlUInt32_t reserved1;
1853 
1860  /* Sub block ID: 0x5005, ICD API: AWR_AE_MSS_BOOTERRORSTATUS_SB */
1861 typedef struct rlMssBootErrStatus
1862 {
1866  rlUInt32_t powerUpTime;
1903  rlUInt32_t powerUpStatus1;
1927  rlUInt32_t powerUpStatus2;
1964  rlUInt32_t bootTestStatus1;
1975  rlUInt32_t bootTestStatus2;
1977 
1982  /* Sub block ID: 0x5006, ICD API: AWR_AE_MSS_LATENTFAULT_TESTREPORT_SB */
1983 typedef struct rlMssLatentFaultReport
1984 {
2021  rlUInt32_t testStatusFlg1;
2032  rlUInt32_t testStatusFlg2;
2036  rlUInt32_t reserved;
2038 
2044  /* Sub block ID: 0x5007, ICD API: AWR_AE_MSS_PERIODICTEST_STATUS_SB */
2045 typedef struct rlMssPeriodicTestStatus
2046 {
2054  rlUInt32_t testStatusFlg;
2058  rlUInt32_t reserved;
2060 
2066  /* Sub block ID: 0x5008, ICD API: AWR_AE_MSS_RFERROR_STATUS_SB */
2067 typedef struct rlMssRfErrStatus
2068 {
2080  rlUInt32_t errStatusFlg;
2084  rlUInt32_t reserved;
2086 
2093  /* Sub block ID: 0x1003, ICD API: AWR_AE_RF_ESMFAULT_SB */
2094 typedef struct rlBssEsmFault
2095 {
2123  rlUInt32_t esmGrp1Err;
2159  rlUInt32_t esmGrp2Err;
2161 
2165 /* Sub block ID: 0x1004, ICD API: AWR_AE_RF_INITCALIBSTATUS_SB */
2166 typedef struct rlRfInitComplete
2167 {
2189  rlUInt32_t calibStatus;
2194  rlUInt32_t calibUpdate;
2200  rlUInt16_t temperature;
2204  rlUInt16_t reserved0;
2210  rlUInt32_t timeStamp;
2214  rlUInt32_t reserved1;
2216 
2220  /* Sub block ID: 0x1012, ICD API: AWR_RUN_TIME_CALIB_SUMMARY_REPORT_AE_SB */
2221 typedef struct rlRfRunTimeCalibReport
2222 {
2243  rlUInt32_t calibErrorFlag;
2249  rlUInt32_t calibUpdateStatus;
2257  rlInt16_t temperature;
2261  rlUInt16_t reserved0;
2267  rlUInt32_t timeStamp;
2271  rlUInt32_t reserved1;
2273 
2283 /* Sub block ID: 0x100A, ICD API: AWR_AE_RF_MONITOR_TYPE_TRIGGER_DONE_SB */
2284 typedef struct rlMonTypeTrigDoneStatus
2285 {
2286 #ifndef MMWL_BIG_ENDIAN
2295  rlUInt8_t monTrigTypeDone;
2299  rlUInt8_t reserved0;
2300 #else
2301 
2304  rlUInt8_t reserved0;
2313  rlUInt8_t monTrigTypeDone;
2314 #endif
2315 
2318  rlUInt16_t reserved1;
2323  rlUInt32_t timeStamp;
2327  rlUInt32_t reserved2;
2329 
2333 typedef struct rlRfApllCalDone
2334 {
2335  rlUInt16_t apllClCalStatus;
2339  rlUInt16_t cccTolerance;
2343  rlUInt16_t cccCount0;
2347  rlUInt16_t measFreqCount;
2351  rlUInt32_t cccCount1;
2353 
2362  /* Sub block ID: 0x1002, ICD API: AWR_AE_RF_CPUFAULT_SB */
2363  /* Sub block ID: 0x5002, ICD API: AWR_AE_MSS_CPUFAULT_SB */
2364 typedef struct rlCpuFault
2365 {
2366 #ifndef MMWL_BIG_ENDIAN
2378  rlUInt8_t faultType;
2395  rlUInt8_t errorCode;
2396 #else
2397 
2413  rlUInt8_t errorCode;
2425  rlUInt8_t faultType;
2426 #endif
2427 
2431  rlUInt16_t lineNum;
2436  rlUInt32_t faultLR;
2442  rlUInt32_t faultPrevLR;
2447  rlUInt32_t faultSpsr;
2451  rlUInt32_t faultSp;
2456  rlUInt32_t faultAddr;
2469  rlUInt16_t faultErrStatus;
2470 #ifndef MMWL_BIG_ENDIAN
2471 
2477  rlUInt8_t faultErrSrc;
2483  rlUInt8_t faultAxiErrType;
2489  rlUInt8_t faultAccType;
2496  rlUInt8_t faultRecovType;
2497 #else
2498 
2503  rlUInt8_t faultAxiErrType;
2510  rlUInt8_t faultErrSrc;
2517  rlUInt8_t faultRecovType;
2523  rlUInt8_t faultAccType;
2524 #endif
2525 
2528  rlUInt16_t reserved1;
2529 }rlCpuFault_t;
2530 
2534 typedef struct rlFwVersionParam
2535 {
2536 #ifndef MMWL_BIG_ENDIAN
2540  rlUInt8_t hwVarient;
2544  rlUInt8_t hwMajor;
2548  rlUInt8_t hwMinor;
2552  rlUInt8_t fwMajor;
2556  rlUInt8_t fwMinor;
2560  rlUInt8_t fwBuild;
2564  rlUInt8_t fwDebug;
2568  rlUInt8_t fwYear;
2572  rlUInt8_t fwMonth;
2576  rlUInt8_t fwDay;
2580  rlUInt8_t patchMajor;
2584  rlUInt8_t patchMinor;
2588  rlUInt8_t patchYear;
2592  rlUInt8_t patchMonth;
2596  rlUInt8_t patchDay;
2602  rlUInt8_t patchBuildDebug;
2603 #else
2604 
2607  rlUInt8_t hwMajor;
2611  rlUInt8_t hwVarient;
2615  rlUInt8_t fwMajor;
2619  rlUInt8_t hwMinor;
2623  rlUInt8_t fwBuild;
2627  rlUInt8_t fwMinor;
2631  rlUInt8_t fwYear;
2635  rlUInt8_t fwDebug;
2639  rlUInt8_t fwDay;
2643  rlUInt8_t fwMonth;
2647  rlUInt8_t patchMinor;
2651  rlUInt8_t patchMajor;
2655  rlUInt8_t patchMonth;
2659  rlUInt8_t patchYear;
2665  rlUInt8_t patchBuildDebug;
2669  rlUInt8_t patchDay;
2670 #endif
2672 
2676 typedef struct rlSwVersionParam
2677 {
2678 #ifndef MMWL_BIG_ENDIAN
2682  rlUInt8_t major;
2686  rlUInt8_t minor;
2690  rlUInt8_t build;
2694  rlUInt8_t debug;
2698  rlUInt8_t year;
2702  rlUInt8_t month;
2706  rlUInt8_t day;
2710  rlUInt8_t reserved;
2711 #else
2712 
2715  rlUInt8_t minor;
2719  rlUInt8_t major;
2723  rlUInt8_t debug;
2727  rlUInt8_t build;
2731  rlUInt8_t month;
2735  rlUInt8_t year;
2739  rlUInt8_t reserved;
2743  rlUInt8_t day;
2744 #endif
2746 
2750 typedef struct rlVersion
2751 {
2755  rlFwVersionParam_t master;
2759  rlFwVersionParam_t rf;
2763  rlSwVersionParam_t mmWaveLink;
2764 }rlVersion_t;
2765 
2769 typedef struct rlGpAdcData
2770 {
2774  rlUInt16_t min;
2778  rlUInt16_t max;
2782  rlUInt16_t avg;
2783 } rlGpAdcData_t;
2784 
2788 /* Sub block ID: 0x100C, ICD API: AWR_AE_RF_GPADC_RESULT_DATA_SB */
2789 typedef struct rlRecvdGpAdcData
2790 {
2794  rlGpAdcData_t sensor[RL_MAX_GPADC_SENSORS];
2798  rlUInt16_t reserved0[4U];
2802  rlUInt32_t reserved1[7U];
2804 
2808 /* Sub block ID: 0x1010, ICD API: AWR_ANALOGFAULT_AE_SB */
2809 typedef struct rlAnalogFaultReportData
2810 {
2811 #ifndef MMWL_BIG_ENDIAN
2819  rlUInt8_t faultType;
2823  rlUInt8_t reserved0;
2824 #else
2825 
2828  rlUInt8_t reserved0;
2836  rlUInt8_t faultType;
2837 #endif
2838 
2841  rlUInt16_t reserved1;
2851  rlUInt32_t faultSig;
2855  rlUInt32_t reserved2;
2857 
2862 /* Sub block ID: 0x1011, ICD API: AWR_CAL_MON_TIMING_FAIL_REPORT_AE_SB */
2863 typedef struct rlCalMonTimingErrorReportData
2864 {
2878  rlUInt16_t timingFailCode;
2879  rlUInt16_t reserved;
2885 /* Sub block ID: 0x1013, ICD API: AWR_MONITOR_RF_DIG_LATENTFAULT_REPORT_AE_SB */
2886 typedef struct rlDigLatentFaultReportData
2887 {
2919  rlUInt32_t digMonLatentFault;
2921 
2926 /* Sub block ID: 0x1015, ICD API: AWR_MONITOR_REPORT_HEADER_AE_SB */
2927 typedef struct rlMonReportHdrData
2928 {
2932  rlUInt32_t fttiCount;
2937  rlUInt16_t avgTemp;
2941  rlUInt16_t reserved0;
2945  rlUInt32_t reserved1;
2947 
2952 /* Sub block ID: 0x1016, ICD API: AWR_MONITOR_RF_DIG_PERIODIC_REPORT_AE_SB */
2953 typedef struct rlDigPeriodicReportData
2954 {
2964  rlUInt32_t digMonPeriodicStatus;
2970  rlUInt32_t timeStamp;
2972 
2979 /* Sub block ID: 0x1017, ICD API: AWR_MONITOR_TEMPERATURE_REPORT_AE_SB */
2980 typedef struct rlMonTempReportData
2981 {
2994  rlUInt16_t statusFlags;
2998  rlUInt16_t errorCode;
3016  rlInt16_t tempValues[10U];
3020  rlUInt32_t reserved;
3026  rlUInt32_t timeStamp;
3028 
3036 /* Sub block ID: 0x1018, ICD API: AWR_MONITOR_RX_GAIN_PHASE_REPORT_AE_SB */
3037 typedef struct rlMonRxGainPhRep
3038 {
3050  rlUInt16_t statusFlags;
3054  rlUInt16_t errorCode;
3055 #ifndef MMWL_BIG_ENDIAN
3056 
3059  rlUInt8_t profIndex;
3073  rlUInt8_t loopbackPowerRF1;
3087  rlUInt8_t loopbackPowerRF2;
3101  rlUInt8_t loopbackPowerRF3;
3102 #else
3103 
3116  rlUInt8_t loopbackPowerRF1;
3120  rlUInt8_t profIndex;
3134  rlUInt8_t loopbackPowerRF3;
3148  rlUInt8_t loopbackPowerRF2;
3149 #endif
3150 
3170  rlUInt16_t rxGainVal[12U];
3185  rlUInt16_t rxPhaseVal[12U];
3208  rlUInt32_t rxNoisePower1;
3231  rlUInt32_t rxNoisePower2;
3237  rlUInt32_t timeStamp;
3239 
3247 /* Sub block ID: 0x1019, ICD API: AWR_MONITOR_RX_NOISE_FIGURE_REPORT_AE_SB */
3248 typedef struct rlMonRxNoiseFigRep
3249 {
3258  rlUInt16_t statusFlags;
3262  rlUInt16_t errorCode;
3263 #ifndef MMWL_BIG_ENDIAN
3264 
3267  rlUInt8_t profIndex;
3271  rlUInt8_t reserved0;
3272 #else
3273 
3276  rlUInt8_t reserved0;
3280  rlUInt8_t profIndex;
3281 #endif
3282 
3285  rlUInt16_t reserved1;
3299  rlUInt16_t rxNoiseFigVal[12U];
3303  rlUInt32_t reserved2;
3307  rlUInt32_t reserved3;
3311  rlUInt32_t reserved4;
3317  rlUInt32_t timeStamp;
3319 
3326 /* Sub block ID: 0x101A, ICD API: AWR_MONITOR_RX_IFSTAGE_REPORT_AE_SB */
3327 typedef struct rlMonRxIfStageRep
3328 {
3339  rlUInt16_t statusFlags;
3343  rlUInt16_t errorCode;
3344 #ifndef MMWL_BIG_ENDIAN
3345 
3348  rlUInt8_t profIndex;
3352  rlUInt8_t reserved0;
3353 #else
3354 
3357  rlUInt8_t reserved0;
3361  rlUInt8_t profIndex;
3362 #endif
3363 
3373  rlInt16_t lpfCutOffBandEdgeDroopValRx0;
3374 #ifndef MMWL_BIG_ENDIAN
3375 
3391  rlInt8_t hpfCutOffFreqEr[8U];
3405  rlInt8_t lpfCutOffStopBandAtten[8U];
3419  rlInt8_t rxIfaGainErVal[8U];
3424  rlInt8_t ifGainExp;
3428  rlUInt8_t reserved2;
3441  rlInt8_t lpfCutOffBandEdgeDroopValRx[6U];
3442 #else
3443 
3459  rlInt8_t hpfCutOffFreqEr[8U];
3473  rlInt8_t lpfCutOffStopBandAtten[8U];
3487  rlInt8_t rxIfaGainErVal[8U];
3491  rlUInt8_t reserved2;
3496  rlInt8_t ifGainExp;
3509  rlInt8_t lpfCutOffBandEdgeDroopValRx[6U];
3510 #endif
3511 
3515  rlUInt32_t timeStamp;
3517 
3525 /* Sub block ID: 0x101B, ICD API: AWR_MONITOR_TX0_POWER_REPORT_AE_SB */
3526 /* Sub block ID: 0x101C, ICD API: AWR_MONITOR_TX1_POWER_REPORT_AE_SB */
3527 /* Sub block ID: 0x101D, ICD API: AWR_MONITOR_TX2_POWER_REPORT_AE_SB */
3528 typedef struct rlMonTxPowRep
3529 {
3539  rlUInt16_t statusFlags;
3543  rlUInt16_t errorCode;
3544 #ifndef MMWL_BIG_ENDIAN
3545 
3548  rlUInt8_t profIndex;
3552  rlUInt8_t reserved0;
3553 #else
3554 
3557  rlUInt8_t reserved0;
3561  rlUInt8_t profIndex;
3562 #endif
3563 
3566  rlUInt16_t reserved1;
3578  rlInt16_t txPowVal[3U];
3582  rlUInt16_t reserved2;
3588  rlUInt32_t timeStamp;
3590 
3599 /* Sub block ID: 0x101E, ICD API: AWR_MONITOR_TX0_BALLBREAK_REPORT_AE_SB */
3600 /* Sub block ID: 0x101F, ICD API: AWR_MONITOR_TX1_BALLBREAK_REPORT_AE_SB */
3601 /* Sub block ID: 0x1020, ICD API: AWR_MONITOR_TX2_BALLBREAK_REPORT_AE_SB */
3602 typedef struct rlMonTxBallBreakRep
3603 {
3612  rlUInt16_t statusFlags;
3616  rlUInt16_t errorCode;
3621  rlInt16_t txReflCoefVal;
3625  rlUInt16_t reserved0;
3629  rlUInt32_t reserved1;
3635  rlUInt32_t timeStamp;
3637 
3644 /* Sub block ID: 0x1021, ICD API: AWR_MONITOR_TX_GAIN_PHASE_MISMATCH_REPORT_AE_SB */
3645 typedef struct rlMonTxGainPhaMisRep
3646 {
3656  rlUInt16_t statusFlags;
3660  rlUInt16_t errorCode;
3661 #ifndef MMWL_BIG_ENDIAN
3662 
3665  rlUInt8_t profIndex;
3671  rlUInt8_t noisePower00;
3677  rlUInt8_t noisePower01;
3683  rlUInt8_t noisePower02;
3684 #else
3685 
3690  rlUInt8_t noisePower00;
3694  rlUInt8_t profIndex;
3700  rlUInt8_t noisePower02;
3706  rlUInt8_t noisePower01;
3707 #endif
3708 
3720  rlInt16_t txGainVal[9U];
3736  rlUInt16_t txPhaVal[9U];
3737 #ifndef MMWL_BIG_ENDIAN
3738 
3743  rlUInt8_t noisePower10;
3749  rlUInt8_t noisePower11;
3755  rlUInt8_t noisePower12;
3761  rlUInt8_t noisePower20;
3767  rlUInt8_t noisePower21;
3773  rlUInt8_t noisePower22;
3777  rlUInt8_t reserved0;
3781  rlUInt8_t reserved1;
3782 #else
3783 
3788  rlUInt8_t noisePower11;
3794  rlUInt8_t noisePower10;
3800  rlUInt8_t noisePower20;
3806  rlUInt8_t noisePower12;
3812  rlUInt8_t noisePower22;
3818  rlUInt8_t noisePower21;
3822  rlUInt8_t reserved1;
3826  rlUInt8_t reserved0;
3827 #endif
3828 
3832  rlUInt32_t timeStamp;
3834 
3842 /* Sub block ID: 0x1022, ICD API: AWR_MONITOR_TX0_PHASE_SHIFTER_REPORT_AE_SB */
3843 /* Sub block ID: 0x1023, ICD API: AWR_MONITOR_TX1_PHASE_SHIFTER_REPORT_AE_SB */
3844 /* Sub block ID: 0x1024, ICD API: AWR_MONITOR_TX2_PHASE_SHIFTER_REPORT_AE_SB */
3845 typedef struct rlMonTxPhShiftRep
3846 {
3856  rlUInt16_t statusFlags;
3860  rlUInt16_t errorCode;
3861 #ifndef MMWL_BIG_ENDIAN
3862 
3865  rlUInt8_t profIndex;
3869  rlUInt8_t reserved0;
3870 #else
3871 
3874  rlUInt8_t reserved0;
3878  rlUInt8_t profIndex;
3879 #endif
3880 
3883  rlUInt16_t reserved1;
3889  rlUInt16_t phaseShifterMonVal1;
3895  rlUInt16_t phaseShifterMonVal2;
3901  rlUInt16_t phaseShifterMonVal3;
3907  rlUInt16_t phaseShifterMonVal4;
3913  rlInt16_t txPsAmplitudeVal1;
3919  rlInt16_t txPsAmplitudeVal2;
3925  rlInt16_t txPsAmplitudeVal3;
3931  rlInt16_t txPsAmplitudeVal4;
3932 #ifndef MMWL_BIG_ENDIAN
3933 
3938  rlInt8_t txPsNoiseVal1;
3944  rlInt8_t txPsNoiseVal2;
3950  rlInt8_t txPsNoiseVal3;
3956  rlInt8_t txPsNoiseVal4;
3957 #else
3958 
3963  rlInt8_t txPsNoiseVal2;
3969  rlInt8_t txPsNoiseVal1;
3975  rlInt8_t txPsNoiseVal4;
3981  rlInt8_t txPsNoiseVal3;
3982 #endif
3983 
3988  rlUInt32_t timeStamp;
3992  rlUInt32_t reserved2;
3996  rlUInt32_t reserved3;
3998 
4005 /* Sub block ID: 0x1025, ICD API: AWR_MONITOR_SYNTHESIZER_FREQUENCY_REPORT_AE_SB */
4006 typedef struct rlMonSynthFreqRep
4007 {
4016  rlUInt16_t statusFlags;
4020  rlUInt16_t errorCode;
4021 #ifndef MMWL_BIG_ENDIAN
4022 
4025  rlUInt8_t profIndex;
4029  rlUInt8_t reserved0;
4030 #else
4031 
4034  rlUInt8_t reserved0;
4038  rlUInt8_t profIndex;
4039 #endif
4040 
4043  rlUInt16_t reserved1;
4051  rlInt32_t maxFreqErVal;
4061  rlUInt32_t freqFailCnt;
4065  rlUInt32_t reserved2;
4069  rlUInt32_t reserved3;
4075  rlUInt32_t timeStamp;
4077 
4084 /* Sub block ID: 0x1026, ICD API: AWR_MONITOR_EXTERNAL_ANALOG_SIGNALS_REPORT_AE_SB */
4085 typedef struct rlMonExtAnaSigRep
4086 {
4100  rlUInt16_t statusFlags;
4104  rlUInt16_t errorCode;
4116  rlInt16_t extAnaSigVal[6U];
4120  rlUInt32_t reserved;
4126  rlUInt32_t timeStamp;
4128 
4135 /* Sub block ID: 0x1027, ICD API: AWR_MONITOR_TX0_INTERNAL_ANALOG_SIGNALS_REPORT_AE_SB */
4136 /* Sub block ID: 0x1028, ICD API: AWR_MONITOR_TX1_INTERNAL_ANALOG_SIGNALS_REPORT_AE_SB */
4137 /* Sub block ID: 0x1029, ICD API: AWR_MONITOR_TX2_INTERNAL_ANALOG_SIGNALS_REPORT_AE_SB */
4138 typedef struct rlMonTxIntAnaSigRep
4139 {
4149  rlUInt16_t statusFlags;
4153  rlUInt16_t errorCode;
4154 #ifndef MMWL_BIG_ENDIAN
4155 
4158  rlUInt8_t profIndex;
4162  rlUInt8_t reserved0;
4167  rlUInt8_t phShiftDacIdeltaMin;
4172  rlUInt8_t phShiftDacQdeltaMin;
4173 #else
4174 
4177  rlUInt8_t reserved0;
4181  rlUInt8_t profIndex;
4186  rlUInt8_t phShiftDacQdeltaMin;
4191  rlUInt8_t phShiftDacIdeltaMin;
4192 #endif
4193 
4198  rlUInt32_t timeStamp;
4200 
4207 /* Sub block ID: 0x102A, ICD API: AWR_MONITOR_RX_INTERNAL_ANALOG_SIGNALS_REPORT_AE_SB */
4208 typedef struct rlMonRxIntAnaSigRep
4209 {
4225  rlUInt16_t statusFlags;
4229  rlUInt16_t errorCode;
4230 #ifndef MMWL_BIG_ENDIAN
4231 
4234  rlUInt8_t profIndex;
4238  rlUInt8_t reserved0;
4239 #else
4240 
4243  rlUInt8_t reserved0;
4247  rlUInt8_t profIndex;
4248 #endif
4249 
4252  rlUInt16_t reserved1;
4258  rlUInt32_t timeStamp;
4260 
4268 /* Sub block ID: 0x102B, ICD API: AWR_MONITOR_PMCLKLO_INTERNAL_ANALOG_SIGNALS_REPORT_AE_SB */
4269 typedef struct rlMonPmclkloIntAnaSigRep
4270 {
4283  rlUInt16_t statusFlags;
4287  rlUInt16_t errorCode;
4288 #ifndef MMWL_BIG_ENDIAN
4289 
4292  rlUInt8_t profIndex;
4305  rlInt8_t sync20GPower;
4306 #else
4307 
4319  rlInt8_t sync20GPower;
4323  rlUInt8_t profIndex;
4324 #endif
4325 
4328  rlUInt16_t reserved;
4334  rlUInt32_t timeStamp;
4336 
4344 /* Sub block ID: 0x102C, ICD API: AWR_MONITOR_GPADC_INTERNAL_ANALOG_SIGNALS_REPORT_AE_SB */
4345 typedef struct rlMonGpadcIntAnaSigRep
4346 {
4356  rlUInt16_t statusFlags;
4360  rlUInt16_t errorCode;
4366  rlInt16_t gpadcRef1Val;
4372  rlUInt16_t gpadcRef2Val;
4376  rlUInt32_t reserved;
4382  rlUInt32_t timeStamp;
4384 
4391 /* Sub block ID: 0x102D, ICD API: AWR_MONITOR_PLL_CONTROL_VOLTAGE_REPORT_AE_SB */
4392 typedef struct rlMonPllConVoltRep
4393 {
4410  rlUInt16_t statusFlags;
4414  rlUInt16_t errorCode;
4435  rlInt16_t pllContVoltVal[8U];
4447  rlInt16_t pllContVoltVal2[2U];
4453  rlUInt32_t timeStamp;
4455 
4462 /* Sub block ID: 0x102E, ICD API: AWR_MONITOR_DUAL_CLOCK_COMP_REPORT_AE_SB */
4463 typedef struct rlMonDccClkFreqRep
4464 {
4477  rlUInt16_t statusFlags;
4481  rlUInt16_t errorCode;
4495  rlUInt16_t freqMeasVal[8U];
4499  rlUInt32_t reserved;
4505  rlUInt32_t timeStamp;
4507 
4515 /* Sub block ID: 0x1031, ICD API: AWR_MONITOR_RX_MIXER_IN_POWER_REPORT_AE_SB */
4516 typedef struct rlMonRxMixrInPwrRep
4517 {
4529  rlUInt16_t statusFlags;
4533  rlUInt16_t errorCode;
4534 
4535 #ifndef MMWL_BIG_ENDIAN
4539  rlUInt8_t profIndex;
4543  rlUInt8_t reserved0;
4544 #else
4545 
4548  rlUInt8_t reserved0;
4552  rlUInt8_t profIndex;
4553 #endif
4554 
4557  rlUInt16_t reserved1;
4570  rlUInt32_t rxMixInVolt;
4574  rlUInt32_t reserved2;
4579  rlUInt32_t timeStamp;
4581 
4589 /* Sub block ID: 0x1033, ICD API: AWR_MONITOR_SYNTHESIZER_FREQUENCY_NONLIVE_REPORT_AE_SB */
4590 typedef struct rlMonSynthFreqNonLiveRep
4591 {
4601  rlUInt16_t statusFlags;
4605  rlUInt16_t errorCode;
4606 
4607 #ifndef MMWL_BIG_ENDIAN
4611  rlUInt8_t profIndex0;
4615  rlUInt8_t reserved0;
4616 #else
4617 
4620  rlUInt8_t reserved0;
4624  rlUInt8_t profIndex0;
4625 #endif
4626 
4629  rlUInt16_t reserved1;
4637  rlInt32_t maxFreqErVal0;
4647  rlUInt32_t freqFailCnt0;
4653  rlUInt32_t maxFreqFailTime0;
4657  rlUInt32_t reserved2;
4658 
4659 #ifndef MMWL_BIG_ENDIAN
4663  rlUInt8_t profIndex1;
4667  rlUInt8_t reserved3;
4668 #else
4669 
4672  rlUInt8_t reserved3;
4676  rlUInt8_t profIndex1;
4677 #endif
4678 
4681  rlUInt16_t reserved4;
4689  rlInt32_t maxFreqErVal1;
4699  rlUInt32_t freqFailCnt1;
4705  rlUInt32_t maxFreqFailTime1;
4709  rlUInt32_t reserved5;
4710 
4715  rlUInt32_t timeStamp;
4717 
4727 typedef struct rlMmwlErrorStatus
4728 {
4729  rlInt32_t errorVal;
4731 
4732 #include <ti/control/mmwavelink/include/rl_device.h>
4733 #include <ti/control/mmwavelink/include/rl_sensor.h>
4734 #include <ti/control/mmwavelink/include/rl_monitoring.h>
4735 #include <ti/control/mmwavelink/include/rl_protocol.h>
4736 #include <ti/control/mmwavelink/include/rl_messages.h>
4737 
4738 
4739 /******************************************************************************
4740  * FUNCTION PROTOTYPES
4741  ******************************************************************************
4742  */
4743 
4744 #ifdef __cplusplus
4745 }
4746 #endif
4747 
4748 #endif
4749 /*
4750  * END OF MMWAVELINK_H
4751  */
4752 
This is the Monitoring report which RadarSS sends to the host, containing information about the relat...
Definition: mmwavelink.h:4466
mmWaveLink RF Run time calibration report for event RL_RF_AE_RUN_TIME_CALIB_REPORT_SB
Definition: mmwavelink.h:2224
This async event is sent periodically to indicate the status of periodic digital monitoring tests....
Definition: mmwavelink.h:2956
mmWaveLink client callback structure
Definition: mmwavelink.h:1529
This is the Monitoring report which RadarSS sends to the host, containing the measured RX noise figur...
Definition: mmwavelink.h:3251
mmWaveLink RF Init Complete data structure for event RL_RF_AE_INITCALIBSTATUS_SB
Definition: mmwavelink.h:2169
Sensors GPADC measurement data for event RL_RF_AE_GPADC_MEAS_DATA_SB.
Definition: mmwavelink.h:2792
Structure to hold the BSS ESM Fault data strucutre for event RL_RF_AE_ESMFAULT_SB.
Definition: mmwavelink.h:2097
mmWaveLink firmware version structure
Definition: mmwavelink.h:2537
Structure to hold the test status report of the latent fault tests data strucutre for event RL_DEV_AE...
Definition: mmwavelink.h:1986
mmWaveLink Report for event RL_RF_AE_MONITOR_TYPE_TRIGGER_DONE_SB. The triggered monitor types are do...
Definition: mmwavelink.h:2287
Communication interface(SPI, MailBox, UART etc) callback functions.
Definition: mmwavelink.h:1080
mmWaveLink CRC callback function
Definition: mmwavelink.h:1365
Calibration monitoring timing error data for event RL_RF_AE_MON_TIMING_FAIL_REPORT_SB.
Definition: mmwavelink.h:2866
This is the Monitoring report which RadarSS sends to the host, containing the measured temperature ne...
Definition: mmwavelink.h:2983
mmWaveLink Init Complete data structure for event RL_DEV_AE_MSSPOWERUPDONE_SB
Definition: mmwavelink.h:1595
This is the Monitoring report which RadarSS sends to the host, containing information about Internal ...
Definition: mmwavelink.h:4272
This API is a Monitoring report which RadarSS sends to the host, containing the measured RX gain and ...
Definition: mmwavelink.h:3040
This is an error status report internally generated from mmWaveLink when it finds any issue with the ...
Definition: mmwavelink.h:4730
This is the Monitoring report which RadarSS sends to the host, containing the measured TX reflection ...
Definition: mmwavelink.h:3605
This is the Monitoring report which RadarSS sends to the host, containing information about the measu...
Definition: mmwavelink.h:4348
This is the Monitoring report which the AWR device sends to the host, containing the measured TX phas...
Definition: mmwavelink.h:3848
OS semaphore callback functions.
Definition: mmwavelink.h:1216
mmWaveLink Device Control, Interrupt callback functions
Definition: mmwavelink.h:1390
This is the Monitoring report which RadarSS sends to the host, containing information related to meas...
Definition: mmwavelink.h:4009
mmWaveLink Timer callback functions
Definition: mmwavelink.h:1345
mmWaveLink debug callback structure
Definition: mmwavelink.h:1504
Analog fault strucure for event RL_RF_AE_ANALOG_FAULT_SB.
Definition: mmwavelink.h:2812
This is the Monitoring report which RadarSS sends to the host, containing the measured Tx gain and ph...
Definition: mmwavelink.h:3648
API APLL closed loop cal Status Get Sub block structure.
Definition: mmwavelink.h:2336
This is the Monitoring report which RadarSS sends to the host, containing information about Internal ...
Definition: mmwavelink.h:4141
This is the Monitoring report which RadarSS sends to the host, containing information about Internal ...
Definition: mmwavelink.h:4211
Structure to hold data strucutre for RF-error status send by MSS for event RL_DEV_AE_MSS_RF_ERROR_STA...
Definition: mmwavelink.h:2070
Latent fault digital monitoring status data for event RL_RF_AE_DIG_LATENTFAULT_REPORT_AE_SB.
Definition: mmwavelink.h:2889
This is the Monitoring report which RadarSS sends to the host, containing the measured PLL control vo...
Definition: mmwavelink.h:4395
GPADC measurement data for sensors.
Definition: mmwavelink.h:2772
This is a Non live Monitoring report which device sends to the host, containing information related t...
Definition: mmwavelink.h:4593
This is the Monitoring report which the xWR device sends to the host, containing the measured RX mixe...
Definition: mmwavelink.h:4519
Structure to hold the MSS Boot error status data strucutre when booted over SPI for event RL_DEV_AE_M...
Definition: mmwavelink.h:1864
Structure to hold the MSS ESM Fault data structure for event RL_DEV_AE_MSS_ESMFAULT_SB.
Definition: mmwavelink.h:1773
The report header includes common information across all enabled monitors like current FTTI number an...
Definition: mmwavelink.h:2930
mmwavelink software version structure
Definition: mmwavelink.h:2679
mmWaveLink callback functions for Command parser
Definition: mmwavelink.h:1353
OS mutex callback functions.
Definition: mmwavelink.h:1143
This is the Monitoring report which RadarSS sends to the host, containing the external signal voltage...
Definition: mmwavelink.h:4088
Structure to hold the MSS/radarSS CPU Fault data strucutre for event RL_DEV_AE_MSS_CPUFAULT_SB and RL...
Definition: mmwavelink.h:2367
mmwavelink version structure
Definition: mmwavelink.h:2753
Structure to hold data strucutre for test status of the periodic tests for event RL_DEV_AE_MSS_PERIOD...
Definition: mmwavelink.h:2048
mmWaveLink RF Start Complete data structure for event RL_DEV_AE_RFPOWERUPDONE_SB
Definition: mmwavelink.h:1717
mmWaveLink Asynchronous event callback function
Definition: mmwavelink.h:1321
This is the Monitoring report which RadarSS sends to the host, containing the measured RX IF filter a...
Definition: mmwavelink.h:3330
OS message queue/Spawn callback functions.
Definition: mmwavelink.h:1276
This is the Monitoring report which RadarSS sends to the host, containing the measured TX power value...
Definition: mmwavelink.h:3531
OS services callback functions.
Definition: mmwavelink.h:1302

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