Data Fields
rlPmicClkCfg_t Struct Reference

mmwave radar device PMIC Clock output More...

#include <control/mmwavelink/include/rl_device.h>

Data Fields

rlUInt8_t pmicClkCtrl
 This field controls the enable - disable of the PMIC clock.
Value Description
0x0 Disable PMIC clock
0x1 Enable PMIC clock
.
 
rlUInt8_t pmicClkSrc
 This field specifies the source of the PMIC clock. Applicable only in case of
PMIC clock enable. Else ignored.
Value Description
0x0 XTAL (as connected to the device)
0x2 600MHz PLL divided clock
.
 
rlUInt8_t srcClkDiv
 This field specifies the division factor to be applie to source clock.
Applicable only in case of PMIC clock
enable. Else ignored.
Value Description
0x0 Divide by 1 (Not supported)
0x1 Divide by 2
... ...
0xFF Divide by 256
. More...
 
rlUInt8_t modeSel
 This field specifies the mode of operation for the PMIC clock generation.
Applicable only in case of PMIC clock
enable. Else ignored.
Value Description
0x0 Continuous mode (free running mode where the frequency
change/jump is triggered based on configured number of
internal clock ticks)
0x1 Chirp-to-Chirp staircase mode (frequency change/jump is
triggered at every chirp boundary)
.
 
rlUInt32_t freqSlope
 Applicable only in case of PMIC clock enable. Else ignored.
Bit[25:0] - Frequency slope value to be applied in [8.18] format.
1 LSB = 1/218
In continuous mode this value is accumulated every PMIC clock tick
with the seed as MIN_NDIV_VAL till MAX_NDIV_VAL is reached
In the stair case mode this value is accumulated every chirp with the
seed as MIN_NDIV_VAL till MAX_NDIV_VAL is reached
.
 
rlUInt8_t minNdivVal
 Applicable only in case of PMIC clock enable. Else ignored. Min allowed divider
value (depends upon the highest desired clock frequency)
. More...
 
rlUInt8_t maxNdivVal
 Applicable only in case of PMIC clock enable. Else ignored. Max allowed divider
value (depends upon the lowest desired clock frequency)
. More...
 
rlUInt8_t clkDitherEn
 Applicable only in case of PMIC clock enable. Else ignored. This field controls
the enable-disable of the clock dithering. Adds a pseudo random real number
(0 or 1) to the accumulated divide value. Hence it brings a random dithering
of 1 LSB.
Value Description
0x0 Clock dithering disabled
0x1 Clock dithering enabled
.
 
rlUInt8_t reserved
 Reserved for future use.
 

Detailed Description

mmwave radar device PMIC Clock output

Definition at line 175 of file rl_device.h.

Field Documentation

◆ maxNdivVal

rlUInt8_t rlPmicClkCfg_t::maxNdivVal

Applicable only in case of PMIC clock enable. Else ignored. Max allowed divider
value (depends upon the lowest desired clock frequency)
.

Note
: The Maximum supported PMIC clock out is 20MHz.

Definition at line 280 of file rl_device.h.

◆ minNdivVal

rlUInt8_t rlPmicClkCfg_t::minNdivVal

Applicable only in case of PMIC clock enable. Else ignored. Min allowed divider
value (depends upon the highest desired clock frequency)
.

Note
: The Maximum supported PMIC clock out is 20MHz.

Definition at line 274 of file rl_device.h.

◆ srcClkDiv

rlUInt8_t rlPmicClkCfg_t::srcClkDiv

This field specifies the division factor to be applie to source clock.
Applicable only in case of PMIC clock
enable. Else ignored.
Value Description
0x0 Divide by 1 (Not supported)
0x1 Divide by 2
... ...
0xFF Divide by 256
.

Note
: The Maximum supported PMIC clock out is 20MHz.

Definition at line 204 of file rl_device.h.


The documentation for this struct was generated from the following file:

Copyright 2020, Texas Instruments Incorporated