Data Fields
rlInterRxGainPhConf_t Struct Reference

Inter-Rx gain and phase offset configuration. More...

#include <control/mmwavelink/include/rl_sensor.h>

Data Fields

rlUInt8_t profileIndx
 This field indicates the profile Index for which this configuration applies.
 
rlUInt8_t digCompEn
 This field can be used to enable or disable different digital compensation.
Bits Assignment
b0 Digital RX gain compensation enable
b1 Digital RX phase compensation enable
b2 Digital RX delay compensation enable
b3 Digital RX frequency shift enable
b4 Digital TX frequency shift enable (for debug purpose only)
b31:5 RESERVED
Value Description
0 Disable
1 Enable
.
 
rlUInt16_t reserved1
 Reserved for Future use.
 
rlInt8_t digRxGainComp [RL_RX_CNT]
 The digital gain compensation for each RX channels
One byte per RX (8-bit signed number)
Byte Assignment
0 RX0 digital gain
1 RX1 digital gain
2 RX2 digital gain
3 RX3 digital gain
1 LSB = 0.1 dB
Valid Range: -120 to 119
.
 
rlUInt16_t digRxPhShiftComp [RL_RX_CNT]
 The digital phase shift compensation for each RX channels
Two bytes per RX
Bits Assignment
b15:0 RX0 digital phase shift
b31:16 RX1 digital phase shift
b47:32 RX2 digital phase shift
b63:48 RX3 digital phase shift
1 LSB = 360 degree / 2^16 ~ 0.0055 (degree)
Valid Range: 0 to 65535
. More...
 
rlUInt8_t digRxDelayComp [RL_RX_CNT]
 The digital delay compensation for each RX channels
One byte per RX (8-bit unsigned number)
Byte Assignment
0 RX0 digital delay
1 RX1 digital delay
2 RX2 digital delay
3 RX3 digital delay
1 LSB = 556ps/16, unsigned
Valid Range: 0 to 255
The RX ADC output is delayed by this amount. The LSB becomes twice of the above
if ADC low power mode is enabled.
.
 
rlUInt32_t reserved2 [4U]
 Reserved for Future use.
 
rlInt16_t digRxFreqShift [RL_RX_CNT]
 The digital frequency shift compensation for each RX channels
Two bytes per RX
Bits Assignment
b15:0 RX0 digital frequency shift
b31:16 RX1 digital frequency shift
b47:32 RX2 digital frequency shift
b63:48 RX3 digital frequency shift
1 LSB = 100MHz/2^16, signed
Valid Range: -32768 to 32767
The frequency range of interest in RX digital output is shifted by this amount.
As an example, this may be used to view the spectrum beyond the conventional
[0 to Output Sampling Rate] range in Complex 1X mode, say [FREQ_SHIFT to Output
Sampling Rate + FREQ_SHIFT].
.
 
rlInt16_t digTxFreqShift [RL_RX_CNT]
 The digital frequency shift compensation for each TX channels, this is supported
only for TX0 and TX1.
Two bytes per TX
Bits Assignment
b15:0 TX0 digital frequency shift
b31:16 TX1 digital frequency shift
b47:32 RESERVED
b63:48 RESERVED
1 LSB = 100MHz/2^16, signed
Valid Range: -32768 to 32767
The frequency of the TX output may be shifted wrt the RX mixer LO frequency by
this amount. If such functionality is not desired, this register should be set
to 0. This register cannot be used in conjunction with TX phase shifter.

This may be useful in factory calibration of IF frequency dependent effects.
As an example, in cascaded applications, the IF frequency at which a corner
reflector’s beat frequency appears at the RX mixer output can be varied using
this and cascade RX IF imbalances can be measured.
.
 
rlUInt32_t reserved3 [4U]
 Reserved for Future use.
 

Detailed Description

Inter-Rx gain and phase offset configuration.

Definition at line 4266 of file rl_sensor.h.

Field Documentation

◆ digRxPhShiftComp

rlUInt16_t rlInterRxGainPhConf_t::digRxPhShiftComp[RL_RX_CNT]

The digital phase shift compensation for each RX channels
Two bytes per RX
Bits Assignment
b15:0 RX0 digital phase shift
b31:16 RX1 digital phase shift
b47:32 RX2 digital phase shift
b63:48 RX3 digital phase shift
1 LSB = 360 degree / 2^16 ~ 0.0055 (degree)
Valid Range: 0 to 65535
.

Note
: This field is NOT applicable when ADC_OUT_FMT is 00 (real output)

Definition at line 4350 of file rl_sensor.h.


The documentation for this struct was generated from the following file:

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