Data Fields
rlPllContrVoltMonConf_t Struct Reference

Internal signals for PLL control voltage monitoring configuration. More...

#include <control/mmwavelink/include/rl_monitoring.h>

Data Fields

rlUInt8_t reportMode
 Value Definition
0 RESERVED
1 Report is send only upon a failure (after checking for thresholds)
2 Report is sent every monitoring period with threshold check.
.
 
rlUInt8_t reserved0
 Reserved for Future use.
 
rlUInt16_t signalEnables
 This field indicates the sets of signals which are to be monitored. When each bit
in this field is set, the corresponding signal set is monitored using test
chirps. Rest of the RF analog may not be ON during these test chirps. The APLL
VCO control voltage can be monitored. The Synthesizer VCO control voltage for
both VCO1 and VCO2 can be monitored, while operating at their respective
minimum and maximum frequencies, and their respective VCO slope (Hz/V) can be
monitored if both frequencies are enabled for that VCO. The monitored signals
are compared against internally chosen valid limits. The comparison results are
part of the monitoring
report message.
Bit Location SIGNAL
0 APLL_VCTRL
1 SYNTH_VCO1_VCTRL
2 SYNTH_VCO2_VCTRL
15:3 RESERVED
The synthesizer VCO extreme frequencies are:
Synthesizer VCO Frequency Limits (Min, Max)
VCO1 (76GHz, 78GHz)
VCO2 (77GHz, 81GHz)
Synthesizer measurements are done with TX switched off to avoid emissions.
.
 
rlUInt32_t reserved1
 Reserved for Future use.
 

Detailed Description

Internal signals for PLL control voltage monitoring configuration.

Definition at line 1689 of file rl_monitoring.h.


The documentation for this struct was generated from the following file:

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