364 #include <ti/control/mmwavelink/include/rl_datatypes.h> 376 #if defined(WIN32) || defined(WIN32_) || defined(_MSC_VER) 377 #define MMWL_EXPORT __declspec(dllexport) 383 #define RL_MMWAVELINK_VERSION "2.2.2.1.13.8.20" 384 #define RL_MMWAVELINK_VERSION_MAJOR (2U) 385 #define RL_MMWAVELINK_VERSION_MINOR (2U) 386 #define RL_MMWAVELINK_VERSION_BUILD (2U) 387 #define RL_MMWAVELINK_VERSION_DEBUG (1U) 388 #define RL_MMWAVELINK_VERSION_DAY (13U) 389 #define RL_MMWAVELINK_VERSION_MONTH (8U) 390 #define RL_MMWAVELINK_VERSION_YEAR (20U) 393 #define RL_RET_CODE_OK ((rlReturnVal_t)0) 394 #define RL_RET_CODE_PROTOCOL_ERROR (-1) 395 #define RL_RET_CODE_INVALID_INPUT (-2) 396 #define RL_RET_CODE_SELF_ERROR (-3) 397 #define RL_RET_CODE_RADAR_IF_ERROR (-4) 398 #define RL_RET_CODE_MALLOC_ERROR (-5) 399 #define RL_RET_CODE_CRC_FAILED (-6) 401 #define RL_RET_CODE_CHKSUM_FAILED (-7) 403 #define RL_RET_CODE_RESP_TIMEOUT (-8) 405 #define RL_RET_CODE_FATAL_ERROR (-9) 407 #define RL_RET_CODE_RADAR_OSIF_ERROR (-10) 408 #define RL_RET_CODE_INVALID_STATE_ERROR (-11) 409 #define RL_RET_CODE_API_NOT_SUPPORTED (-12) 410 #define RL_RET_CODE_MSGID_MISMATCHED (-13) 412 #define RL_RET_CODE_NULL_PTR (-14) 413 #define RL_RET_CODE_INTERFACE_CB_NULL (-15) 414 #define RL_RET_CODE_NACK_ERROR (-16) 415 #define RL_RET_CODE_HOSTIRQ_TIMEOUT (-17) 418 #define RL_RET_CODE_RX_SEQ_NUM_NOT_MATCH (-18) 422 #define RL_RET_CODE_INVLD_OPCODE (1U) 423 #define RL_RET_CODE_INVLD_NUM_SB (2U) 424 #define RL_RET_CODE_INVLD_SB_ID (3U) 425 #define RL_RET_CODE_INVLD_SB_LEN (4U) 426 #define RL_RET_CODE_SB_INVL_DATA (5U) 427 #define RL_RET_CODE_SB_PROCESS_ERR (6U) 428 #define RL_RET_CODE_MISMATCH_FILE_CRC (7U) 429 #define RL_RET_CODE_MISMATCH_FILE_TYPE (8U) 432 #define RL_RET_CODE_FRAME_ALREADY_STARTED (20U) 434 #define RL_RET_CODE_FRAME_ALREADY_ENDED (21U) 436 #define RL_RET_CODE_FRAME_CFG_NOT_RECVD (22U) 438 #define RL_RET_CODE_FRAME_TRIG_INVL_IN (23U) 442 #define RL_RET_CODE_CH_CFG_RX_INVAL_IN (24U) 444 #define RL_RET_CODE_CH_CFG_TX_INVAL_IN (25U) 446 #define RL_RET_CODE_CH_CFG_CASC_INVAL_IN (26U) 450 #define RL_RET_CODE_ADC_BITS_INVAL_IN (27U) 452 #define RL_RET_CODE_ADC_FORM_INVAL_IN (28U) 456 #define RL_RET_CODE_LP_ADC_INVAL_IN (29U) 460 #define RL_RET_CODE_DYN_PS_INVAL_IN (30U) 464 #define RL_RET_CODE_HSI_DIV_INVAL_IN (31U) 465 #define RL_RET_CODE_RESERVED0 (32U) 466 #define RL_RET_CODE_HSI_DIV_INVAL_1IN (33U) 468 #define RL_RET_CODE_HSI_DIV_INVAL_2IN (34U) 472 #define RL_RET_CODE_PF_IND_INVAL_IN (35U) 473 #define RL_RET_CODE_PF_START_FREQ_INVAL_IN (36U) 475 #define RL_RET_CODE_PF_IDLE_TIME_INVAL_IN (37U) 476 #define RL_RET_CODE_PF_IDLE_TIME_1INVAL_IN (38U) 480 #define RL_RET_CODE_PF_ADC_START_INVAL_IN (39U) 481 #define RL_RET_CODE_PF_RAMP_END_INVAL_IN (40U) 482 #define RL_RET_CODE_PF_RAMP_END_1INVAL_IN (41U) 484 #define RL_RET_CODE_PF_TX0_INVAL_IN (42U) 486 #define RL_RET_CODE_PF_TX1_INVAL_IN (43U) 488 #define RL_RET_CODE_PF_TX2_INVAL_IN (44U) 490 #define RL_RET_CODE_RESERVED1 (45U) 491 #define RL_RET_CODE_PF_FREQ_SLOPE_1INVAL_IN (46U) 493 #define RL_RET_CODE_PF_TX_START_INVAL_IN (47U) 495 #define RL_RET_CODE_PF_NUM_ADC_SMAP_INVAL_IN (48U) 497 #define RL_RET_CODE_PF_DFE_SAMP_RATE_INVAL_IN (49U) 499 #define RL_RET_CODE_PF_HPF1_CF_INVAL_IN (50U) 500 #define RL_RET_CODE_PF_HPF2_CF_INVAL_IN (51U) 501 #define RL_RET_CODE_PF_RX_GAIN_INVAL_IN (52U) 503 #define RL_RET_CODE_RESERVED2 (53U) 504 #define RL_RET_CODE_RESERVED3 (54U) 505 #define RL_RET_CODE_RESERVED4 (55U) 506 #define RL_RET_CODE_RESERVED5 (56U) 507 #define RL_RET_CODE_RESERVED6 (57U) 508 #define RL_RET_CODE_RESERVED7 (58U) 511 #define RL_RET_CODE_CHIRP_START_INVAL_IN (59U) 512 #define RL_RET_CODE_CHIRP_END_INVAL_IN (60U) 513 #define RL_RET_CODE_CHIRP_END_1INVAL_IN (61U) 514 #define RL_RET_CODE_CHIRP_PF_IND_INVAL_IN (62U) 515 #define RL_RET_CODE_CHIRP_PF_IND_1INVAL_IN (63U) 517 #define RL_RET_CODE_CHIRP_START_FREQ_INVAL_IN (64U) 518 #define RL_RET_CODE_CHIRP_SLOPE_INVAL_IN (65U) 519 #define RL_RET_CODE_CHIRP_SLOPE_1INVAL_IN (66U) 521 #define RL_RET_CODE_CHIRP_IDLE_TIME_INVAL_IN (67U) 522 #define RL_RET_CODE_CHIRP_ADC_START_INVAL_IN (68U) 523 #define RL_RET_CODE_CHIRP_ADC_START_1INVAL_IN (69U) 525 #define RL_RET_CODE_CHIRP_TX_ENA_INVAL_IN (70U) 526 #define RL_RET_CODE_CHIRP_TX_ENA_1INVAL_IN (71U) 531 #define RL_RET_CODE_FRAME_CHIRP_STR_INVAL_IN (72U) 532 #define RL_RET_CODE_FRAME_CHIRP_END_INVAL_IN (73U) 533 #define RL_RET_CODE_FRAME_CHIRP_END_1INVAL_IN (74U) 534 #define RL_RET_CODE_FRAME_CHIRP_END_2INVAL_IN (75U) 536 #define RL_RET_CODE_FRAME_CHIRP_PF_INVAL_IN (76U) 538 #define RL_RET_CODE_FRAME_CHIRP_LOOPS_INVAL_IN (77U) 539 #define RL_RET_CODE_RESERVED8 (78U) 540 #define RL_RET_CODE_FRAME_PERIOD_INVAL_IN (79U) 542 #define RL_RET_CODE_FRAME_PERIOD_1INVAL_IN (80U) 543 #define RL_RET_CODE_FRAME_TRIG_SEL_INVAL_IN (81U) 544 #define RL_RET_CODE_FRAME_TRIG_DELAY_INVAL_IN (82U) 545 #define RL_RET_CODE_FRAME_IS_ONGOING (83U) 546 #define RL_RET_CODE_FRAME_DUMMY_CHIRPS_INVAL_IN (160U) 550 #define RL_RET_CODE_AFRAME_NUM_SUBF_INVAL_IN (84U) 551 #define RL_RET_CODE_AFRAME_FORCE_PF_INVAL_IN (85U) 553 #define RL_RET_CODE_AFRAME_PF_IND_INVAL_IN (86U) 554 #define RL_RET_CODE_AFRAME_PF_IND_1INVAL_IN (87U) 556 #define RL_RET_CODE_AFRAME_CHIRP_STR_INVAL_IN (88U) 557 #define RL_RET_CODE_AFRAME_NCHIRP_INVAL_IN (89U) 559 #define RL_RET_CODE_AFRAME_NCHIRP_1INVAL_IN (90U) 561 #define RL_RET_CODE_AFRAME_CHIRP_PF_INVAL_IN (91U) 563 #define RL_RET_CODE_AFRAME_CHIRP_LOOPS_INVAL_IN (92U) 565 #define RL_RET_CODE_AFRAME_BURST_PERIOD_INVAL_IN (93U) 567 #define RL_RET_CODE_AFRAME_BURST_PER_1INVAL_IN (94U) 568 #define RL_RET_CODE_AFRAME_BURST_STIND_INVAL_IN (95U) 570 #define RL_RET_CODE_AFRAME_BURST_SIND_1INVAL_IN (96U) 574 #define RL_RET_CODE_AFRAME_NUM_BURSTS_INVAL_IN (97U) 576 #define RL_RET_CODE_AFRAME_BURST_LOOPS_INVAL_IN (98U) 578 #define RL_RET_CODE_AFRAME_SF_PERIOD_INVAL_IN (99U) 580 #define RL_RET_CODE_AFRAME_SF_PERIOD_1INVAL_IN (100U) 583 #define RL_RET_CODE_RESERVED9 (101U) 584 #define RL_RET_CODE_AFRAME_TRIG_SEL_INVAL_IN (102U) 585 #define RL_RET_CODE_AFRAME_TRIG_DELAY_INVAL_IN (103U) 586 #define RL_RET_CODE_AFRAME_IS_ONGOING (104U) 589 #define RL_RET_CODE_TS_POS_VECY_INVAL_IN (105U) 590 #define RL_RET_CODE_RESERVED10 (106U) 591 #define RL_RET_CODE_TS_VEL_VECXYZ_INVAL_IN (107U) 594 #define RL_RET_CODE_TS_SIG_LEVEL_INVAL_IN (108U) 595 #define RL_RET_CODE_TS_RX_ANT_POS_INVAL_IN (109U) 596 #define RL_RET_CODE_RESERVED11 (110U) 599 #define RL_RET_CODE_PROG_FILT_STARTINDX_INVALID (111U) 601 #define RL_RET_CODE_PROG_FILT_PROFILE_INVALID (112U) 602 #define RL_RET_CODE_PROG_FILT_UNSUPPORTED_DEV (113U) 605 #define RL_RET_CODE_PERCHIRPPHSHIFT_UNSUPPORTED_DEV (114U) 607 #define RL_RET_CODE_PERCHIRPPHSHIFT_STIND (115U) 608 #define RL_RET_CODE_PERCHIRPPHSHIFT_ENIND (116U) 609 #define RL_RET_CODE_PERCHIRPPHSHIFT_WRONG_STIND (117U) 612 #define RL_RET_CODE_RF_INIT_NOT_DONE (118U) 614 #define RL_RET_CODE_FORCE_TEMP_BIN_IDX_INVALID (286U) 616 #define RL_RET_CODE_FREQ_LIMIT_OUT_RANGE (119U) 618 #define RL_RET_CODE_CAL_MON_TIME_INVALID (120U) 619 #define RL_RET_CODE_RUN_CAL_PERIOD_INVALID (121U) 620 #define RL_RET_CODE_CONT_STREAM_MODE_EN (122U) 622 #define RL_RET_CODE_RX_GAIN_BOOT_CAL_NOT_DONE (123U) 625 #define RL_RET_CODE_LO_DIST_BOOT_CAL_NOT_DONE (124U) 628 #define RL_RET_CODE_TX_PWR_BOOT_CAL_NOT_DONE (125U) 631 #define RL_RET_CODE_PROG_FILTR_UNSUPPORTED_DFEMODE (126U) 632 #define RL_RET_CODE_ADC_BITS_FULL_SCALE_REDUC_INVAL (127U) 635 #define RL_RET_CODE_CAL_MON_NUM_CASC_DEV_INVALID (128U) 636 #define RL_RET_CODE_FRAME_TRIG_INVL_STOP_IN (129U) 638 #define RL_RET_CODE_RF_FREQBAND_INVALID (130U) 641 #define RL_RET_CODE_INVAL_LOOPBACK_TYPE (132U) 642 #define RL_RET_CODE_INVAL_LOOPBACK_BURST_IND (133U) 643 #define RL_RET_CODE_INVAL_LOOPBACK_CONFIG (134U) 644 #define RL_RET_CODE_DYN_CHIRP_INVAL_SEG (135U) 645 #define RL_RET_CODE_DYN_PERCHIRP_PHSHFT_INVA_SEG (136U) 646 #define RL_RET_CODE_INVALID_CAL_CHUNK_ID (137U) 647 #define RL_RET_CODE_INVALID_CAL_CHUNK_DATA (138U) 650 #define RL_RET_CODE_RX02_RF_TURN_OFF_TIME_INVALID (139U) 652 #define RL_RET_CODE_RX13_RF_TURN_OFF_TIME_INVALID (140U) 654 #define RL_RET_CODE_RX02_BB_TURN_OFF_TIME_INVALID (141U) 656 #define RL_RET_CODE_RX13_BB_TURN_OFF_TIME_INVALID (142U) 658 #define RL_RET_CODE_RX02_RF_PREENABLE_TIME_INVALID (143U) 660 #define RL_RET_CODE_RX13_RF_PREENABLE_TIME_INVALID (144U) 662 #define RL_RET_CODE_RX02_BB_PREENABLE_TIME_INVALID (145U) 664 #define RL_RET_CODE_RX13_BB_PREENABLE_TIME_INVALID (146U) 666 #define RL_RET_CODE_RX02_RF_TURN_ON_TIME_INVALID (147U) 668 #define RL_RET_CODE_RX13_RF_TURN_ON_TIME_INVALID (148U) 670 #define RL_RET_CODE_RX02_BB_TURN_ON_TIME_INVALID (149U) 672 #define RL_RET_CODE_RX13_BB_TURN_ON_TIME_INVALID (150U) 674 #define RL_RET_CODE_RX_LO_TURN_OFF_TIME_INVALID (151U) 676 #define RL_RET_CODE_TX_LO_TURN_OFF_TIME_INVALID (152U) 678 #define RL_RET_CODE_RX_LO_TURN_ON_TIME_INVALID (153U) 680 #define RL_RET_CODE_TX_LO_TURN_ON_TIME_INVALID (154U) 682 #define RL_RET_CODE_SUBFRAME_TRIGGER_INVALID (155U) 687 #define RL_RET_CODE_REGULAR_ADC_MODE_INVALID (156U) 689 #define RL_RET_CODE_CHIRP_ROW_SELECT_INVAL_IN (159U) 692 #define RL_RET_CODE_DEVICE_NOT_ASILB_TYPE (250U) 693 #define RL_RET_CODE_FRAME_ONGOING (251U) 696 #define RL_RET_CODE_INVLD_REPO_MODE (252U) 697 #define RL_RET_CODE_INVLD_PROFILE_ID (253U) 699 #define RL_RET_CODE_INVLD_PROFILE (254U) 701 #define RL_RET_CODE_INVLD_EXTSIG_SETLTIME (255U) 703 #define RL_RET_CODE_INVLD_NO_RX_ENABLED (256U) 704 #define RL_RET_CODE_INVLD_TX0_NOT_ENABLED (257U) 705 #define RL_RET_CODE_INVLD_TX1_NOT_ENABLED (258U) 706 #define RL_RET_CODE_INVLD_TX2_NOT_ENABLED (259U) 707 #define RL_RET_CODE_MON_INVALID_RF_BIT_MASK (260U) 708 #define RL_RET_CODE_RESERVED12 (261U) 709 #define RL_RET_CODE_RESERVED13 (262U) 710 #define RL_RET_CODE_MON_TX_EN_CHK_FAIL (263U) 711 #define RL_RET_CODE_MON_RX_CH_EN_CHK_FAIL (264U) 712 #define RL_RET_CODE_MON_TX_CH_PS_LB (265U) 715 #define RL_RET_CODE_INVLD_SAT_MON_SEL (266U) 716 #define RL_RET_CODE_INVLD_SAT_MON_PRI_SLICE_DUR (267U) 719 #define RL_RET_CODE_INVLD_SAT_MON_NUM_SLICES (268U) 721 #define RL_RET_CODE_INVLD_SIG_IMG_SLICENUM (269U) 723 #define RL_RET_CODE_INVLD_SIG_IMG_NUMSAMPPERSLICE (270U) 727 #define RL_RET_CODE_INVLD_SYNTH_L1_LIN (271U) 728 #define RL_RET_CODE_INVLD_SYNTH_L2_LIN (272U) 729 #define RL_RET_CODE_INVLD_SYNTH_N_LIN (273U) 730 #define RL_RET_CODE_INVLD_SYNTH_MON_START_TIME (274U) 732 #define RL_RET_CODE_INVLD_SYNTH_MON_LIN_RAM_ADDR (275U) 733 #define RL_RET_CODE_LDO_BYPASSED (279U) 735 #define RL_RET_CODE_INVLD_SIG_IMG_BAND_MONTR (280U) 737 #define RL_RET_CODE_ANALOG_MONITOR_NOT_SUPPORTED (281U) 738 #define RL_RET_CODE_ISSUE_TO_ENABLE_CASCASE_MODE (282U) 741 #define RL_RET_CODE_RX_SAT_MON_NOT_SUPPORTED (283U) 742 #define RL_API_NRESP_ANA_MON_MODE_NOT_API_BASED (284U) 745 #define RL_API_NRESP_ANA_MON_TRIG_TYPE_INVALID (285U) 749 #define RL_RET_CODE_CHIRP_FAIL (290U) 750 #define RL_RET_CODE_PD_PWR_LVL (291U) 752 #define RL_RET_CODE_ADC_PWR_LVL (292U) 753 #define RL_RET_CODE_NOISE_FIG_LOW (293U) 754 #define RL_RET_CODE_PD_CDS_ON_FAIL (294U) 756 #define RL_RET_CODE_PGA_GAIN_FAIL (295U) 757 #define RL_RET_CODE_20G_MONITOR_NOT_SUPPORTED (296U) 759 #define RL_RET_CODE_MONITOR_CONFIG_MODE_INVALID (297U) 760 #define RL_RET_CODE_LIVE_NONLIVE_TOGETHER_INVALID (298U) 765 #define RL_RET_CODE_CHIRP_PARAM_IND_INVALID (300U) 766 #define RL_RET_CODE_RESET_MODE_INVALID (301U) 767 #define RL_RET_CODE_DEL_LUT_PAR_UPT_PER_INVALID (303U) 770 #define RL_RET_CODE_SF_CHIRP_PAR_DEL_INVALID (304U) 772 #define RL_RET_CODE_DEL_LUT_RESET_PERIOD_INVALID (305U) 775 #define RL_RET_CODE_LUT_PAT_ADD_OFF_INVALID (306U) 777 #define RL_RET_CODE_LUT_NUM_PATTERNS_INVALID (307U) 779 #define RL_RET_CODE_LUT_SF_BURST_IND_OFF_INVALID (308U) 782 #define RL_RET_CODE_LUT_CHIRP_PAR_SCALE_SIZE_INVALID (309U) 784 #define RL_RET_CODE_LEGACY_API_INPUTS_INVALID (310U) 787 #define RL_RET_CODE_ALL_CHIRP_PARAMS_NOT_DEFINED (311U) 789 #define RL_RET_CODE_TX_PHASE_SHIF_INT_INVALID (312U) 791 #define RL_RET_CODE_NUM_PATTERNS_PROGRAM_INVALID (313U) 795 #define RL_RET_CODE_NUM_CHIRPS_PROGRAM_INVALID (315U) 797 #define RL_RET_CODE_TX_PH_SHIFT_PHASE_MASK_INVALID (316U) 800 #define RL_RET_CODE_TX_PH_SHIFT_RX_MASK_INVALID (317U) 805 #define RL_RET_CODE_NUM_BYTES_PROGRAM_INVALID (314U) 807 #define RL_RET_CODE_TX_IND_PH_SHIFT_RESTORE_INVALID (318U) 811 #define RL_RET_CODE_RX_CHAN_EN_OOR (1001U) 812 #define RL_RET_CODE_NUM_ADC_BITS_OOR (1002U) 813 #define RL_RET_CODE_ADC_OUT_FMT_OOR (1003U) 814 #define RL_RET_CODE_IQ_SWAP_SEL_OOR (1004U) 816 #define RL_RET_CODE_CHAN_INTERLEAVE_OOR (1005U) 820 #define RL_RET_CODE_DATA_INTF_SEL_OOR (1006U) 821 #define RL_RET_CODE_DATA_FMT_PKT0_INVALID (1007U) 823 #define RL_RET_CODE_DATA_FMT_PKT1_INVALID (1008U) 827 #define RL_RET_CODE_LANE_ENABLE_OOR (1009U) 828 #define RL_RET_CODE_LANE_ENABLE_INVALID (1010U) 831 #define RL_RET_CODE_LANE_CLK_CFG_OOR (1011U) 832 #define RL_RET_CODE_LANE_CLK_CFG_INVALID (1012U) 833 #define RL_RET_CODE_DATA_RATE_OOR (1013U) 836 #define RL_RET_CODE_LANE_FMT_MAP_OOR (1014U) 837 #define RL_RET_CODE_LANE_PARAM_CFG_OOR (1015U) 840 #define RL_RET_CODE_CONT_STREAM_MODE_OOR (1016U) 842 #define RL_RET_CODE_CONT_STREAM_MODE_INVALID (1017U) 846 #define RL_RET_CODE_LANE0_POS_POL_OOR (1018U) 847 #define RL_RET_CODE_LANE1_POS_POL_OOR (1019U) 848 #define RL_RET_CODE_LANE2_POS_POL_OOR (1020U) 849 #define RL_RET_CODE_LANE3_POS_POL_OOR (1021U) 850 #define RL_RET_CODE_CLOCK_POS_OOR (1022U) 853 #define RL_RET_CODE_HALF_WORDS_PER_CHIRP_OOR (1023U) 856 #define RL_RET_CODE_NUM_SUBFRAMES_OOR (1024U) 858 #define RL_RET_CODE_SF1_TOT_NUM_CHIRPS_OOR (1025U) 859 #define RL_RET_CODE_SF1_NUM_ADC_SAMP_OOR (1026U) 861 #define RL_RET_CODE_SF1_NUM_CHIRPS_OOR (1027U) 864 #define RL_RET_CODE_SF2_TOT_NUM_CHIRPS_OOR (1028U) 866 #define RL_RET_CODE_SF2_NUM_ADC_SAMP_OOR (1029U) 868 #define RL_RET_CODE_SF2_NUM_CHIRPS_OOR (1030U) 871 #define RL_RET_CODE_SF3_TOT_NUM_CHIRPS_OOR (1031U) 873 #define RL_RET_CODE_SF3_NUM_ADC_SAMP_OOR (1032U) 875 #define RL_RET_CODE_SF3_NUM_CHIRPS_OOR (1033U) 878 #define RL_RET_CODE_SF4_TOT_NUM_CHIRPS_OOR (1034U) 880 #define RL_RET_CODE_SF4_NUM_ADC_SAMP_OOR (1035U) 882 #define RL_RET_CODE_SF4_NUM_CHIRPS_OOR (1036U) 884 #define RL_RET_CODE_MCUCLOCK_CTRL_OOR (1040U) 885 #define RL_RET_CODE_MCUCLOCK_SRC_OOR (1041U) 887 #define RL_RET_CODE_PMICCLOCK_CTRL_OOR (1042U) 888 #define RL_RET_CODE_PMICCLOCK_SRC_OOR (1043U) 889 #define RL_RET_CODE_PMICMODE_SELECT_OOR (1044U) 890 #define RL_RET_CODE_PMICFREQ_SLOPE_OOR (1045U) 891 #define RL_RET_CODE_PMICCLK_DITHER_EN_OOR (1046U) 893 #define RL_RET_CODE_TESTPATTERN_EN_OOR (1047U) 895 #define RL_RET_CODE_LFAULTTEST_UNSUPPORTED_OOR (1048U) 899 #define RL_API_NRESP_LFAULTTEST_UNSUPPORTED_OOR (1051U) 902 #define RL_API_NRESP_DATACONFIG_NOTDONE (1052U) 912 #define RL_DISABLE_LOGGING 1 915 #define RL_OSI_RET_CODE_OK (0) 916 #define RL_IF_RET_CODE_OK (0) 918 #ifdef RL_EXTENDED_MESSAGE 921 #define RL_MAX_SIZE_MSG (2044U) 923 #define RL_MAX_SIZE_MSG (256U) 937 #define RL_DEVICE_MAP_NATIVE (0U) 938 #define RL_DEVICE_MAP_CASCADED_1 (1U) 939 #define RL_DEVICE_MAP_CASCADED_2 (2U) 940 #define RL_DEVICE_MAP_CASCADED_3 (4U) 941 #define RL_DEVICE_MAP_CASCADED_4 (8U) 944 #define RL_DEVICE_MAP_CASCADED_ALL (RL_DEVICE_MAP_CASCADED_1 |\ 945 RL_DEVICE_MAP_CASCADED_2 |\ 946 RL_DEVICE_MAP_CASCADED_3 |\ 947 RL_DEVICE_MAP_CASCADED_4) 950 #define RL_DEVICE_INDEX_INTERNAL_BSS (0U) 951 #define RL_DEVICE_INDEX_INTERNAL_DSS_MSS (1U) 952 #define RL_DEVICE_INDEX_INTERNAL_HOST (2U) 955 #define RL_DEVICE_MAP_INTERNAL_BSS (RL_DEVICE_MAP_CASCADED_1) 957 #define RL_DEVICE_MAP_INTERNAL_DSS_MSS (RL_DEVICE_MAP_CASCADED_2) 958 #define RL_DEVICE_MAP_INTERNAL_HOST (RL_DEVICE_MAP_CASCADED_3) 961 #define RL_DEVICE_CONNECTED_MAX (4U) 978 #ifndef RL_CASCADE_NUM_DEVICES 979 #define RL_CASCADE_NUM_DEVICES (1U) 985 #define RL_CRC_TYPE_16BIT_CCITT (0U) 986 #define RL_CRC_TYPE_32BIT (1U) 987 #define RL_CRC_TYPE_64BIT_ISO (2U) 988 #define RL_CRC_TYPE_NO_CRC (3U) 993 #define RL_PLATFORM_HOST (0x0U) 994 #define RL_PLATFORM_MSS (0x1U) 995 #define RL_PLATFORM_DSS (0x2U) 1000 #define RL_AR_DEVICETYPE_12XX (0x0U) 1001 #define RL_AR_DEVICETYPE_14XX (0x1U) 1002 #define RL_AR_DEVICETYPE_16XX (0x2U) 1003 #define RL_AR_DEVICETYPE_18XX (0x3U) 1004 #define RL_AR_DEVICETYPE_68XX (0x4U) 1005 #define RL_AR_DEVICETYPE_22XX (0x5U) 1010 #define RL_DBG_LEVEL_NONE ((rlUInt8_t)0U) 1011 #define RL_DBG_LEVEL_DATABYTE ((rlUInt8_t)1U) 1012 #define RL_DBG_LEVEL_ERROR ((rlUInt8_t)2U) 1013 #define RL_DBG_LEVEL_WARNING ((rlUInt8_t)3U) 1014 #define RL_DBG_LEVEL_INFO ((rlUInt8_t)4U) 1015 #define RL_DBG_LEVEL_DEBUG ((rlUInt8_t)5U) 1016 #define RL_DBG_LEVEL_VERBOSE ((rlUInt8_t)6U) 1021 #define RL_SENSOR_ANALOGTEST_ONE (0U) 1022 #define RL_SENSOR_ANALOGTEST_TWO (1U) 1023 #define RL_SENSOR_ANALOGTEST_THREE (2U) 1024 #define RL_SENSOR_ANALOGTEST_FOUR (3U) 1025 #define RL_SENSOR_ANAMUX (4U) 1026 #define RL_SENSOR_VSENSE (5U) 1027 #define RL_MAX_GPADC_SENSORS (6U) 1032 #define RL_SWAP_32(x) (((x) & 0x0000FFFFU)<<16U)|(((x) & 0xFFFF0000U)>>16U); 1049 typedef rlInt32_t rlReturnVal_t;
1054 typedef rlUInt8_t rlCrcType_t;
1061 typedef void (*RL_P_OSI_SPAWN_ENTRY)(
const void* pValue);
1066 typedef void (*RL_P_EVENT_HANDLER)(rlUInt8_t deviceIndex,
void* pValue);
1071 typedef struct rlComIfCbs
1085 rlComIfHdl_t (*rlComIfOpen)(rlUInt8_t deviceIndex, rlUInt32_t flags);
1100 rlInt32_t (*rlComIfRead)(rlComIfHdl_t fd, rlUInt8_t *pBuff, rlUInt16_t len);
1115 rlInt32_t (*rlComIfWrite)(rlComIfHdl_t fd, rlUInt8_t *pBuff, rlUInt16_t len);
1128 rlInt32_t (*rlComIfClose)(rlComIfHdl_t fd);
1134 typedef struct rlOsiMutexCbs
1148 rlInt32_t (*rlOsiMutexCreate)(rlOsiMutexHdl_t* mutexHdl, rlInt8_t* name);
1174 rlInt32_t (*rlOsiMutexLock)(rlOsiMutexHdl_t* mutexHdl, rlOsiTime_t timeout);
1188 rlInt32_t (*rlOsiMutexUnLock)(rlOsiMutexHdl_t* mutexHdl);
1201 rlInt32_t (*rlOsiMutexDelete)(rlOsiMutexHdl_t* mutexHdl);
1207 typedef struct rlOsiSemCbs
1221 rlInt32_t (*rlOsiSemCreate)(rlOsiSemHdl_t* semHdl, rlInt8_t* name);
1235 rlInt32_t (*rlOsiSemWait)(rlOsiSemHdl_t* semHdl, rlOsiTime_t timeout);
1248 rlInt32_t (*rlOsiSemSignal)(rlOsiSemHdl_t* semHdl);
1261 rlInt32_t (*rlOsiSemDelete)(rlOsiSemHdl_t* semHdl);
1267 typedef struct rlOsiMsgQCbs
1286 rlInt32_t (*rlOsiSpawn)(RL_P_OSI_SPAWN_ENTRY pEntry,
const void* pValue, rlUInt32_t flags);
1293 typedef struct rlOsiCbs
1312 typedef struct rlEventCbs
1329 void (*rlAsyncEvent)(rlUInt8_t devIndex, rlUInt16_t subId, rlUInt16_t subLen,
1330 rlUInt8_t *payload);
1336 typedef struct rlTimerCbs
1338 rlInt32_t (*rlDelay)(rlUInt32_t delay);
1344 typedef struct rlCmdParserCbs
1346 rlInt32_t (*rlCmdParser)(rlUInt8_t rxMsgClass, rlInt32_t inVal);
1347 rlInt32_t (*rlPostCnysStep)(rlUInt8_t devIndex);
1356 typedef struct rlCrcCbs
1374 rlInt32_t (*rlComputeCRC)(rlUInt8_t* data, rlUInt32_t dataLen, rlUInt8_t crcType,
1381 typedef struct rlDeviceCtrlCbs
1395 rlInt32_t (*rlDeviceEnable)(rlUInt8_t deviceIndex);
1409 rlInt32_t (*rlDeviceDisable)(rlUInt8_t deviceIndex);
1421 void (*rlDeviceMaskHostIrq)(rlComIfHdl_t fd);
1433 void (*rlDeviceUnMaskHostIrq)(rlComIfHdl_t fd);
1452 rlInt32_t (*rlDeviceWaitIrqStatus)(rlComIfHdl_t fd, rlUInt8_t highLow);
1465 rlUInt16_t (*rlCommIfAssertIrq)(rlUInt8_t highLow);
1484 rlInt32_t (*rlRegisterInterruptHandler)(rlUInt8_t deviceIndex,
1485 RL_P_EVENT_HANDLER pHandler,
void* pValue);
1490 typedef rlInt32_t (*rlPrintFptr)(
const rlInt8_t* format, ...);
1495 typedef struct rlDbgCb
1510 rlPrintFptr rlPrint;
1520 typedef struct rlClientCbs
1554 rlCrcType_t crcType;
1560 rlUInt32_t ackTimeout;
1571 rlUInt8_t arDevType;
1586 typedef struct rlInitComplete
1591 rlUInt32_t powerUpTime;
1628 rlUInt32_t powerUpStatus1;
1652 rlUInt32_t powerUpStatus2;
1689 rlUInt32_t bootTestStatus1;
1700 rlUInt32_t bootTestStatus2;
1708 typedef struct rlStartComplete
1746 rlUInt32_t powerUpTime;
1750 rlUInt32_t reserved0;
1754 rlUInt32_t reserved1;
1764 typedef struct rlMssEsmFault
1801 rlUInt32_t esmGrp1Err;
1837 rlUInt32_t esmGrp2Err;
1841 rlUInt32_t reserved0;
1845 rlUInt32_t reserved1;
1855 typedef struct rlMssBootErrStatus
1860 rlUInt32_t powerUpTime;
1897 rlUInt32_t powerUpStatus1;
1921 rlUInt32_t powerUpStatus2;
1958 rlUInt32_t bootTestStatus1;
1969 rlUInt32_t bootTestStatus2;
1977 typedef struct rlMssLatentFaultReport
2015 rlUInt32_t testStatusFlg1;
2026 rlUInt32_t testStatusFlg2;
2030 rlUInt32_t reserved;
2039 typedef struct rlMssPeriodicTestStatus
2048 rlUInt32_t testStatusFlg;
2052 rlUInt32_t reserved;
2061 typedef struct rlMssRfErrStatus
2074 rlUInt32_t errStatusFlg;
2078 rlUInt32_t reserved;
2087 typedef struct rlBssEsmFault
2116 rlUInt32_t esmGrp1Err;
2152 rlUInt32_t esmGrp2Err;
2159 typedef struct rlRfInitComplete
2181 rlUInt32_t calibStatus;
2186 rlUInt32_t calibUpdate;
2192 rlUInt16_t temperature;
2196 rlUInt16_t reserved0;
2202 rlUInt32_t timeStamp;
2206 rlUInt32_t reserved1;
2213 typedef struct rlRfRunTimeCalibReport
2234 rlUInt32_t calibErrorFlag;
2240 rlUInt32_t calibUpdateStatus;
2248 rlInt16_t temperature;
2252 rlUInt16_t reserved0;
2258 rlUInt32_t timeStamp;
2262 rlUInt32_t reserved1;
2275 typedef struct rlMonTypeTrigDoneStatus
2277 #ifndef MMWL_BIG_ENDIAN 2286 rlUInt8_t monTrigTypeDone;
2290 rlUInt8_t reserved0;
2295 rlUInt8_t reserved0;
2304 rlUInt8_t monTrigTypeDone;
2309 rlUInt16_t reserved1;
2314 rlUInt32_t timeStamp;
2318 rlUInt32_t reserved2;
2324 typedef struct rlRfApllCalDone
2326 rlUInt16_t apllClCalStatus;
2330 rlUInt16_t cccTolerance;
2334 rlUInt16_t cccCount0;
2338 rlUInt16_t measFreqCount;
2342 rlUInt32_t cccCount1;
2355 typedef struct rlCpuFault
2357 #ifndef MMWL_BIG_ENDIAN 2369 rlUInt8_t faultType;
2386 rlUInt8_t errorCode;
2404 rlUInt8_t errorCode;
2416 rlUInt8_t faultType;
2433 rlUInt32_t faultPrevLR;
2438 rlUInt32_t faultSpsr;
2447 rlUInt32_t faultAddr;
2460 rlUInt16_t faultErrStatus;
2461 #ifndef MMWL_BIG_ENDIAN 2468 rlUInt8_t faultErrSrc;
2474 rlUInt8_t faultAxiErrType;
2480 rlUInt8_t faultAccType;
2487 rlUInt8_t faultRecovType;
2494 rlUInt8_t faultAxiErrType;
2501 rlUInt8_t faultErrSrc;
2508 rlUInt8_t faultRecovType;
2514 rlUInt8_t faultAccType;
2519 rlUInt16_t reserved1;
2525 typedef struct rlFwVersionParam
2527 #ifndef MMWL_BIG_ENDIAN 2531 rlUInt8_t hwVarient;
2571 rlUInt8_t patchMajor;
2575 rlUInt8_t patchMinor;
2579 rlUInt8_t patchYear;
2583 rlUInt8_t patchMonth;
2593 rlUInt8_t patchBuildDebug;
2602 rlUInt8_t hwVarient;
2638 rlUInt8_t patchMinor;
2642 rlUInt8_t patchMajor;
2646 rlUInt8_t patchMonth;
2650 rlUInt8_t patchYear;
2656 rlUInt8_t patchBuildDebug;
2667 typedef struct rlSwVersionParam
2669 #ifndef MMWL_BIG_ENDIAN 2741 typedef struct rlVersion
2760 typedef struct rlGpAdcData
2780 typedef struct rlRecvdGpAdcData
2789 rlUInt16_t reserved0[4U];
2793 rlUInt32_t reserved1[7U];
2800 typedef struct rlAnalogFaultReportData
2802 #ifndef MMWL_BIG_ENDIAN 2810 rlUInt8_t faultType;
2814 rlUInt8_t reserved0;
2819 rlUInt8_t reserved0;
2827 rlUInt8_t faultType;
2832 rlUInt16_t reserved1;
2842 rlUInt32_t faultSig;
2846 rlUInt32_t reserved2;
2854 typedef struct rlCalMonTimingErrorReportData
2869 rlUInt16_t timingFailCode;
2870 rlUInt16_t reserved;
2877 typedef struct rlDigLatentFaultReportData
2910 rlUInt32_t digMonLatentFault;
2918 typedef struct rlMonReportHdrData
2923 rlUInt32_t fttiCount;
2932 rlUInt16_t reserved0;
2936 rlUInt32_t reserved1;
2944 typedef struct rlDigPeriodicReportData
2955 rlUInt32_t digMonPeriodicStatus;
2961 rlUInt32_t timeStamp;
2971 typedef struct rlMonTempReportData
2985 rlUInt16_t statusFlags;
2989 rlUInt16_t errorCode;
3007 rlInt16_t tempValues[10U];
3011 rlUInt32_t reserved;
3017 rlUInt32_t timeStamp;
3028 typedef struct rlMonRxGainPhRep
3041 rlUInt16_t statusFlags;
3045 rlUInt16_t errorCode;
3046 #ifndef MMWL_BIG_ENDIAN 3050 rlUInt8_t profIndex;
3064 rlUInt8_t loopbackPowerRF1;
3078 rlUInt8_t loopbackPowerRF2;
3092 rlUInt8_t loopbackPowerRF3;
3107 rlUInt8_t loopbackPowerRF1;
3111 rlUInt8_t profIndex;
3125 rlUInt8_t loopbackPowerRF3;
3139 rlUInt8_t loopbackPowerRF2;
3169 rlUInt16_t rxGainVal[12U];
3184 rlUInt16_t rxPhaseVal[12U];
3207 rlUInt32_t rxNoisePower1;
3230 rlUInt32_t rxNoisePower2;
3236 rlUInt32_t timeStamp;
3247 typedef struct rlMonRxNoiseFigRep
3257 rlUInt16_t statusFlags;
3261 rlUInt16_t errorCode;
3262 #ifndef MMWL_BIG_ENDIAN 3266 rlUInt8_t profIndex;
3270 rlUInt8_t reserved0;
3275 rlUInt8_t reserved0;
3279 rlUInt8_t profIndex;
3284 rlUInt16_t reserved1;
3298 rlUInt16_t rxNoiseFigVal[12U];
3302 rlUInt32_t reserved2;
3306 rlUInt32_t reserved3;
3310 rlUInt32_t reserved4;
3316 rlUInt32_t timeStamp;
3326 typedef struct rlMonRxIfStageRep
3338 rlUInt16_t statusFlags;
3342 rlUInt16_t errorCode;
3343 #ifndef MMWL_BIG_ENDIAN 3347 rlUInt8_t profIndex;
3351 rlUInt8_t reserved0;
3356 rlUInt8_t reserved0;
3360 rlUInt8_t profIndex;
3372 rlInt16_t lpfCutOffBandEdgeDroopValRx0;
3373 #ifndef MMWL_BIG_ENDIAN 3390 rlInt8_t hpfCutOffFreqEr[8U];
3404 rlInt8_t lpfCutOffStopBandAtten[8U];
3418 rlInt8_t rxIfaGainErVal[8U];
3427 rlUInt8_t reserved2;
3440 rlInt8_t lpfCutOffBandEdgeDroopValRx[6U];
3458 rlInt8_t hpfCutOffFreqEr[8U];
3472 rlInt8_t lpfCutOffStopBandAtten[8U];
3486 rlInt8_t rxIfaGainErVal[8U];
3490 rlUInt8_t reserved2;
3508 rlInt8_t lpfCutOffBandEdgeDroopValRx[6U];
3514 rlUInt32_t timeStamp;
3527 typedef struct rlMonTxPowRep
3538 rlUInt16_t statusFlags;
3542 rlUInt16_t errorCode;
3543 #ifndef MMWL_BIG_ENDIAN 3547 rlUInt8_t profIndex;
3551 rlUInt8_t reserved0;
3556 rlUInt8_t reserved0;
3560 rlUInt8_t profIndex;
3565 rlUInt16_t reserved1;
3577 rlInt16_t txPowVal[3U];
3581 rlUInt16_t reserved2;
3587 rlUInt32_t timeStamp;
3601 typedef struct rlMonTxBallBreakRep
3611 rlUInt16_t statusFlags;
3615 rlUInt16_t errorCode;
3620 rlInt16_t txReflCoefVal;
3624 rlUInt16_t reserved0;
3628 rlUInt32_t reserved1;
3634 rlUInt32_t timeStamp;
3644 typedef struct rlMonTxGainPhaMisRep
3655 rlUInt16_t statusFlags;
3659 rlUInt16_t errorCode;
3660 #ifndef MMWL_BIG_ENDIAN 3664 rlUInt8_t profIndex;
3670 rlUInt8_t noisePower00;
3676 rlUInt8_t noisePower01;
3682 rlUInt8_t noisePower02;
3689 rlUInt8_t noisePower00;
3693 rlUInt8_t profIndex;
3699 rlUInt8_t noisePower02;
3705 rlUInt8_t noisePower01;
3719 rlInt16_t txGainVal[9U];
3733 rlUInt16_t txPhaVal[9U];
3734 #ifndef MMWL_BIG_ENDIAN 3740 rlUInt8_t noisePower10;
3746 rlUInt8_t noisePower11;
3752 rlUInt8_t noisePower12;
3758 rlUInt8_t noisePower20;
3764 rlUInt8_t noisePower21;
3770 rlUInt8_t noisePower22;
3774 rlUInt8_t reserved0;
3778 rlUInt8_t reserved1;
3785 rlUInt8_t noisePower11;
3791 rlUInt8_t noisePower10;
3797 rlUInt8_t noisePower20;
3803 rlUInt8_t noisePower12;
3809 rlUInt8_t noisePower22;
3815 rlUInt8_t noisePower21;
3819 rlUInt8_t reserved1;
3823 rlUInt8_t reserved0;
3829 rlUInt32_t timeStamp;
3842 typedef struct rlMonTxPhShiftRep
3853 rlUInt16_t statusFlags;
3857 rlUInt16_t errorCode;
3858 #ifndef MMWL_BIG_ENDIAN 3862 rlUInt8_t profIndex;
3866 rlUInt8_t reserved0;
3871 rlUInt8_t reserved0;
3875 rlUInt8_t profIndex;
3880 rlUInt16_t reserved1;
3886 rlUInt16_t phaseShifterMonVal1;
3892 rlUInt16_t phaseShifterMonVal2;
3898 rlUInt16_t phaseShifterMonVal3;
3904 rlUInt16_t phaseShifterMonVal4;
3910 rlInt16_t txPsAmplitudeVal1;
3916 rlInt16_t txPsAmplitudeVal2;
3922 rlInt16_t txPsAmplitudeVal3;
3928 rlInt16_t txPsAmplitudeVal4;
3929 #ifndef MMWL_BIG_ENDIAN 3935 rlInt8_t txPsNoiseVal1;
3941 rlInt8_t txPsNoiseVal2;
3947 rlInt8_t txPsNoiseVal3;
3953 rlInt8_t txPsNoiseVal4;
3960 rlInt8_t txPsNoiseVal2;
3966 rlInt8_t txPsNoiseVal1;
3972 rlInt8_t txPsNoiseVal4;
3978 rlInt8_t txPsNoiseVal3;
3985 rlUInt32_t timeStamp;
3989 rlUInt32_t reserved2;
3993 rlUInt32_t reserved3;
4003 typedef struct rlMonSynthFreqRep
4013 rlUInt16_t statusFlags;
4017 rlUInt16_t errorCode;
4018 #ifndef MMWL_BIG_ENDIAN 4022 rlUInt8_t profIndex;
4026 rlUInt8_t reserved0;
4031 rlUInt8_t reserved0;
4035 rlUInt8_t profIndex;
4040 rlUInt16_t reserved1;
4048 rlInt32_t maxFreqErVal;
4058 rlUInt32_t freqFailCnt;
4062 rlUInt32_t reserved2;
4066 rlUInt32_t reserved3;
4072 rlUInt32_t timeStamp;
4082 typedef struct rlMonExtAnaSigRep
4097 rlUInt16_t statusFlags;
4101 rlUInt16_t errorCode;
4113 rlInt16_t extAnaSigVal[6U];
4117 rlUInt32_t reserved;
4123 rlUInt32_t timeStamp;
4135 typedef struct rlMonTxIntAnaSigRep
4146 rlUInt16_t statusFlags;
4150 rlUInt16_t errorCode;
4151 #ifndef MMWL_BIG_ENDIAN 4155 rlUInt8_t profIndex;
4159 rlUInt8_t reserved0;
4164 rlUInt8_t phShiftDacIdeltaMin;
4169 rlUInt8_t phShiftDacQdeltaMin;
4174 rlUInt8_t reserved0;
4178 rlUInt8_t profIndex;
4183 rlUInt8_t phShiftDacQdeltaMin;
4188 rlUInt8_t phShiftDacIdeltaMin;
4195 rlUInt32_t timeStamp;
4205 typedef struct rlMonRxIntAnaSigRep
4222 rlUInt16_t statusFlags;
4226 rlUInt16_t errorCode;
4227 #ifndef MMWL_BIG_ENDIAN 4231 rlUInt8_t profIndex;
4235 rlUInt8_t reserved0;
4240 rlUInt8_t reserved0;
4244 rlUInt8_t profIndex;
4249 rlUInt16_t reserved1;
4255 rlUInt32_t timeStamp;
4266 typedef struct rlMonPmclkloIntAnaSigRep
4280 rlUInt16_t statusFlags;
4284 rlUInt16_t errorCode;
4285 #ifndef MMWL_BIG_ENDIAN 4289 rlUInt8_t profIndex;
4302 rlInt8_t sync20GPower;
4316 rlInt8_t sync20GPower;
4320 rlUInt8_t profIndex;
4325 rlUInt16_t reserved;
4331 rlUInt32_t timeStamp;
4342 typedef struct rlMonGpadcIntAnaSigRep
4353 rlUInt16_t statusFlags;
4357 rlUInt16_t errorCode;
4363 rlInt16_t gpadcRef1Val;
4369 rlUInt16_t gpadcRef2Val;
4373 rlUInt32_t reserved;
4379 rlUInt32_t timeStamp;
4389 typedef struct rlMonPllConVoltRep
4405 rlUInt16_t statusFlags;
4409 rlUInt16_t errorCode;
4430 rlInt16_t pllContVoltVal[8U];
4434 rlUInt32_t reserved;
4440 rlUInt32_t timeStamp;
4450 typedef struct rlMonDccClkFreqRep
4464 rlUInt16_t statusFlags;
4468 rlUInt16_t errorCode;
4482 rlUInt16_t freqMeasVal[8U];
4486 rlUInt32_t reserved;
4492 rlUInt32_t timeStamp;
4503 typedef struct rlMonRxMixrInPwrRep
4516 rlUInt16_t statusFlags;
4520 rlUInt16_t errorCode;
4522 #ifndef MMWL_BIG_ENDIAN 4526 rlUInt8_t profIndex;
4530 rlUInt8_t reserved0;
4535 rlUInt8_t reserved0;
4539 rlUInt8_t profIndex;
4544 rlUInt16_t reserved1;
4557 rlUInt32_t rxMixInVolt;
4561 rlUInt32_t reserved2;
4566 rlUInt32_t timeStamp;
4577 typedef struct rlMonSynthFreqNonLiveRep
4588 rlUInt16_t statusFlags;
4592 rlUInt16_t errorCode;
4594 #ifndef MMWL_BIG_ENDIAN 4598 rlUInt8_t profIndex0;
4602 rlUInt8_t reserved0;
4607 rlUInt8_t reserved0;
4611 rlUInt8_t profIndex0;
4616 rlUInt16_t reserved1;
4624 rlInt32_t maxFreqErVal0;
4634 rlUInt32_t freqFailCnt0;
4640 rlUInt32_t maxFreqFailTime0;
4644 rlUInt32_t reserved2;
4646 #ifndef MMWL_BIG_ENDIAN 4650 rlUInt8_t profIndex1;
4654 rlUInt8_t reserved3;
4659 rlUInt8_t reserved3;
4663 rlUInt8_t profIndex1;
4668 rlUInt16_t reserved4;
4676 rlInt32_t maxFreqErVal1;
4686 rlUInt32_t freqFailCnt1;
4692 rlUInt32_t maxFreqFailTime1;
4696 rlUInt32_t reserved5;
4702 rlUInt32_t timeStamp;
4714 typedef struct rlMmwlErrorStatus
4719 #include <ti/control/mmwavelink/include/rl_device.h> 4720 #include <ti/control/mmwavelink/include/rl_sensor.h> 4721 #include <ti/control/mmwavelink/include/rl_monitoring.h> 4722 #include <ti/control/mmwavelink/include/rl_protocol.h> 4723 #include <ti/control/mmwavelink/include/rl_messages.h> This is the Monitoring report which RadarSS sends to the host, containing information about the relat...
mmWaveLink RF Run time calibration report for event RL_RF_AE_RUN_TIME_CALIB_REPORT_SB
This async event is sent periodically to indicate the status of periodic digital monitoring tests....
mmWaveLink client callback structure
This is the Monitoring report which RadarSS sends to the host, containing the measured RX noise figur...
mmWaveLink RF Init Complete data structure for event RL_RF_AE_INITCALIBSTATUS_SB
Sensors GPADC measurement data for event RL_RF_AE_GPADC_MEAS_DATA_SB.
Structure to hold the BSS ESM Fault data strucutre for event RL_RF_AE_ESMFAULT_SB.
mmWaveLink firmware version structure
Structure to hold the test status report of the latent fault tests data strucutre for event RL_DEV_AE...
mmWaveLink Report for event RL_RF_AE_MONITOR_TYPE_TRIGGER_DONE_SB. The triggered monitor types are do...
Communication interface(SPI, MailBox, UART etc) callback functions.
mmWaveLink CRC callback function
Calibration monitoring timing error data for event RL_RF_AE_MON_TIMING_FAIL_REPORT_SB.
This is the Monitoring report which RadarSS sends to the host, containing the measured temperature ne...
mmWaveLink Init Complete data structure for event RL_DEV_AE_MSSPOWERUPDONE_SB
This is the Monitoring report which RadarSS sends to the host, containing information about Internal ...
This API is a Monitoring report which RadarSS sends to the host, containing the measured RX gain and ...
This is an error status report internally generated from mmWaveLink when it finds any issue with the ...
This is the Monitoring report which RadarSS sends to the host, containing the measured TX reflection ...
This is the Monitoring report which RadarSS sends to the host, containing information about the measu...
This is the Monitoring report which the AWR device sends to the host, containing the measured TX phas...
OS semaphore callback functions.
mmWaveLink Device Control, Interrupt callback functions
This is the Monitoring report which RadarSS sends to the host, containing information related to meas...
mmWaveLink Timer callback functions
mmWaveLink debug callback structure
Analog fault strucure for event RL_RF_AE_ANALOG_FAULT_SB.
This is the Monitoring report which RadarSS sends to the host, containing the measured Tx gain and ph...
API APLL closed loop cal Status Get Sub block structure.
This is the Monitoring report which RadarSS sends to the host, containing information about Internal ...
This is the Monitoring report which RadarSS sends to the host, containing information about Internal ...
Structure to hold data strucutre for RF-error status send by MSS for event RL_DEV_AE_MSS_RF_ERROR_STA...
Latent fault digital monitoring status data for event RL_RF_AE_DIG_LATENTFAULT_REPORT_AE_SB.
This is the Monitoring report which RadarSS sends to the host, containing the measured PLL control vo...
GPADC measurement data for sensors.
This is a Non live Monitoring report which device sends to the host, containing information related t...
This is the Monitoring report which the xWR device sends to the host, containing the measured RX mixe...
Structure to hold the MSS Boot error status data strucutre when booted over SPI for event RL_DEV_AE_M...
Structure to hold the MSS ESM Fault data structure for event RL_DEV_AE_MSS_ESMFAULT_SB.
The report header includes common information across all enabled monitors like current FTTI number an...
mmwavelink software version structure
mmWaveLink callback functions for Command parser
OS mutex callback functions.
This is the Monitoring report which RadarSS sends to the host, containing the external signal voltage...
Structure to hold the MSS/radarSS CPU Fault data strucutre for event RL_DEV_AE_MSS_CPUFAULT_SB and RL...
mmwavelink version structure
Structure to hold data strucutre for test status of the periodic tests for event RL_DEV_AE_MSS_PERIOD...
mmWaveLink RF Start Complete data structure for event RL_DEV_AE_RFPOWERUPDONE_SB
mmWaveLink Asynchronous event callback function
This is the Monitoring report which RadarSS sends to the host, containing the measured RX IF filter a...
OS message queue/Spawn callback functions.
This is the Monitoring report which RadarSS sends to the host, containing the measured TX power value...
OS services callback functions.