mmwavelink.h
1 /*************************************************************************************************
2  * FileName : mmwavelink.h
3  *
4  * Description : This file includes all the header files which needs to be included by application
5  *
6  *************************************************************************************************
7  * (C) Copyright 2014, Texas Instruments Incorporated. - TI web address www.ti.com
8  *------------------------------------------------------------------------------------------------
9  *
10  * Redistribution and use in source and binary forms, with or without modification, are permitted
11  * provided that the following conditions are met:
12  *
13  * Redistributions of source code must retain the above copyright notice, this list of
14  * conditions and the following disclaimer.
15  *
16  * Redistributions in binary form must reproduce the above copyright notice, this list of
17  * conditions and the following disclaimer in the documentation and/or other materials provided
18  * with the distribution.
19  *
20  * Neither the name of Texas Instruments Incorporated nor the names of its contributors may be
21  * used to endorse or promote products derived from this software without specific prior
22  * written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
25  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
26  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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33  *
34  */
35 
36 /*************************************************************************************************
37  * FILE INCLUSION PROTECTION
38  *************************************************************************************************
39  */
40 #ifndef MMWAVELINK_H
41 #define MMWAVELINK_H
42 /*LDRA_NOANALYSIS*/
356 /*LDRA_ANALYSIS*/
357 
358  /****************************************************************************************
359  * INCLUDE FILES
360  *****************************************************************************************
361  */
362 #include <stdint.h>
363 #include <stdio.h>
364 #include <ti/control/mmwavelink/include/rl_datatypes.h>
365 
366 #ifdef __cplusplus
367 extern "C" {
368 #endif
369 
370 /*****************************************************************************************
371  * MACRO DEFINITIONS
372  *****************************************************************************************
373  */
374 
375 /* Export Macro for DLL */
376 #if defined(WIN32) || defined(WIN32_) || defined(_MSC_VER)
377 #define MMWL_EXPORT __declspec(dllexport)
378 #else
379 #define MMWL_EXPORT
380 #endif
381 
383 #define RL_MMWAVELINK_VERSION "2.2.2.1.13.8.20"
384 #define RL_MMWAVELINK_VERSION_MAJOR (2U)
385 #define RL_MMWAVELINK_VERSION_MINOR (2U)
386 #define RL_MMWAVELINK_VERSION_BUILD (2U)
387 #define RL_MMWAVELINK_VERSION_DEBUG (1U)
388 #define RL_MMWAVELINK_VERSION_DAY (13U)
389 #define RL_MMWAVELINK_VERSION_MONTH (8U)
390 #define RL_MMWAVELINK_VERSION_YEAR (20U)
391 
393 #define RL_RET_CODE_OK ((rlReturnVal_t)0) /* no-error */
394 #define RL_RET_CODE_PROTOCOL_ERROR (-1) /* mmWaveLink Protocol error */
395 #define RL_RET_CODE_INVALID_INPUT (-2) /* invalid input from the application */
396 #define RL_RET_CODE_SELF_ERROR (-3) /* error in mmWaveLink itself */
397 #define RL_RET_CODE_RADAR_IF_ERROR (-4) /* Radar HW/SW interface error */
398 #define RL_RET_CODE_MALLOC_ERROR (-5) /* memory allocation error */
399 #define RL_RET_CODE_CRC_FAILED (-6) /* CRC value mismatched wrt
400  received data */
401 #define RL_RET_CODE_CHKSUM_FAILED (-7) /* Checksum value mismatched wrt to
402  received data */
403 #define RL_RET_CODE_RESP_TIMEOUT (-8) /* device failed to send response
404  within time */
405 #define RL_RET_CODE_FATAL_ERROR (-9) /* Fatal error internal to
406  mmWaveLink APIs */
407 #define RL_RET_CODE_RADAR_OSIF_ERROR (-10) /* OS interface failure */
408 #define RL_RET_CODE_INVALID_STATE_ERROR (-11) /* Invalid state within mmWaveLink */
409 #define RL_RET_CODE_API_NOT_SUPPORTED (-12) /* API called is not supported */
410 #define RL_RET_CODE_MSGID_MISMATCHED (-13) /* Message-ID mismatched in
411  response data */
412 #define RL_RET_CODE_NULL_PTR (-14) /* Null pointer error */
413 #define RL_RET_CODE_INTERFACE_CB_NULL (-15) /* Interface callback passed as NULL */
414 #define RL_RET_CODE_NACK_ERROR (-16) /* If device sends NACK message */
415 #define RL_RET_CODE_HOSTIRQ_TIMEOUT (-17) /* If post writing CNYS HostIRQ is not
416  down within time limit and re-writing
417  CNYS also has same result */
418 #define RL_RET_CODE_RX_SEQ_NUM_NOT_MATCH (-18) /* ACK sequence number is not matching with
419  CMD sequence number */
420 
422 #define RL_RET_CODE_INVLD_OPCODE (1U) /* Incorrect opcode/Msg ID */
423 #define RL_RET_CODE_INVLD_NUM_SB (2U) /* Incorrect no. of Sub-Block */
424 #define RL_RET_CODE_INVLD_SB_ID (3U) /* Incorrect Sub-Block ID */
425 #define RL_RET_CODE_INVLD_SB_LEN (4U) /* Incorrect Sub-Block Length */
426 #define RL_RET_CODE_SB_INVL_DATA (5U) /* Incorrect Sub-Block Data */
427 #define RL_RET_CODE_SB_PROCESS_ERR (6U) /* Error in Sub Block processing */
428 #define RL_RET_CODE_MISMATCH_FILE_CRC (7U) /* Mismatch in File CRC */
429 #define RL_RET_CODE_MISMATCH_FILE_TYPE (8U) /* Mismatch in File Type */
430 
432 #define RL_RET_CODE_FRAME_ALREADY_STARTED (20U) /* Frames are already started when the
433  FRAME_START command was issued */
434 #define RL_RET_CODE_FRAME_ALREADY_ENDED (21U) /* Frames are already stopped when the
435  FRAME_STOP command was issued */
436 #define RL_RET_CODE_FRAME_CFG_NOT_RECVD (22U) /* No valid frame configuration API was
437  issued and frames are started */
438 #define RL_RET_CODE_FRAME_TRIG_INVL_IN (23U) /* START_STOP_CMD parameter is out of
439  range*/
440 
442 #define RL_RET_CODE_CH_CFG_RX_INVAL_IN (24U) /* RX_CHAN_EN parameter is out of range
443  may vary based on device */
444 #define RL_RET_CODE_CH_CFG_TX_INVAL_IN (25U) /* TX_CHAN_EN parameter is out of range
445  may vary based on device */
446 #define RL_RET_CODE_CH_CFG_CASC_INVAL_IN (26U) /* CASCADING_CFG parameter is out of
447  range [0, 2] */
448 
450 #define RL_RET_CODE_ADC_BITS_INVAL_IN (27U) /* NUM_ADC_BITS parameter is out of
451  range [0, 2] */
452 #define RL_RET_CODE_ADC_FORM_INVAL_IN (28U) /* ADC_OUT_FMT parameter is out of
453  range [0, 3] */
454 
456 #define RL_RET_CODE_LP_ADC_INVAL_IN (29U) /* LP_ADC_MODE parameter is out of
457  range [0, 1] */
458 
460 #define RL_RET_CODE_DYN_PS_INVAL_IN (30U) /* BLOCK_CFG parameter is out of
461  range [0, 7] */
462 
464 #define RL_RET_CODE_HSI_DIV_INVAL_IN (31U) /* HSI clock rate code[1:0] is 0 */
465 #define RL_RET_CODE_RESERVED0 (32U)
466 #define RL_RET_CODE_HSI_DIV_INVAL_1IN (33U) /* HSI clock rate code[3:2] is 3 &
467  HSI clock rate code[1:0] is 2 */
468 #define RL_RET_CODE_HSI_DIV_INVAL_2IN (34U) /* HSI clock rate code[3:2] is 3 &
469  HSI clock rate code[1:0] is 2 */
470 
472 #define RL_RET_CODE_PF_IND_INVAL_IN (35U) /* PF indx >= 4 */
473 #define RL_RET_CODE_PF_START_FREQ_INVAL_IN (36U) /* PF freq const is not
474  with[76GHz,81GHz] in limit */
475 #define RL_RET_CODE_PF_IDLE_TIME_INVAL_IN (37U) /* PF idle time const > 5.24ms */
476 #define RL_RET_CODE_PF_IDLE_TIME_1INVAL_IN (38U) /* Maximum DFE spill time (refer
477  rampgen calculator in mmWaveStudio
478  for more details) > PF idle
479  time const */
480 #define RL_RET_CODE_PF_ADC_START_INVAL_IN (39U) /* PF ADC start time const > 4095 */
481 #define RL_RET_CODE_PF_RAMP_END_INVAL_IN (40U) /* PF ramp end time > 524287 */
482 #define RL_RET_CODE_PF_RAMP_END_1INVAL_IN (41U) /* PF ramp end time < PF ADC start
483  time const + ADC sampling time */
484 #define RL_RET_CODE_PF_TX0_INVAL_IN (42U) /* PF_TX_OUTPUT_POWER_BACKOFF for
485  TX0 > 30 */
486 #define RL_RET_CODE_PF_TX1_INVAL_IN (43U) /* PF_TX_OUTPUT_POWER_BACKOFF for
487  TX1 > 30 */
488 #define RL_RET_CODE_PF_TX2_INVAL_IN (44U) /* PF_TX_OUTPUT_POWER_BACKOFF for
489  TX2 > 30 */
490 #define RL_RET_CODE_RESERVED1 (45U)
491 #define RL_RET_CODE_PF_FREQ_SLOPE_1INVAL_IN (46U) /* Ramp end freq is not
492  with[76GHz,81GHz] in limits */
493 #define RL_RET_CODE_PF_TX_START_INVAL_IN (47U) /* Absolute value of TX_START_TIME
494  is > 38.45us */
495 #define RL_RET_CODE_PF_NUM_ADC_SMAP_INVAL_IN (48U) /* Number of ADC samples is not
496  within [2,8192] */
497 #define RL_RET_CODE_PF_DFE_SAMP_RATE_INVAL_IN (49U) /* Output sampling rate is not
498  within [2, 37.5]Msps */
499 #define RL_RET_CODE_PF_HPF1_CF_INVAL_IN (50U) /* HPF1 corner frequency > 700 kHz */
500 #define RL_RET_CODE_PF_HPF2_CF_INVAL_IN (51U) /* HPF2 corner frequency > 2.8 MHz */
501 #define RL_RET_CODE_PF_RX_GAIN_INVAL_IN (52U) /* PF_RX_GAIN is not within [24, 52] dB
502  orPF_RX_GAIN is an odd number */
503 #define RL_RET_CODE_RESERVED2 (53U)
504 #define RL_RET_CODE_RESERVED3 (54U)
505 #define RL_RET_CODE_RESERVED4 (55U)
506 #define RL_RET_CODE_RESERVED5 (56U)
507 #define RL_RET_CODE_RESERVED6 (57U)
508 #define RL_RET_CODE_RESERVED7 (58U)
509 
511 #define RL_RET_CODE_CHIRP_START_INVAL_IN (59U) /* Chirp Start indx >= 512 */
512 #define RL_RET_CODE_CHIRP_END_INVAL_IN (60U) /* Chirp End indx >= 512 */
513 #define RL_RET_CODE_CHIRP_END_1INVAL_IN (61U) /* Chirp Start indx > Chirp End indx */
514 #define RL_RET_CODE_CHIRP_PF_IND_INVAL_IN (62U) /* PF indx >= 4 */
515 #define RL_RET_CODE_CHIRP_PF_IND_1INVAL_IN (63U) /* PF corresponding to PF indx is not
516  defined */
517 #define RL_RET_CODE_CHIRP_START_FREQ_INVAL_IN (64U) /* Chirp freq start > 8388607 */
518 #define RL_RET_CODE_CHIRP_SLOPE_INVAL_IN (65U) /* Chirp freq slope > 63 */
519 #define RL_RET_CODE_CHIRP_SLOPE_1INVAL_IN (66U) /* Chirp start or end
520  freq[76GHz,81GHz] is outside */
521 #define RL_RET_CODE_CHIRP_IDLE_TIME_INVAL_IN (67U) /* Chirp Idle time > 4095 */
522 #define RL_RET_CODE_CHIRP_ADC_START_INVAL_IN (68U) /* Chirp ADC start time > 4095 */
523 #define RL_RET_CODE_CHIRP_ADC_START_1INVAL_IN (69U) /* Ramp end time < ADC start time +
524  ADC sampling time */
525 #define RL_RET_CODE_CHIRP_TX_ENA_INVAL_IN (70U) /* Chirp TX enable > 7 */
526 #define RL_RET_CODE_CHIRP_TX_ENA_1INVAL_IN (71U) /* Chirp TX enable indicates to enable
527  a TX which is not enabled in
528  Channel config */
529 
531 #define RL_RET_CODE_FRAME_CHIRP_STR_INVAL_IN (72U) /* Chirp Start indx >= 512 */
532 #define RL_RET_CODE_FRAME_CHIRP_END_INVAL_IN (73U) /* Chirp End indx >= 512 */
533 #define RL_RET_CODE_FRAME_CHIRP_END_1INVAL_IN (74U) /* Chirp Start indx > Chirp End indx */
534 #define RL_RET_CODE_FRAME_CHIRP_END_2INVAL_IN (75U) /* Chirp used in frame is not
535  configured by Chirp config */
536 #define RL_RET_CODE_FRAME_CHIRP_PF_INVAL_IN (76U) /* Profile used in frame is not
537  configured by PF config */
538 #define RL_RET_CODE_FRAME_CHIRP_LOOPS_INVAL_IN (77U) /* No. of loops is outside[1,255] */
539 #define RL_RET_CODE_RESERVED8 (78U)
540 #define RL_RET_CODE_FRAME_PERIOD_INVAL_IN (79U) /* Frame periodicity is
541  outside[100us,1.342s] */
542 #define RL_RET_CODE_FRAME_PERIOD_1INVAL_IN (80U) /* Frame ON time > Frame periodicity */
543 #define RL_RET_CODE_FRAME_TRIG_SEL_INVAL_IN (81U) /* Trigger select is outside[1,2] */
544 #define RL_RET_CODE_FRAME_TRIG_DELAY_INVAL_IN (82U) /* Frame Trigger delay > 100us */
545 #define RL_RET_CODE_FRAME_IS_ONGOING (83U) /* API issued when frame is ongoing */
546 #define RL_RET_CODE_FRAME_DUMMY_CHIRPS_INVAL_IN (160U) /* The Dummy chirps at end of frame
547  is not supported */
548 
550 #define RL_RET_CODE_AFRAME_NUM_SUBF_INVAL_IN (84U) /* No. Sub Frames is outside[1,4] */
551 #define RL_RET_CODE_AFRAME_FORCE_PF_INVAL_IN (85U) /* Force single Profile is
552  outside[1,4] */
553 #define RL_RET_CODE_AFRAME_PF_IND_INVAL_IN (86U) /* Force single Profile >= 4 */
554 #define RL_RET_CODE_AFRAME_PF_IND_1INVAL_IN (87U) /* Profile defined by Force Single
555  Profile is not defined */
556 #define RL_RET_CODE_AFRAME_CHIRP_STR_INVAL_IN (88U) /* Sub Frame Chirp Start indx >= 512 */
557 #define RL_RET_CODE_AFRAME_NCHIRP_INVAL_IN (89U) /* Sub Frame NO. of unique chirps per
558  Burst is outside[1,512] */
559 #define RL_RET_CODE_AFRAME_NCHIRP_1INVAL_IN (90U) /* Chirp used in frame is not
560  configured by Chirp config */
561 #define RL_RET_CODE_AFRAME_CHIRP_PF_INVAL_IN (91U) /* Profie used in the frame is not
562  configured by profile config */
563 #define RL_RET_CODE_AFRAME_CHIRP_LOOPS_INVAL_IN (92U) /* Sub Frame No. of loops is
564  outside[1,225] */
565 #define RL_RET_CODE_AFRAME_BURST_PERIOD_INVAL_IN (93U) /* Sub Frame burst period is
566  outside[100us,1.342s] */
567 #define RL_RET_CODE_AFRAME_BURST_PER_1INVAL_IN (94U) /* Burst ON time > Burst period */
568 #define RL_RET_CODE_AFRAME_BURST_STIND_INVAL_IN (95U) /* Sub Frame Chirp start indx
569  offset >= 512 */
570 #define RL_RET_CODE_AFRAME_BURST_SIND_1INVAL_IN (96U) /* Sub Frame Chirp start indx >= 512
571  or (Sub Frame Chirp start indx +
572  Sub Frame No. unique Chirps per
573  burst - 1) >= 512*/
574 #define RL_RET_CODE_AFRAME_NUM_BURSTS_INVAL_IN (97U) /* Sub Frame No. bursts is
575  outside[1,512] */
576 #define RL_RET_CODE_AFRAME_BURST_LOOPS_INVAL_IN (98U) /* Sub Frame No. outer loops is
577  outside[1,64] */
578 #define RL_RET_CODE_AFRAME_SF_PERIOD_INVAL_IN (99U) /* Sub Frame period is
579  outside[100us,1.342s] */
580 #define RL_RET_CODE_AFRAME_SF_PERIOD_1INVAL_IN (100U) /* Sub Frame ontime > Sub Frame period
581  or when test source enabled, Sub
582  Frame idale time < 150us */
583 #define RL_RET_CODE_RESERVED9 (101U)
584 #define RL_RET_CODE_AFRAME_TRIG_SEL_INVAL_IN (102U) /* Trigger select is outside[1,2] */
585 #define RL_RET_CODE_AFRAME_TRIG_DELAY_INVAL_IN (103U) /* Frame trigger delay is > 100us */
586 #define RL_RET_CODE_AFRAME_IS_ONGOING (104U) /* API issued when frame is ongoing */
587 
589 #define RL_RET_CODE_TS_POS_VECY_INVAL_IN (105U) /* position vector x[y] < 0 */
590 #define RL_RET_CODE_RESERVED10 (106U)
591 #define RL_RET_CODE_TS_VEL_VECXYZ_INVAL_IN (107U) /* position vector x[x] < 5000 or
592  position vector x[y] < 5000 or
593  position vector x[x] < 5000 */
594 #define RL_RET_CODE_TS_SIG_LEVEL_INVAL_IN (108U) /* SIG_LEV_VECx > 950 */
595 #define RL_RET_CODE_TS_RX_ANT_POS_INVAL_IN (109U) /* RX_ANT_POS_XZ[Bytex] > 120 */
596 #define RL_RET_CODE_RESERVED11 (110U)
597 
599 #define RL_RET_CODE_PROG_FILT_STARTINDX_INVALID (111U) /* Prog. Filter coefficient start
600  indx is odd number */
601 #define RL_RET_CODE_PROG_FILT_PROFILE_INVALID (112U) /* Pro indx >= 4 */
602 #define RL_RET_CODE_PROG_FILT_UNSUPPORTED_DEV (113U) /* API issued for non AWR1642 device*/
603 
605 #define RL_RET_CODE_PERCHIRPPHSHIFT_UNSUPPORTED_DEV (114U) /* API issued for non AWR1243/AWR2243
606  device */
607 #define RL_RET_CODE_PERCHIRPPHSHIFT_STIND (115U) /* Chirp Start indx >= 512 */
608 #define RL_RET_CODE_PERCHIRPPHSHIFT_ENIND (116U) /* Chirp End indx >= 512 */
609 #define RL_RET_CODE_PERCHIRPPHSHIFT_WRONG_STIND (117U) /* Chirp Start indx > End indx */
610 
612 #define RL_RET_CODE_RF_INIT_NOT_DONE (118U) /* Boot time calibrations are not
613  done so cannot run runtime calibrations */
614 #define RL_RET_CODE_FORCE_TEMP_BIN_IDX_INVALID (286U) /* The forced temperature bin index
615  is invalid */
616 #define RL_RET_CODE_FREQ_LIMIT_OUT_RANGE (119U) /* Freq. is outside[76GHz,81GHz] or
617  Freq. low limit > high limit */
618 #define RL_RET_CODE_CAL_MON_TIME_INVALID (120U) /* CALIB_MON_TIME_UNIT <= 0 */
619 #define RL_RET_CODE_RUN_CAL_PERIOD_INVALID (121U) /* CALIBRATION_ PERIODICITY = 0 */
620 #define RL_RET_CODE_CONT_STREAM_MODE_EN (122U) /* API is issued when continuous
621  streaming mode is on */
622 #define RL_RET_CODE_RX_GAIN_BOOT_CAL_NOT_DONE (123U) /* RX gain run time calibration was
623  requested but boot time calibration
624  was not performed */
625 #define RL_RET_CODE_LO_DIST_BOOT_CAL_NOT_DONE (124U) /* LO distribution run time
626  calibration was requested but boot time
627  calibration was not performed */
628 #define RL_RET_CODE_TX_PWR_BOOT_CAL_NOT_DONE (125U) /* TX power run time calibration was
629  requested but boot time calibration
630  was not performed */
631 #define RL_RET_CODE_PROG_FILTR_UNSUPPORTED_DFEMODE (126U) /* DFE mode is pseudo real */
632 #define RL_RET_CODE_ADC_BITS_FULL_SCALE_REDUC_INVAL (127U) /* FULL_SCALE_REDUCTION_FACTOR is > 0
633  for 16 bit ADC, or > 2 for 14 bit
634  ADC mode or > 4 for 12 bit ADC mode */
635 #define RL_RET_CODE_CAL_MON_NUM_CASC_DEV_INVALID (128U) /* NUM_OF_CASCADED_DEV <= 0 */
636 #define RL_RET_CODE_FRAME_TRIG_INVL_STOP_IN (129U)/* Frame stop option-4 cannot be used
637  in SW Triggered mode */
638 #define RL_RET_CODE_RF_FREQBAND_INVALID (130U) /* Minimum RF frequency is < 200MHz */
639 
641 #define RL_RET_CODE_INVAL_LOOPBACK_TYPE (132U)
642 #define RL_RET_CODE_INVAL_LOOPBACK_BURST_IND (133U)
643 #define RL_RET_CODE_INVAL_LOOPBACK_CONFIG (134U)
644 #define RL_RET_CODE_DYN_CHIRP_INVAL_SEG (135U)
645 #define RL_RET_CODE_DYN_PERCHIRP_PHSHFT_INVA_SEG (136U)
646 #define RL_RET_CODE_INVALID_CAL_CHUNK_ID (137U)
647 #define RL_RET_CODE_INVALID_CAL_CHUNK_DATA (138U)
648 
650 #define RL_RET_CODE_RX02_RF_TURN_OFF_TIME_INVALID (139U) /* RX02_RF_TURN_OFF_TIME is not
651  within the range [-1024, 1023] */
652 #define RL_RET_CODE_RX13_RF_TURN_OFF_TIME_INVALID (140U) /* RX13_RF_TURN_OFF_TIME is not
653  within the range [-1024, 1023] */
654 #define RL_RET_CODE_RX02_BB_TURN_OFF_TIME_INVALID (141U) /* RX02_BB_TURN_OFF_TIME is not
655  within the range [-1024, 1023] */
656 #define RL_RET_CODE_RX13_BB_TURN_OFF_TIME_INVALID (142U) /* RX13_BB_TURN_OFF_TIME is not
657  within the range [-1024, 1023] */
658 #define RL_RET_CODE_RX02_RF_PREENABLE_TIME_INVALID (143U) /* RX02_RF_PREENABLE_TIME is not
659  within the range [-1024, 1023] */
660 #define RL_RET_CODE_RX13_RF_PREENABLE_TIME_INVALID (144U) /* RX13_RF_PREENABLE_TIME is not
661  within the range [-1024, 1023] */
662 #define RL_RET_CODE_RX02_BB_PREENABLE_TIME_INVALID (145U) /* RX02_BB_PREENABLE_TIME is not
663  within the range [-1024, 1023] */
664 #define RL_RET_CODE_RX13_BB_PREENABLE_TIME_INVALID (146U) /* RX13_BB_PREENABLE_TIME is not
665  within the range [-1024, 1023] */
666 #define RL_RET_CODE_RX02_RF_TURN_ON_TIME_INVALID (147U) /* RX02_RF_TURN_ON_TIME is not
667  within the range [-1024, 1023] */
668 #define RL_RET_CODE_RX13_RF_TURN_ON_TIME_INVALID (148U) /* RX13_RF_TURN_ON_TIME is not
669  within the range [-1024, 1023] */
670 #define RL_RET_CODE_RX02_BB_TURN_ON_TIME_INVALID (149U) /* RX02_BB_TURN_ON_TIME is not
671  within the range [-1024, 1023] */
672 #define RL_RET_CODE_RX13_BB_TURN_ON_TIME_INVALID (150U) /* RX13_BB_TURN_ON_TIME is not
673  within the range [-1024, 1023] */
674 #define RL_RET_CODE_RX_LO_TURN_OFF_TIME_INVALID (151U) /* RX_LO_TURN_OFF_TIME is not
675  within the range [-1024, 1023] */
676 #define RL_RET_CODE_TX_LO_TURN_OFF_TIME_INVALID (152U) /* TX_LO_TURN_OFF_TIME is not
677  within the range [-1024, 1023] */
678 #define RL_RET_CODE_RX_LO_TURN_ON_TIME_INVALID (153U) /* RX_LO_TURN_ON_TIME is not
679  within the range [-1024, 1023] */
680 #define RL_RET_CODE_TX_LO_TURN_ON_TIME_INVALID (154U) /* TX_LO_TURN_ON_TIME is not
681  within the range [-1024, 1023] */
682 #define RL_RET_CODE_SUBFRAME_TRIGGER_INVALID (155U) /* Sub frame trigger option is not
683  enabled but sub frame trigger API
684  is issued or frame is configured
685  for software trigger mode and
686  sub-frame trigger API is issued */
687 #define RL_RET_CODE_REGULAR_ADC_MODE_INVALID (156U) /* Regular ADC mode is issued on a
688  5 MHz part variant */
689 #define RL_RET_CODE_CHIRP_ROW_SELECT_INVAL_IN (159U) /* Chirp row select is not with in
690  the range [0x00, 0x30] */
691 
692 #define RL_RET_CODE_DEVICE_NOT_ASILB_TYPE (250U) /* Device type is not ASILB */
693 #define RL_RET_CODE_FRAME_ONGOING (251U) /* Fault injection API or Digital
694  latent fault API is issued when
695  frames are ongoing */
696 #define RL_RET_CODE_INVLD_REPO_MODE (252U) /* Invalid reporting mode */
697 #define RL_RET_CODE_INVLD_PROFILE_ID (253U) /* Configured profile ID is not
698  within [0,3] */
699 #define RL_RET_CODE_INVLD_PROFILE (254U) /* Monitoring profile ID is not
700  configured yet */
701 #define RL_RET_CODE_INVLD_EXTSIG_SETLTIME (255U) /* Settling time is configured is
702  more than 12us */
703 #define RL_RET_CODE_INVLD_NO_RX_ENABLED (256U) /* None of the RXs are enabled */
704 #define RL_RET_CODE_INVLD_TX0_NOT_ENABLED (257U) /* TX0 is not enabled */
705 #define RL_RET_CODE_INVLD_TX1_NOT_ENABLED (258U) /* TX1 is not enabled */
706 #define RL_RET_CODE_INVLD_TX2_NOT_ENABLED (259U) /* TX2 is not enabled */
707 #define RL_RET_CODE_MON_INVALID_RF_BIT_MASK (260U) /* Invalid RF bit mask */
708 #define RL_RET_CODE_RESERVED12 (261U)
709 #define RL_RET_CODE_RESERVED13 (262U)
710 #define RL_RET_CODE_MON_TX_EN_CHK_FAIL (263U) /* Monitored TX is not enabled */
711 #define RL_RET_CODE_MON_RX_CH_EN_CHK_FAIL (264U) /* Monitored RX is not enabled */
712 #define RL_RET_CODE_MON_TX_CH_PS_LB (265U) /* TX selected for RX gain phase
713  monitor is TX2 (Only TX0 or TX1 is
714  allowed) */
715 #define RL_RET_CODE_INVLD_SAT_MON_SEL (266U) /* SAT_MON_SEL is not in [0, 3] */
716 #define RL_RET_CODE_INVLD_SAT_MON_PRI_SLICE_DUR (267U) /* SAT_MON_PRIMARY_TIME_SLICE_DURATION
717  is less than 0.64us or greater
718  than ADC sampling time */
719 #define RL_RET_CODE_INVLD_SAT_MON_NUM_SLICES (268U) /* SAT_MON_NUM_SLICES is 0 or
720  greater than 127 */
721 #define RL_RET_CODE_INVLD_SIG_IMG_SLICENUM (269U) /* SIG_IMG_MON_NUM_SLICES is 0 or
722  greater than 127 */
723 #define RL_RET_CODE_INVLD_SIG_IMG_NUMSAMPPERSLICE (270U) /* NUM_SAMPLES_ PER_PRIMARY_TIME_SLICE
724  is odd, or less than 4 in Complex1x
725  mode or less than 8 in non-Complex1x
726  modes or greater than NUM_ADC_SAMPLES*/
727 #define RL_RET_CODE_INVLD_SYNTH_L1_LIN (271U)
728 #define RL_RET_CODE_INVLD_SYNTH_L2_LIN (272U)
729 #define RL_RET_CODE_INVLD_SYNTH_N_LIN (273U)
730 #define RL_RET_CODE_INVLD_SYNTH_MON_START_TIME (274U) /* MONITOR_START_TIME is outside the
731  specified range. */
732 #define RL_RET_CODE_INVLD_SYNTH_MON_LIN_RAM_ADDR (275U)
733 #define RL_RET_CODE_LDO_BYPASSED (279U) /* LDO fault inject is requested but
734  LDOs are bypassed */
735 #define RL_RET_CODE_INVLD_SIG_IMG_BAND_MONTR (280U) /* Signal and image band monitor is
736  not supported */
737 #define RL_RET_CODE_ANALOG_MONITOR_NOT_SUPPORTED (281U)
738 #define RL_RET_CODE_ISSUE_TO_ENABLE_CASCASE_MODE (282U) /* Device variant does not allow
739  cascading but API is issued to
740  enable cascading mode */
741 #define RL_RET_CODE_RX_SAT_MON_NOT_SUPPORTED (283U)
742 #define RL_API_NRESP_ANA_MON_MODE_NOT_API_BASED (284U) /* Monitoring trigger API is not
743  supported in autonomous mode
744  of operation */
745 #define RL_API_NRESP_ANA_MON_TRIG_TYPE_INVALID (285U) /* Monitoring trigger bit masks
746  are all zeros in
747  AWR_MONITOR_TYPE_TRIG_CONF_SB */
748 
749 #define RL_RET_CODE_CHIRP_FAIL (290U) /* Monitoring chirp error */
750 #define RL_RET_CODE_PD_PWR_LVL (291U) /* Loopback power measured by PD
751  is below -40 dBm */
752 #define RL_RET_CODE_ADC_PWR_LVL (292U) /* ADC power is higher than 7 dBm */
753 #define RL_RET_CODE_NOISE_FIG_LOW (293U) /* Noise figure is less than 0 */
754 #define RL_RET_CODE_PD_CDS_ON_FAIL (294U) /* PD measurement with RF on is less
755  than with RF off */
756 #define RL_RET_CODE_PGA_GAIN_FAIL (295U) /* Incorrect PGA gain for monitoring*/
757 #define RL_RET_CODE_20G_MONITOR_NOT_SUPPORTED (296U) /* The 20G monitor is not supported
758  in single chip configuration */
759 #define RL_RET_CODE_MONITOR_CONFIG_MODE_INVALID (297U) /* MONITOR_CONFIG_MODE is invalid. */
760 #define RL_RET_CODE_LIVE_NONLIVE_TOGETHER_INVALID (298U) /* Both Live and Non-live synth
761  frequency monitors are cannot be
762  enabled together. */
763 
764 /* Advanced Chirp config API */
765 #define RL_RET_CODE_CHIRP_PARAM_IND_INVALID (300U) /* Invalid CHIRP_PARAM_INDEX */
766 #define RL_RET_CODE_RESET_MODE_INVALID (301U) /* Invalid GLOBAL_RESET_MODE */
767 #define RL_RET_CODE_DEL_LUT_PAR_UPT_PER_INVALID (303U) /* Invalid update period
768  DELTA_PARAM_UPDATE_PERIOD or
769  LUT_PARAM_UPDATE_PERIOD */
770 #define RL_RET_CODE_SF_CHIRP_PAR_DEL_INVALID (304U) /* Invalid fixed delta parameter
771  SFn_CHIRP_PARAM_DELTA */
772 #define RL_RET_CODE_DEL_LUT_RESET_PERIOD_INVALID (305U) /* Invalid reset period
773  DELTA_RESET_PERIOD or
774  LUT_RESET_PERIOD*/
775 #define RL_RET_CODE_LUT_PAT_ADD_OFF_INVALID (306U) /* Invalid LUT address
776  LUT_PATTERN_ADDRESS_OFFSET */
777 #define RL_RET_CODE_LUT_NUM_PATTERNS_INVALID (307U) /* Invalid number of patterns in
778  LUT NUM_OF_PATTERNS */
779 #define RL_RET_CODE_LUT_SF_BURST_IND_OFF_INVALID (308U) /* Invalid LUT index offset value
780  BURST_LUT_INDEX_OFFSET or
781  SF_LUT_INDEX_OFFSET */
782 #define RL_RET_CODE_LUT_CHIRP_PAR_SCALE_SIZE_INVALID (309U) /* Invalid LUT_CHIRP_PARAM_SIZE and
783  LUT_CHIRP_PARAM_SCALE */
784 #define RL_RET_CODE_LEGACY_API_INPUTS_INVALID (310U) /* Invalid legacy APIs are issued
785  when advance chirp config API is
786  enabled or vice-versa */
787 #define RL_RET_CODE_ALL_CHIRP_PARAMS_NOT_DEFINED (311U) /* All chirp parameters are not
788  defined in advance chirp API */
789 #define RL_RET_CODE_TX_PHASE_SHIF_INT_INVALID (312U) /* Invalid TX phase shifter dither
790  value */
791 #define RL_RET_CODE_NUM_PATTERNS_PROGRAM_INVALID (313U) /* Insufficient number of
792  NUM_OF_PATTERNS programmed compared
793  to actual programmed chirps
794  (array out of bound error) */
795 #define RL_RET_CODE_NUM_CHIRPS_PROGRAM_INVALID (315U) /* Invalid num of chirps programmed
796  in frame config API */
797 #define RL_RET_CODE_TX_PH_SHIFT_PHASE_MASK_INVALID (316U) /* Invalid phase mask or at least one
798  of the phase should be enabled for
799  monitoring */
800 #define RL_RET_CODE_TX_PH_SHIFT_RX_MASK_INVALID (317U) /* Invalid RX mask or the RX mask is
801  not enabled in channel
802  configuration API */
803 
804 /* Advanced Chirp Generic LUT Load API */
805 #define RL_RET_CODE_NUM_BYTES_PROGRAM_INVALID (314U) /* Invalid num of bytes */
806 
807 #define RL_RET_CODE_TX_IND_PH_SHIFT_RESTORE_INVALID (318U) /* Invalid TX index in phase shifter
808  restore API */
809 
810 /* ADC Config API */
811 #define RL_RET_CODE_RX_CHAN_EN_OOR (1001U) /* numADCBits out of Range */
812 #define RL_RET_CODE_NUM_ADC_BITS_OOR (1002U) /* rxChannelEn out of Range */
813 #define RL_RET_CODE_ADC_OUT_FMT_OOR (1003U) /* adcOutFormat out of Range */
814 #define RL_RET_CODE_IQ_SWAP_SEL_OOR (1004U) /* sampleInterleave out of
815  Range */
816 #define RL_RET_CODE_CHAN_INTERLEAVE_OOR (1005U) /* channelInterleave out of
817  Range */
818 
819 /* Data Path Config API */
820 #define RL_RET_CODE_DATA_INTF_SEL_OOR (1006U) /* dataIntfSel out of Range */
821 #define RL_RET_CODE_DATA_FMT_PKT0_INVALID (1007U) /* dataTransPkt0Format
822  Unsupporetd */
823 #define RL_RET_CODE_DATA_FMT_PKT1_INVALID (1008U) /* dataTransPkt1Format
824  Unsupporetd */
825 
826 /* Lane Enable config API */
827 #define RL_RET_CODE_LANE_ENABLE_OOR (1009U) /* laneEnable is out of range */
828 #define RL_RET_CODE_LANE_ENABLE_INVALID (1010U) /* laneEnable is not supported */
829 
830 /* Lane Clock config API */
831 #define RL_RET_CODE_LANE_CLK_CFG_OOR (1011U) /* laneClkCfg is out of range */
832 #define RL_RET_CODE_LANE_CLK_CFG_INVALID (1012U) /* laneClkCfg is not supported */
833 #define RL_RET_CODE_DATA_RATE_OOR (1013U) /* dataRate is out of range */
834 
835 /* LVDS config API */
836 #define RL_RET_CODE_LANE_FMT_MAP_OOR (1014U) /* laneFmtMap is out of range */
837 #define RL_RET_CODE_LANE_PARAM_CFG_OOR (1015U) /* laneParamCfg is out of range */
838 
839 /* Continuous Streaming Mode API */
840 #define RL_RET_CODE_CONT_STREAM_MODE_OOR (1016U) /* contStreamMode is out of
841  range */
842 #define RL_RET_CODE_CONT_STREAM_MODE_INVALID (1017U) /* contStreamMode is already
843  in requested mode */
844 
845 /* CSI2 Lane Config API */
846 #define RL_RET_CODE_LANE0_POS_POL_OOR (1018U) /* lane0 pos is out of range */
847 #define RL_RET_CODE_LANE1_POS_POL_OOR (1019U) /* lane1 pos is out of range */
848 #define RL_RET_CODE_LANE2_POS_POL_OOR (1020U) /* lane2 pos is out of range */
849 #define RL_RET_CODE_LANE3_POS_POL_OOR (1021U) /* lane3 pos is out of range */
850 #define RL_RET_CODE_CLOCK_POS_OOR (1022U) /* ClockPos is out of range */
851 
852 /* Frame Config Apply API */
853 #define RL_RET_CODE_HALF_WORDS_PER_CHIRP_OOR (1023U) /* adcOutSize is out of range */
854 
855 /* Advanced Frame Config API */
856 #define RL_RET_CODE_NUM_SUBFRAMES_OOR (1024U) /* numSubFrames is out of range */
857 
858 #define RL_RET_CODE_SF1_TOT_NUM_CHIRPS_OOR (1025U) /* totNumChirps is out of range */
859 #define RL_RET_CODE_SF1_NUM_ADC_SAMP_OOR (1026U) /* numADCSamplesInPkt is out
860  of range */
861 #define RL_RET_CODE_SF1_NUM_CHIRPS_OOR (1027U) /* numChirpsInPkt is out of
862  range */
863 
864 #define RL_RET_CODE_SF2_TOT_NUM_CHIRPS_OOR (1028U) /* totNumChirps is out of
865  range */
866 #define RL_RET_CODE_SF2_NUM_ADC_SAMP_OOR (1029U) /* numADCSamplesInPkt is out
867  of range */
868 #define RL_RET_CODE_SF2_NUM_CHIRPS_OOR (1030U) /* numChirpsInPkt is out of
869  range */
870 
871 #define RL_RET_CODE_SF3_TOT_NUM_CHIRPS_OOR (1031U) /* totNumChirps is out of
872  range */
873 #define RL_RET_CODE_SF3_NUM_ADC_SAMP_OOR (1032U) /* numADCSamplesInPkt is out of
874  range */
875 #define RL_RET_CODE_SF3_NUM_CHIRPS_OOR (1033U) /* numChirpsInPkt is out of
876  range */
877 
878 #define RL_RET_CODE_SF4_TOT_NUM_CHIRPS_OOR (1034U) /* totNumChirps is out of
879  range */
880 #define RL_RET_CODE_SF4_NUM_ADC_SAMP_OOR (1035U) /* numADCSamplesInPkt is out of
881  range */
882 #define RL_RET_CODE_SF4_NUM_CHIRPS_OOR (1036U) /* numChirpsInPkt is out of range */
883 
884 #define RL_RET_CODE_MCUCLOCK_CTRL_OOR (1040U) /* mcuClkOutEn is out of range */
885 #define RL_RET_CODE_MCUCLOCK_SRC_OOR (1041U) /* mcuClkOutSrc is out of range */
886 
887 #define RL_RET_CODE_PMICCLOCK_CTRL_OOR (1042U) /* pmicClkOutEn is out of range */
888 #define RL_RET_CODE_PMICCLOCK_SRC_OOR (1043U) /* pmicClkOutSrc is out of range */
889 #define RL_RET_CODE_PMICMODE_SELECT_OOR (1044U) /* modeSel is out of range */
890 #define RL_RET_CODE_PMICFREQ_SLOPE_OOR (1045U) /* freqSlope is out of range */
891 #define RL_RET_CODE_PMICCLK_DITHER_EN_OOR (1046U) /* clkDitherEn is out of range */
892 
893 #define RL_RET_CODE_TESTPATTERN_EN_OOR (1047U) /* testPatternGenEn is out of
894  range */
895 #define RL_RET_CODE_LFAULTTEST_UNSUPPORTED_OOR (1048U) /* Data interface selected in
896  RL_DEV_RX_DATA_PATH_CONF_SET_SB
897  is SPI */
898 
899 #define RL_API_NRESP_LFAULTTEST_UNSUPPORTED_OOR (1051U) /* Unsupported Latent Fault test
900  selected in
901  RL_DEV_LATENTFAULT_TEST_CONF_SB */
902 #define RL_API_NRESP_DATACONFIG_NOTDONE (1052U) /* Invoking
903  AWR_DEV_ADV_FRAME_CONFIG_APPLY_SB
904  message without configuring
905  data path */
906 
912 #define RL_DISABLE_LOGGING 1
913 
914 /* mmwavelink MACROs for Error Checks */
915 #define RL_OSI_RET_CODE_OK (0)
916 #define RL_IF_RET_CODE_OK (0)
917 
918 #ifdef RL_EXTENDED_MESSAGE /* build time MACRO to change message size */
919 /* if mmWaveLink instance is running inside xWR1443/1642 device then Max size of packet can
920  be (2048 -4) bytes, where 4 bytes are reserved for mailbox header */
921 #define RL_MAX_SIZE_MSG (2044U)
922 #else
923 #define RL_MAX_SIZE_MSG (256U)
924 #endif
925 
926 
937 #define RL_DEVICE_MAP_NATIVE (0U)
938 #define RL_DEVICE_MAP_CASCADED_1 (1U)
939 #define RL_DEVICE_MAP_CASCADED_2 (2U)
940 #define RL_DEVICE_MAP_CASCADED_3 (4U)
941 #define RL_DEVICE_MAP_CASCADED_4 (8U)
943 /* AWR2243 Device Map - Max Cascading */
944 #define RL_DEVICE_MAP_CASCADED_ALL (RL_DEVICE_MAP_CASCADED_1 |\
945  RL_DEVICE_MAP_CASCADED_2 |\
946  RL_DEVICE_MAP_CASCADED_3 |\
947  RL_DEVICE_MAP_CASCADED_4)
948 
949 /* Device Index for SubSystem */
950 #define RL_DEVICE_INDEX_INTERNAL_BSS (0U)
951 #define RL_DEVICE_INDEX_INTERNAL_DSS_MSS (1U)
952 #define RL_DEVICE_INDEX_INTERNAL_HOST (2U)
955 #define RL_DEVICE_MAP_INTERNAL_BSS (RL_DEVICE_MAP_CASCADED_1)
957 #define RL_DEVICE_MAP_INTERNAL_DSS_MSS (RL_DEVICE_MAP_CASCADED_2)
958 #define RL_DEVICE_MAP_INTERNAL_HOST (RL_DEVICE_MAP_CASCADED_3)
961 #define RL_DEVICE_CONNECTED_MAX (4U)
962 
978 #ifndef RL_CASCADE_NUM_DEVICES
979 #define RL_CASCADE_NUM_DEVICES (1U)
980 #endif
981 
985 #define RL_CRC_TYPE_16BIT_CCITT (0U)
986 #define RL_CRC_TYPE_32BIT (1U)
987 #define RL_CRC_TYPE_64BIT_ISO (2U)
988 #define RL_CRC_TYPE_NO_CRC (3U)
993 #define RL_PLATFORM_HOST (0x0U)
994 #define RL_PLATFORM_MSS (0x1U)
995 #define RL_PLATFORM_DSS (0x2U)
1000 #define RL_AR_DEVICETYPE_12XX (0x0U)
1001 #define RL_AR_DEVICETYPE_14XX (0x1U)
1002 #define RL_AR_DEVICETYPE_16XX (0x2U)
1003 #define RL_AR_DEVICETYPE_18XX (0x3U)
1004 #define RL_AR_DEVICETYPE_68XX (0x4U)
1005 #define RL_AR_DEVICETYPE_22XX (0x5U)
1010 #define RL_DBG_LEVEL_NONE ((rlUInt8_t)0U)
1011 #define RL_DBG_LEVEL_DATABYTE ((rlUInt8_t)1U)
1012 #define RL_DBG_LEVEL_ERROR ((rlUInt8_t)2U)
1013 #define RL_DBG_LEVEL_WARNING ((rlUInt8_t)3U)
1014 #define RL_DBG_LEVEL_INFO ((rlUInt8_t)4U)
1015 #define RL_DBG_LEVEL_DEBUG ((rlUInt8_t)5U)
1016 #define RL_DBG_LEVEL_VERBOSE ((rlUInt8_t)6U)
1017 
1021 #define RL_SENSOR_ANALOGTEST_ONE (0U)
1022 #define RL_SENSOR_ANALOGTEST_TWO (1U)
1023 #define RL_SENSOR_ANALOGTEST_THREE (2U)
1024 #define RL_SENSOR_ANALOGTEST_FOUR (3U)
1025 #define RL_SENSOR_ANAMUX (4U)
1026 #define RL_SENSOR_VSENSE (5U)
1027 #define RL_MAX_GPADC_SENSORS (6U)
1028 
1032 #define RL_SWAP_32(x) (((x) & 0x0000FFFFU)<<16U)|(((x) & 0xFFFF0000U)>>16U);
1033 
1034 /******************************************************************************
1035  * TYPE-DEFINE STRUCT/ENUM/UNION DEFINITIONS
1036  ******************************************************************************
1037  */
1038 
1039 /* DesignId : MMWL_DesignId_001 */
1040 /* Requirements : AUTORADAR_REQ-697, AUTORADAR_REQ-698, AUTORADAR_REQ-699, AUTORADAR_REQ-700,
1041  AUTORADAR_REQ-701, AUTORADAR_REQ-702, AUTORADAR_REQ-703, AUTORADAR_REQ-704,
1042  AUTORADAR_REQ-705, AUTORADAR_REQ-706, AUTORADAR_REQ-830, AUTORADAR_REQ-831,
1043  AUTORADAR_REQ-832, AUTORADAR_REQ-888, AUTORADAR_REQ-889, AUTORADAR_REQ-890
1044 */
1045 
1049 typedef rlInt32_t rlReturnVal_t;
1050 
1054 typedef rlUInt8_t rlCrcType_t;
1055 
1056 /* Function pointers for spawn task function and event handlers*/
1057 
1061 typedef void (*RL_P_OSI_SPAWN_ENTRY)(const void* pValue);
1062 
1066 typedef void (*RL_P_EVENT_HANDLER)(rlUInt8_t deviceIndex, void* pValue);
1067 
1071 typedef struct rlComIfCbs
1072 {
1083  /* DesignId : MMWL_DesignId_004 */
1084  /* Requirements : AUTORADAR_REQ-785 */
1085  rlComIfHdl_t (*rlComIfOpen)(rlUInt8_t deviceIndex, rlUInt32_t flags);
1086 
1098  /* DesignId : MMWL_DesignId_004 */
1099  /* Requirements : AUTORADAR_REQ-785 */
1100  rlInt32_t (*rlComIfRead)(rlComIfHdl_t fd, rlUInt8_t *pBuff, rlUInt16_t len);
1101 
1113  /* DesignId : */
1114  /* Requirements : AUTORADAR_REQ-785 */
1115  rlInt32_t (*rlComIfWrite)(rlComIfHdl_t fd, rlUInt8_t *pBuff, rlUInt16_t len);
1116 
1126  /* DesignId : MMWL_DesignId_004 */
1127  /* Requirements : AUTORADAR_REQ-785 */
1128  rlInt32_t (*rlComIfClose)(rlComIfHdl_t fd);
1129 }rlComIfCbs_t;
1130 
1134 typedef struct rlOsiMutexCbs
1135 {
1146  /* DesignId : MMWL_DesignId_004 */
1147  /* Requirements : AUTORADAR_REQ-784 */
1148  rlInt32_t (*rlOsiMutexCreate)(rlOsiMutexHdl_t* mutexHdl, rlInt8_t* name);
1149 
1172  /* DesignId : MMWL_DesignId_004 */
1173  /* Requirements : AUTORADAR_REQ-784 */
1174  rlInt32_t (*rlOsiMutexLock)(rlOsiMutexHdl_t* mutexHdl, rlOsiTime_t timeout);
1175 
1186  /* DesignId : MMWL_DesignId_004 */
1187  /* Requirements : AUTORADAR_REQ-784 */
1188  rlInt32_t (*rlOsiMutexUnLock)(rlOsiMutexHdl_t* mutexHdl);
1189 
1199  /* DesignId : MMWL_DesignId_004 */
1200  /* Requirements : AUTORADAR_REQ-784 */
1201  rlInt32_t (*rlOsiMutexDelete)(rlOsiMutexHdl_t* mutexHdl);
1203 
1207 typedef struct rlOsiSemCbs
1208 {
1219  /* DesignId : MMWL_DesignId_004 */
1220  /* Requirements : AUTORADAR_REQ-784 */
1221  rlInt32_t (*rlOsiSemCreate)(rlOsiSemHdl_t* semHdl, rlInt8_t* name);
1222 
1233  /* DesignId : MMWL_DesignId_004 */
1234  /* Requirements : AUTORADAR_REQ-784 */
1235  rlInt32_t (*rlOsiSemWait)(rlOsiSemHdl_t* semHdl, rlOsiTime_t timeout);
1236 
1246  /* DesignId : MMWL_DesignId_004 */
1247  /* Requirements : AUTORADAR_REQ-784 */
1248  rlInt32_t (*rlOsiSemSignal)(rlOsiSemHdl_t* semHdl);
1249 
1259  /* DesignId : MMWL_DesignId_004 */
1260  /* Requirements : AUTORADAR_REQ-784 */
1261  rlInt32_t (*rlOsiSemDelete)(rlOsiSemHdl_t* semHdl);
1262 }rlOsiSemCbs_t;
1263 
1267 typedef struct rlOsiMsgQCbs
1268 {
1284  /* DesignId : MMWL_DesignId_004 */
1285  /* Requirements : AUTORADAR_REQ-784 */
1286  rlInt32_t (*rlOsiSpawn)(RL_P_OSI_SPAWN_ENTRY pEntry, const void* pValue, rlUInt32_t flags);
1288 
1289 
1293 typedef struct rlOsiCbs
1294 {
1298  rlOsiMutexCbs_t mutex;
1302  rlOsiSemCbs_t sem;
1306  rlOsiMsgQCbs_t queue;
1307 }rlOsiCbs_t;
1308 
1312 typedef struct rlEventCbs
1313 {
1327  /* DesignId : MMWL_DesignId_004 */
1328  /* Requirements : AUTORADAR_REQ-783 */
1329  void (*rlAsyncEvent)(rlUInt8_t devIndex, rlUInt16_t subId, rlUInt16_t subLen,
1330  rlUInt8_t *payload);
1331 }rlEventCbs_t;
1336 typedef struct rlTimerCbs
1337 {
1338  rlInt32_t (*rlDelay)(rlUInt32_t delay);
1340 
1344 typedef struct rlCmdParserCbs
1345 {
1346  rlInt32_t (*rlCmdParser)(rlUInt8_t rxMsgClass, rlInt32_t inVal);
1347  rlInt32_t (*rlPostCnysStep)(rlUInt8_t devIndex);
1349 
1356 typedef struct rlCrcCbs
1357 {
1372  /* DesignId : */
1373  /* Requirements : */
1374  rlInt32_t (*rlComputeCRC)(rlUInt8_t* data, rlUInt32_t dataLen, rlUInt8_t crcType,
1375  rlUInt8_t* crc);
1376 }rlCrcCbs_t;
1377 
1381 typedef struct rlDeviceCtrlCbs
1382 {
1393  /* DesignId : MMWL_DesignId_004 */
1394  /* Requirements : AUTORADAR_REQ-786 */
1395  rlInt32_t (*rlDeviceEnable)(rlUInt8_t deviceIndex);
1396 
1407  /* DesignId : MMWL_DesignId_004 */
1408  /* Requirements : AUTORADAR_REQ-786 */
1409  rlInt32_t (*rlDeviceDisable)(rlUInt8_t deviceIndex);
1410 
1419  /* DesignId : MMWL_DesignId_004 */
1420  /* Requirements : AUTORADAR_REQ-787 */
1421  void (*rlDeviceMaskHostIrq)(rlComIfHdl_t fd);
1422 
1431  /* DesignId : MMWL_DesignId_004 */
1432  /* Requirements : AUTORADAR_REQ-787 */
1433  void (*rlDeviceUnMaskHostIrq)(rlComIfHdl_t fd);
1434 
1450  /* DesignId :MMWL_DesignId_004 */
1451  /* Requirements : AUTORADAR_REQ-787 */
1452  rlInt32_t (*rlDeviceWaitIrqStatus)(rlComIfHdl_t fd, rlUInt8_t highLow);
1453 
1463  /* DesignId : MMWL_DesignId_004 */
1464  /* Requirements : AUTORADAR_REQ-787 */
1465  rlUInt16_t (*rlCommIfAssertIrq)(rlUInt8_t highLow);
1466 
1482  /* DesignId : MMWL_DesignId_026 */
1483  /* Requirements : AUTORADAR_REQ-777 */
1484  rlInt32_t (*rlRegisterInterruptHandler)(rlUInt8_t deviceIndex,
1485  RL_P_EVENT_HANDLER pHandler, void* pValue);
1490 typedef rlInt32_t (*rlPrintFptr)(const rlInt8_t* format, ...);
1491 
1495 typedef struct rlDbgCb
1496 {
1508  /* DesignId : */
1509  /* Requirements : */
1510  rlPrintFptr rlPrint;
1514  rlUInt8_t dbgLevel;
1515 }rlDbgCb_t;
1516 
1520 typedef struct rlClientCbs
1521 {
1525  rlComIfCbs_t comIfCb;
1529  rlOsiCbs_t osiCb;
1533  rlEventCbs_t eventCb;
1537  rlDeviceCtrlCbs_t devCtrlCb;
1541  rlTimerCbs_t timerCb;
1546  rlCmdParserCbs_t cmdParserCb;
1550  rlCrcCbs_t crcCb;
1554  rlCrcType_t crcType;
1560  rlUInt32_t ackTimeout;
1566  rlUInt8_t platform;
1571  rlUInt8_t arDevType;
1575  rlDbgCb_t dbgCb;
1576 }rlClientCbs_t;
1577 
1585 /* Sub block ID: 0x5000, ICD API: AWR_AE_DEV_MSSPOWERUPDONE_SB */
1586 typedef struct rlInitComplete
1587 {
1591  rlUInt32_t powerUpTime;
1628  rlUInt32_t powerUpStatus1;
1652  rlUInt32_t powerUpStatus2;
1689  rlUInt32_t bootTestStatus1;
1700  rlUInt32_t bootTestStatus2;
1702 
1707  /* Sub block ID: 0x5001, ICD API: AWR_AE_DEV_RFPOWERUPDONE_SB */
1708 typedef struct rlStartComplete
1709 {
1742  rlUInt32_t status;
1746  rlUInt32_t powerUpTime;
1750  rlUInt32_t reserved0;
1754  rlUInt32_t reserved1;
1756 
1763  /* Sub block ID: 0x5003, ICD API: AWR_AE_MSS_ESMFAULT_STATUS_SB */
1764 typedef struct rlMssEsmFault
1765 {
1801  rlUInt32_t esmGrp1Err;
1837  rlUInt32_t esmGrp2Err;
1841  rlUInt32_t reserved0;
1845  rlUInt32_t reserved1;
1847 
1854  /* Sub block ID: 0x5005, ICD API: AWR_AE_MSS_BOOTERRORSTATUS_SB */
1855 typedef struct rlMssBootErrStatus
1856 {
1860  rlUInt32_t powerUpTime;
1897  rlUInt32_t powerUpStatus1;
1921  rlUInt32_t powerUpStatus2;
1958  rlUInt32_t bootTestStatus1;
1969  rlUInt32_t bootTestStatus2;
1971 
1976  /* Sub block ID: 0x5006, ICD API: AWR_AE_MSS_LATENTFAULT_TESTREPORT_SB */
1977 typedef struct rlMssLatentFaultReport
1978 {
2015  rlUInt32_t testStatusFlg1;
2026  rlUInt32_t testStatusFlg2;
2030  rlUInt32_t reserved;
2032 
2038  /* Sub block ID: 0x5007, ICD API: AWR_AE_MSS_PERIODICTEST_STATUS_SB */
2039 typedef struct rlMssPeriodicTestStatus
2040 {
2048  rlUInt32_t testStatusFlg;
2052  rlUInt32_t reserved;
2054 
2060  /* Sub block ID: 0x5008, ICD API: AWR_AE_MSS_RFERROR_STATUS_SB */
2061 typedef struct rlMssRfErrStatus
2062 {
2074  rlUInt32_t errStatusFlg;
2078  rlUInt32_t reserved;
2080 
2086  /* Sub block ID: 0x1003, ICD API: AWR_AE_RF_ESMFAULT_SB */
2087 typedef struct rlBssEsmFault
2088 {
2116  rlUInt32_t esmGrp1Err;
2152  rlUInt32_t esmGrp2Err;
2154 
2158 /* Sub block ID: 0x1004, ICD API: AWR_AE_RF_INITCALIBSTATUS_SB */
2159 typedef struct rlRfInitComplete
2160 {
2181  rlUInt32_t calibStatus;
2186  rlUInt32_t calibUpdate;
2192  rlUInt16_t temperature;
2196  rlUInt16_t reserved0;
2202  rlUInt32_t timeStamp;
2206  rlUInt32_t reserved1;
2208 
2212  /* Sub block ID: 0x1012, ICD API: AWR_RUN_TIME_CALIB_SUMMARY_REPORT_AE_SB */
2213 typedef struct rlRfRunTimeCalibReport
2214 {
2234  rlUInt32_t calibErrorFlag;
2240  rlUInt32_t calibUpdateStatus;
2248  rlInt16_t temperature;
2252  rlUInt16_t reserved0;
2258  rlUInt32_t timeStamp;
2262  rlUInt32_t reserved1;
2264 
2274 /* Sub block ID: 0x100A, ICD API: AWR_AE_RF_MONITOR_TYPE_TRIGGER_DONE_SB */
2275 typedef struct rlMonTypeTrigDoneStatus
2276 {
2277 #ifndef MMWL_BIG_ENDIAN
2286  rlUInt8_t monTrigTypeDone;
2290  rlUInt8_t reserved0;
2291 #else
2292 
2295  rlUInt8_t reserved0;
2304  rlUInt8_t monTrigTypeDone;
2305 #endif
2306 
2309  rlUInt16_t reserved1;
2314  rlUInt32_t timeStamp;
2318  rlUInt32_t reserved2;
2320 
2324 typedef struct rlRfApllCalDone
2325 {
2326  rlUInt16_t apllClCalStatus;
2330  rlUInt16_t cccTolerance;
2334  rlUInt16_t cccCount0;
2338  rlUInt16_t measFreqCount;
2342  rlUInt32_t cccCount1;
2344 
2353  /* Sub block ID: 0x1002, ICD API: AWR_AE_RF_CPUFAULT_SB */
2354  /* Sub block ID: 0x5002, ICD API: AWR_AE_MSS_CPUFAULT_SB */
2355 typedef struct rlCpuFault
2356 {
2357 #ifndef MMWL_BIG_ENDIAN
2369  rlUInt8_t faultType;
2386  rlUInt8_t errorCode;
2387 #else
2388 
2404  rlUInt8_t errorCode;
2416  rlUInt8_t faultType;
2417 #endif
2418 
2422  rlUInt16_t lineNum;
2427  rlUInt32_t faultLR;
2433  rlUInt32_t faultPrevLR;
2438  rlUInt32_t faultSpsr;
2442  rlUInt32_t faultSp;
2447  rlUInt32_t faultAddr;
2460  rlUInt16_t faultErrStatus;
2461 #ifndef MMWL_BIG_ENDIAN
2462 
2468  rlUInt8_t faultErrSrc;
2474  rlUInt8_t faultAxiErrType;
2480  rlUInt8_t faultAccType;
2487  rlUInt8_t faultRecovType;
2488 #else
2489 
2494  rlUInt8_t faultAxiErrType;
2501  rlUInt8_t faultErrSrc;
2508  rlUInt8_t faultRecovType;
2514  rlUInt8_t faultAccType;
2515 #endif
2516 
2519  rlUInt16_t reserved1;
2520 }rlCpuFault_t;
2521 
2525 typedef struct rlFwVersionParam
2526 {
2527 #ifndef MMWL_BIG_ENDIAN
2531  rlUInt8_t hwVarient;
2535  rlUInt8_t hwMajor;
2539  rlUInt8_t hwMinor;
2543  rlUInt8_t fwMajor;
2547  rlUInt8_t fwMinor;
2551  rlUInt8_t fwBuild;
2555  rlUInt8_t fwDebug;
2559  rlUInt8_t fwYear;
2563  rlUInt8_t fwMonth;
2567  rlUInt8_t fwDay;
2571  rlUInt8_t patchMajor;
2575  rlUInt8_t patchMinor;
2579  rlUInt8_t patchYear;
2583  rlUInt8_t patchMonth;
2587  rlUInt8_t patchDay;
2593  rlUInt8_t patchBuildDebug;
2594 #else
2595 
2598  rlUInt8_t hwMajor;
2602  rlUInt8_t hwVarient;
2606  rlUInt8_t fwMajor;
2610  rlUInt8_t hwMinor;
2614  rlUInt8_t fwBuild;
2618  rlUInt8_t fwMinor;
2622  rlUInt8_t fwYear;
2626  rlUInt8_t fwDebug;
2630  rlUInt8_t fwDay;
2634  rlUInt8_t fwMonth;
2638  rlUInt8_t patchMinor;
2642  rlUInt8_t patchMajor;
2646  rlUInt8_t patchMonth;
2650  rlUInt8_t patchYear;
2656  rlUInt8_t patchBuildDebug;
2660  rlUInt8_t patchDay;
2661 #endif
2663 
2667 typedef struct rlSwVersionParam
2668 {
2669 #ifndef MMWL_BIG_ENDIAN
2673  rlUInt8_t major;
2677  rlUInt8_t minor;
2681  rlUInt8_t build;
2685  rlUInt8_t debug;
2689  rlUInt8_t year;
2693  rlUInt8_t month;
2697  rlUInt8_t day;
2701  rlUInt8_t reserved;
2702 #else
2703 
2706  rlUInt8_t minor;
2710  rlUInt8_t major;
2714  rlUInt8_t debug;
2718  rlUInt8_t build;
2722  rlUInt8_t month;
2726  rlUInt8_t year;
2730  rlUInt8_t reserved;
2734  rlUInt8_t day;
2735 #endif
2737 
2741 typedef struct rlVersion
2742 {
2746  rlFwVersionParam_t master;
2750  rlFwVersionParam_t rf;
2754  rlSwVersionParam_t mmWaveLink;
2755 }rlVersion_t;
2756 
2760 typedef struct rlGpAdcData
2761 {
2765  rlUInt16_t min;
2769  rlUInt16_t max;
2773  rlUInt16_t avg;
2774 } rlGpAdcData_t;
2775 
2779 /* Sub block ID: 0x100C, ICD API: AWR_AE_RF_GPADC_RESULT_DATA_SB */
2780 typedef struct rlRecvdGpAdcData
2781 {
2785  rlGpAdcData_t sensor[RL_MAX_GPADC_SENSORS];
2789  rlUInt16_t reserved0[4U];
2793  rlUInt32_t reserved1[7U];
2795 
2799 /* Sub block ID: 0x1010, ICD API: AWR_ANALOGFAULT_AE_SB */
2800 typedef struct rlAnalogFaultReportData
2801 {
2802 #ifndef MMWL_BIG_ENDIAN
2810  rlUInt8_t faultType;
2814  rlUInt8_t reserved0;
2815 #else
2816 
2819  rlUInt8_t reserved0;
2827  rlUInt8_t faultType;
2828 #endif
2829 
2832  rlUInt16_t reserved1;
2842  rlUInt32_t faultSig;
2846  rlUInt32_t reserved2;
2848 
2853 /* Sub block ID: 0x1011, ICD API: AWR_CAL_MON_TIMING_FAIL_REPORT_AE_SB */
2854 typedef struct rlCalMonTimingErrorReportData
2855 {
2869  rlUInt16_t timingFailCode;
2870  rlUInt16_t reserved;
2876 /* Sub block ID: 0x1013, ICD API: AWR_MONITOR_RF_DIG_LATENTFAULT_REPORT_AE_SB */
2877 typedef struct rlDigLatentFaultReportData
2878 {
2910  rlUInt32_t digMonLatentFault;
2912 
2917 /* Sub block ID: 0x1015, ICD API: AWR_MONITOR_REPORT_HEADER_AE_SB */
2918 typedef struct rlMonReportHdrData
2919 {
2923  rlUInt32_t fttiCount;
2928  rlUInt16_t avgTemp;
2932  rlUInt16_t reserved0;
2936  rlUInt32_t reserved1;
2938 
2943 /* Sub block ID: 0x1016, ICD API: AWR_MONITOR_RF_DIG_PERIODIC_REPORT_AE_SB */
2944 typedef struct rlDigPeriodicReportData
2945 {
2955  rlUInt32_t digMonPeriodicStatus;
2961  rlUInt32_t timeStamp;
2963 
2970 /* Sub block ID: 0x1017, ICD API: AWR_MONITOR_TEMPERATURE_REPORT_AE_SB */
2971 typedef struct rlMonTempReportData
2972 {
2985  rlUInt16_t statusFlags;
2989  rlUInt16_t errorCode;
3007  rlInt16_t tempValues[10U];
3011  rlUInt32_t reserved;
3017  rlUInt32_t timeStamp;
3019 
3027 /* Sub block ID: 0x1018, ICD API: AWR_MONITOR_RX_GAIN_PHASE_REPORT_AE_SB */
3028 typedef struct rlMonRxGainPhRep
3029 {
3041  rlUInt16_t statusFlags;
3045  rlUInt16_t errorCode;
3046 #ifndef MMWL_BIG_ENDIAN
3047 
3050  rlUInt8_t profIndex;
3064  rlUInt8_t loopbackPowerRF1;
3078  rlUInt8_t loopbackPowerRF2;
3092  rlUInt8_t loopbackPowerRF3;
3093 #else
3094 
3107  rlUInt8_t loopbackPowerRF1;
3111  rlUInt8_t profIndex;
3125  rlUInt8_t loopbackPowerRF3;
3139  rlUInt8_t loopbackPowerRF2;
3140 #endif
3141 
3169  rlUInt16_t rxGainVal[12U];
3184  rlUInt16_t rxPhaseVal[12U];
3207  rlUInt32_t rxNoisePower1;
3230  rlUInt32_t rxNoisePower2;
3236  rlUInt32_t timeStamp;
3238 
3246 /* Sub block ID: 0x1019, ICD API: AWR_MONITOR_RX_NOISE_FIGURE_REPORT_AE_SB */
3247 typedef struct rlMonRxNoiseFigRep
3248 {
3257  rlUInt16_t statusFlags;
3261  rlUInt16_t errorCode;
3262 #ifndef MMWL_BIG_ENDIAN
3263 
3266  rlUInt8_t profIndex;
3270  rlUInt8_t reserved0;
3271 #else
3272 
3275  rlUInt8_t reserved0;
3279  rlUInt8_t profIndex;
3280 #endif
3281 
3284  rlUInt16_t reserved1;
3298  rlUInt16_t rxNoiseFigVal[12U];
3302  rlUInt32_t reserved2;
3306  rlUInt32_t reserved3;
3310  rlUInt32_t reserved4;
3316  rlUInt32_t timeStamp;
3318 
3325 /* Sub block ID: 0x101A, ICD API: AWR_MONITOR_RX_IFSTAGE_REPORT_AE_SB */
3326 typedef struct rlMonRxIfStageRep
3327 {
3338  rlUInt16_t statusFlags;
3342  rlUInt16_t errorCode;
3343 #ifndef MMWL_BIG_ENDIAN
3344 
3347  rlUInt8_t profIndex;
3351  rlUInt8_t reserved0;
3352 #else
3353 
3356  rlUInt8_t reserved0;
3360  rlUInt8_t profIndex;
3361 #endif
3362 
3372  rlInt16_t lpfCutOffBandEdgeDroopValRx0;
3373 #ifndef MMWL_BIG_ENDIAN
3374 
3390  rlInt8_t hpfCutOffFreqEr[8U];
3404  rlInt8_t lpfCutOffStopBandAtten[8U];
3418  rlInt8_t rxIfaGainErVal[8U];
3423  rlInt8_t ifGainExp;
3427  rlUInt8_t reserved2;
3440  rlInt8_t lpfCutOffBandEdgeDroopValRx[6U];
3441 #else
3442 
3458  rlInt8_t hpfCutOffFreqEr[8U];
3472  rlInt8_t lpfCutOffStopBandAtten[8U];
3486  rlInt8_t rxIfaGainErVal[8U];
3490  rlUInt8_t reserved2;
3495  rlInt8_t ifGainExp;
3508  rlInt8_t lpfCutOffBandEdgeDroopValRx[6U];
3509 #endif
3510 
3514  rlUInt32_t timeStamp;
3516 
3524 /* Sub block ID: 0x101B, ICD API: AWR_MONITOR_TX0_POWER_REPORT_AE_SB */
3525 /* Sub block ID: 0x101C, ICD API: AWR_MONITOR_TX1_POWER_REPORT_AE_SB */
3526 /* Sub block ID: 0x101D, ICD API: AWR_MONITOR_TX2_POWER_REPORT_AE_SB */
3527 typedef struct rlMonTxPowRep
3528 {
3538  rlUInt16_t statusFlags;
3542  rlUInt16_t errorCode;
3543 #ifndef MMWL_BIG_ENDIAN
3544 
3547  rlUInt8_t profIndex;
3551  rlUInt8_t reserved0;
3552 #else
3553 
3556  rlUInt8_t reserved0;
3560  rlUInt8_t profIndex;
3561 #endif
3562 
3565  rlUInt16_t reserved1;
3577  rlInt16_t txPowVal[3U];
3581  rlUInt16_t reserved2;
3587  rlUInt32_t timeStamp;
3589 
3598 /* Sub block ID: 0x101E, ICD API: AWR_MONITOR_TX0_BALLBREAK_REPORT_AE_SB */
3599 /* Sub block ID: 0x101F, ICD API: AWR_MONITOR_TX1_BALLBREAK_REPORT_AE_SB */
3600 /* Sub block ID: 0x1020, ICD API: AWR_MONITOR_TX2_BALLBREAK_REPORT_AE_SB */
3601 typedef struct rlMonTxBallBreakRep
3602 {
3611  rlUInt16_t statusFlags;
3615  rlUInt16_t errorCode;
3620  rlInt16_t txReflCoefVal;
3624  rlUInt16_t reserved0;
3628  rlUInt32_t reserved1;
3634  rlUInt32_t timeStamp;
3636 
3643 /* Sub block ID: 0x1021, ICD API: AWR_MONITOR_TX_GAIN_PHASE_MISMATCH_REPORT_AE_SB */
3644 typedef struct rlMonTxGainPhaMisRep
3645 {
3655  rlUInt16_t statusFlags;
3659  rlUInt16_t errorCode;
3660 #ifndef MMWL_BIG_ENDIAN
3661 
3664  rlUInt8_t profIndex;
3670  rlUInt8_t noisePower00;
3676  rlUInt8_t noisePower01;
3682  rlUInt8_t noisePower02;
3683 #else
3684 
3689  rlUInt8_t noisePower00;
3693  rlUInt8_t profIndex;
3699  rlUInt8_t noisePower02;
3705  rlUInt8_t noisePower01;
3706 #endif
3707 
3719  rlInt16_t txGainVal[9U];
3733  rlUInt16_t txPhaVal[9U];
3734 #ifndef MMWL_BIG_ENDIAN
3735 
3740  rlUInt8_t noisePower10;
3746  rlUInt8_t noisePower11;
3752  rlUInt8_t noisePower12;
3758  rlUInt8_t noisePower20;
3764  rlUInt8_t noisePower21;
3770  rlUInt8_t noisePower22;
3774  rlUInt8_t reserved0;
3778  rlUInt8_t reserved1;
3779 #else
3780 
3785  rlUInt8_t noisePower11;
3791  rlUInt8_t noisePower10;
3797  rlUInt8_t noisePower20;
3803  rlUInt8_t noisePower12;
3809  rlUInt8_t noisePower22;
3815  rlUInt8_t noisePower21;
3819  rlUInt8_t reserved1;
3823  rlUInt8_t reserved0;
3824 #endif
3825 
3829  rlUInt32_t timeStamp;
3831 
3839 /* Sub block ID: 0x1022, ICD API: AWR_MONITOR_TX0_PHASE_SHIFTER_REPORT_AE_SB */
3840 /* Sub block ID: 0x1023, ICD API: AWR_MONITOR_TX1_PHASE_SHIFTER_REPORT_AE_SB */
3841 /* Sub block ID: 0x1024, ICD API: AWR_MONITOR_TX2_PHASE_SHIFTER_REPORT_AE_SB */
3842 typedef struct rlMonTxPhShiftRep
3843 {
3853  rlUInt16_t statusFlags;
3857  rlUInt16_t errorCode;
3858 #ifndef MMWL_BIG_ENDIAN
3859 
3862  rlUInt8_t profIndex;
3866  rlUInt8_t reserved0;
3867 #else
3868 
3871  rlUInt8_t reserved0;
3875  rlUInt8_t profIndex;
3876 #endif
3877 
3880  rlUInt16_t reserved1;
3886  rlUInt16_t phaseShifterMonVal1;
3892  rlUInt16_t phaseShifterMonVal2;
3898  rlUInt16_t phaseShifterMonVal3;
3904  rlUInt16_t phaseShifterMonVal4;
3910  rlInt16_t txPsAmplitudeVal1;
3916  rlInt16_t txPsAmplitudeVal2;
3922  rlInt16_t txPsAmplitudeVal3;
3928  rlInt16_t txPsAmplitudeVal4;
3929 #ifndef MMWL_BIG_ENDIAN
3930 
3935  rlInt8_t txPsNoiseVal1;
3941  rlInt8_t txPsNoiseVal2;
3947  rlInt8_t txPsNoiseVal3;
3953  rlInt8_t txPsNoiseVal4;
3954 #else
3955 
3960  rlInt8_t txPsNoiseVal2;
3966  rlInt8_t txPsNoiseVal1;
3972  rlInt8_t txPsNoiseVal4;
3978  rlInt8_t txPsNoiseVal3;
3979 #endif
3980 
3985  rlUInt32_t timeStamp;
3989  rlUInt32_t reserved2;
3993  rlUInt32_t reserved3;
3995 
4002 /* Sub block ID: 0x1025, ICD API: AWR_MONITOR_SYNTHESIZER_FREQUENCY_REPORT_AE_SB */
4003 typedef struct rlMonSynthFreqRep
4004 {
4013  rlUInt16_t statusFlags;
4017  rlUInt16_t errorCode;
4018 #ifndef MMWL_BIG_ENDIAN
4019 
4022  rlUInt8_t profIndex;
4026  rlUInt8_t reserved0;
4027 #else
4028 
4031  rlUInt8_t reserved0;
4035  rlUInt8_t profIndex;
4036 #endif
4037 
4040  rlUInt16_t reserved1;
4048  rlInt32_t maxFreqErVal;
4058  rlUInt32_t freqFailCnt;
4062  rlUInt32_t reserved2;
4066  rlUInt32_t reserved3;
4072  rlUInt32_t timeStamp;
4074 
4081 /* Sub block ID: 0x1026, ICD API: AWR_MONITOR_EXTERNAL_ANALOG_SIGNALS_REPORT_AE_SB */
4082 typedef struct rlMonExtAnaSigRep
4083 {
4097  rlUInt16_t statusFlags;
4101  rlUInt16_t errorCode;
4113  rlInt16_t extAnaSigVal[6U];
4117  rlUInt32_t reserved;
4123  rlUInt32_t timeStamp;
4125 
4132 /* Sub block ID: 0x1027, ICD API: AWR_MONITOR_TX0_INTERNAL_ANALOG_SIGNALS_REPORT_AE_SB */
4133 /* Sub block ID: 0x1028, ICD API: AWR_MONITOR_TX1_INTERNAL_ANALOG_SIGNALS_REPORT_AE_SB */
4134 /* Sub block ID: 0x1029, ICD API: AWR_MONITOR_TX2_INTERNAL_ANALOG_SIGNALS_REPORT_AE_SB */
4135 typedef struct rlMonTxIntAnaSigRep
4136 {
4146  rlUInt16_t statusFlags;
4150  rlUInt16_t errorCode;
4151 #ifndef MMWL_BIG_ENDIAN
4152 
4155  rlUInt8_t profIndex;
4159  rlUInt8_t reserved0;
4164  rlUInt8_t phShiftDacIdeltaMin;
4169  rlUInt8_t phShiftDacQdeltaMin;
4170 #else
4171 
4174  rlUInt8_t reserved0;
4178  rlUInt8_t profIndex;
4183  rlUInt8_t phShiftDacQdeltaMin;
4188  rlUInt8_t phShiftDacIdeltaMin;
4189 #endif
4190 
4195  rlUInt32_t timeStamp;
4197 
4204 /* Sub block ID: 0x102A, ICD API: AWR_MONITOR_RX_INTERNAL_ANALOG_SIGNALS_REPORT_AE_SB */
4205 typedef struct rlMonRxIntAnaSigRep
4206 {
4222  rlUInt16_t statusFlags;
4226  rlUInt16_t errorCode;
4227 #ifndef MMWL_BIG_ENDIAN
4228 
4231  rlUInt8_t profIndex;
4235  rlUInt8_t reserved0;
4236 #else
4237 
4240  rlUInt8_t reserved0;
4244  rlUInt8_t profIndex;
4245 #endif
4246 
4249  rlUInt16_t reserved1;
4255  rlUInt32_t timeStamp;
4257 
4265 /* Sub block ID: 0x102B, ICD API: AWR_MONITOR_PMCLKLO_INTERNAL_ANALOG_SIGNALS_REPORT_AE_SB */
4266 typedef struct rlMonPmclkloIntAnaSigRep
4267 {
4280  rlUInt16_t statusFlags;
4284  rlUInt16_t errorCode;
4285 #ifndef MMWL_BIG_ENDIAN
4286 
4289  rlUInt8_t profIndex;
4302  rlInt8_t sync20GPower;
4303 #else
4304 
4316  rlInt8_t sync20GPower;
4320  rlUInt8_t profIndex;
4321 #endif
4322 
4325  rlUInt16_t reserved;
4331  rlUInt32_t timeStamp;
4333 
4341 /* Sub block ID: 0x102C, ICD API: AWR_MONITOR_GPADC_INTERNAL_ANALOG_SIGNALS_REPORT_AE_SB */
4342 typedef struct rlMonGpadcIntAnaSigRep
4343 {
4353  rlUInt16_t statusFlags;
4357  rlUInt16_t errorCode;
4363  rlInt16_t gpadcRef1Val;
4369  rlUInt16_t gpadcRef2Val;
4373  rlUInt32_t reserved;
4379  rlUInt32_t timeStamp;
4381 
4388 /* Sub block ID: 0x102D, ICD API: AWR_MONITOR_PLL_CONTROL_VOLTAGE_REPORT_AE_SB */
4389 typedef struct rlMonPllConVoltRep
4390 {
4405  rlUInt16_t statusFlags;
4409  rlUInt16_t errorCode;
4430  rlInt16_t pllContVoltVal[8U];
4434  rlUInt32_t reserved;
4440  rlUInt32_t timeStamp;
4442 
4449 /* Sub block ID: 0x102E, ICD API: AWR_MONITOR_DUAL_CLOCK_COMP_REPORT_AE_SB */
4450 typedef struct rlMonDccClkFreqRep
4451 {
4464  rlUInt16_t statusFlags;
4468  rlUInt16_t errorCode;
4482  rlUInt16_t freqMeasVal[8U];
4486  rlUInt32_t reserved;
4492  rlUInt32_t timeStamp;
4494 
4502 /* Sub block ID: 0x1031, ICD API: AWR_MONITOR_RX_MIXER_IN_POWER_REPORT_AE_SB */
4503 typedef struct rlMonRxMixrInPwrRep
4504 {
4516  rlUInt16_t statusFlags;
4520  rlUInt16_t errorCode;
4521 
4522 #ifndef MMWL_BIG_ENDIAN
4526  rlUInt8_t profIndex;
4530  rlUInt8_t reserved0;
4531 #else
4532 
4535  rlUInt8_t reserved0;
4539  rlUInt8_t profIndex;
4540 #endif
4541 
4544  rlUInt16_t reserved1;
4557  rlUInt32_t rxMixInVolt;
4561  rlUInt32_t reserved2;
4566  rlUInt32_t timeStamp;
4568 
4576 /* Sub block ID: 0x1033, ICD API: AWR_MONITOR_SYNTHESIZER_FREQUENCY_NONLIVE_REPORT_AE_SB */
4577 typedef struct rlMonSynthFreqNonLiveRep
4578 {
4588  rlUInt16_t statusFlags;
4592  rlUInt16_t errorCode;
4593 
4594 #ifndef MMWL_BIG_ENDIAN
4598  rlUInt8_t profIndex0;
4602  rlUInt8_t reserved0;
4603 #else
4604 
4607  rlUInt8_t reserved0;
4611  rlUInt8_t profIndex0;
4612 #endif
4613 
4616  rlUInt16_t reserved1;
4624  rlInt32_t maxFreqErVal0;
4634  rlUInt32_t freqFailCnt0;
4640  rlUInt32_t maxFreqFailTime0;
4644  rlUInt32_t reserved2;
4645 
4646 #ifndef MMWL_BIG_ENDIAN
4650  rlUInt8_t profIndex1;
4654  rlUInt8_t reserved3;
4655 #else
4656 
4659  rlUInt8_t reserved3;
4663  rlUInt8_t profIndex1;
4664 #endif
4665 
4668  rlUInt16_t reserved4;
4676  rlInt32_t maxFreqErVal1;
4686  rlUInt32_t freqFailCnt1;
4692  rlUInt32_t maxFreqFailTime1;
4696  rlUInt32_t reserved5;
4697 
4702  rlUInt32_t timeStamp;
4704 
4714 typedef struct rlMmwlErrorStatus
4715 {
4716  rlInt32_t errorVal;
4718 
4719 #include <ti/control/mmwavelink/include/rl_device.h>
4720 #include <ti/control/mmwavelink/include/rl_sensor.h>
4721 #include <ti/control/mmwavelink/include/rl_monitoring.h>
4722 #include <ti/control/mmwavelink/include/rl_protocol.h>
4723 #include <ti/control/mmwavelink/include/rl_messages.h>
4724 
4725 
4726 /******************************************************************************
4727  * FUNCTION PROTOTYPES
4728  ******************************************************************************
4729  */
4730 
4731 #ifdef __cplusplus
4732 }
4733 #endif
4734 
4735 #endif
4736 /*
4737  * END OF MMWAVELINK_H
4738  */
4739 
This is the Monitoring report which RadarSS sends to the host, containing information about the relat...
Definition: mmwavelink.h:4453
mmWaveLink RF Run time calibration report for event RL_RF_AE_RUN_TIME_CALIB_REPORT_SB
Definition: mmwavelink.h:2216
This async event is sent periodically to indicate the status of periodic digital monitoring tests....
Definition: mmwavelink.h:2947
mmWaveLink client callback structure
Definition: mmwavelink.h:1523
This is the Monitoring report which RadarSS sends to the host, containing the measured RX noise figur...
Definition: mmwavelink.h:3250
mmWaveLink RF Init Complete data structure for event RL_RF_AE_INITCALIBSTATUS_SB
Definition: mmwavelink.h:2162
Sensors GPADC measurement data for event RL_RF_AE_GPADC_MEAS_DATA_SB.
Definition: mmwavelink.h:2783
Structure to hold the BSS ESM Fault data strucutre for event RL_RF_AE_ESMFAULT_SB.
Definition: mmwavelink.h:2090
mmWaveLink firmware version structure
Definition: mmwavelink.h:2528
Structure to hold the test status report of the latent fault tests data strucutre for event RL_DEV_AE...
Definition: mmwavelink.h:1980
mmWaveLink Report for event RL_RF_AE_MONITOR_TYPE_TRIGGER_DONE_SB. The triggered monitor types are do...
Definition: mmwavelink.h:2278
Communication interface(SPI, MailBox, UART etc) callback functions.
Definition: mmwavelink.h:1074
mmWaveLink CRC callback function
Definition: mmwavelink.h:1359
Calibration monitoring timing error data for event RL_RF_AE_MON_TIMING_FAIL_REPORT_SB.
Definition: mmwavelink.h:2857
This is the Monitoring report which RadarSS sends to the host, containing the measured temperature ne...
Definition: mmwavelink.h:2974
mmWaveLink Init Complete data structure for event RL_DEV_AE_MSSPOWERUPDONE_SB
Definition: mmwavelink.h:1589
This is the Monitoring report which RadarSS sends to the host, containing information about Internal ...
Definition: mmwavelink.h:4269
This API is a Monitoring report which RadarSS sends to the host, containing the measured RX gain and ...
Definition: mmwavelink.h:3031
This is an error status report internally generated from mmWaveLink when it finds any issue with the ...
Definition: mmwavelink.h:4717
This is the Monitoring report which RadarSS sends to the host, containing the measured TX reflection ...
Definition: mmwavelink.h:3604
This is the Monitoring report which RadarSS sends to the host, containing information about the measu...
Definition: mmwavelink.h:4345
This is the Monitoring report which the AWR device sends to the host, containing the measured TX phas...
Definition: mmwavelink.h:3845
OS semaphore callback functions.
Definition: mmwavelink.h:1210
mmWaveLink Device Control, Interrupt callback functions
Definition: mmwavelink.h:1384
This is the Monitoring report which RadarSS sends to the host, containing information related to meas...
Definition: mmwavelink.h:4006
mmWaveLink Timer callback functions
Definition: mmwavelink.h:1339
mmWaveLink debug callback structure
Definition: mmwavelink.h:1498
Analog fault strucure for event RL_RF_AE_ANALOG_FAULT_SB.
Definition: mmwavelink.h:2803
This is the Monitoring report which RadarSS sends to the host, containing the measured Tx gain and ph...
Definition: mmwavelink.h:3647
API APLL closed loop cal Status Get Sub block structure.
Definition: mmwavelink.h:2327
This is the Monitoring report which RadarSS sends to the host, containing information about Internal ...
Definition: mmwavelink.h:4138
This is the Monitoring report which RadarSS sends to the host, containing information about Internal ...
Definition: mmwavelink.h:4208
Structure to hold data strucutre for RF-error status send by MSS for event RL_DEV_AE_MSS_RF_ERROR_STA...
Definition: mmwavelink.h:2064
Latent fault digital monitoring status data for event RL_RF_AE_DIG_LATENTFAULT_REPORT_AE_SB.
Definition: mmwavelink.h:2880
This is the Monitoring report which RadarSS sends to the host, containing the measured PLL control vo...
Definition: mmwavelink.h:4392
GPADC measurement data for sensors.
Definition: mmwavelink.h:2763
This is a Non live Monitoring report which device sends to the host, containing information related t...
Definition: mmwavelink.h:4580
This is the Monitoring report which the xWR device sends to the host, containing the measured RX mixe...
Definition: mmwavelink.h:4506
Structure to hold the MSS Boot error status data strucutre when booted over SPI for event RL_DEV_AE_M...
Definition: mmwavelink.h:1858
Structure to hold the MSS ESM Fault data structure for event RL_DEV_AE_MSS_ESMFAULT_SB.
Definition: mmwavelink.h:1767
The report header includes common information across all enabled monitors like current FTTI number an...
Definition: mmwavelink.h:2921
mmwavelink software version structure
Definition: mmwavelink.h:2670
mmWaveLink callback functions for Command parser
Definition: mmwavelink.h:1347
OS mutex callback functions.
Definition: mmwavelink.h:1137
This is the Monitoring report which RadarSS sends to the host, containing the external signal voltage...
Definition: mmwavelink.h:4085
Structure to hold the MSS/radarSS CPU Fault data strucutre for event RL_DEV_AE_MSS_CPUFAULT_SB and RL...
Definition: mmwavelink.h:2358
mmwavelink version structure
Definition: mmwavelink.h:2744
Structure to hold data strucutre for test status of the periodic tests for event RL_DEV_AE_MSS_PERIOD...
Definition: mmwavelink.h:2042
mmWaveLink RF Start Complete data structure for event RL_DEV_AE_RFPOWERUPDONE_SB
Definition: mmwavelink.h:1711
mmWaveLink Asynchronous event callback function
Definition: mmwavelink.h:1315
This is the Monitoring report which RadarSS sends to the host, containing the measured RX IF filter a...
Definition: mmwavelink.h:3329
OS message queue/Spawn callback functions.
Definition: mmwavelink.h:1270
This is the Monitoring report which RadarSS sends to the host, containing the measured TX power value...
Definition: mmwavelink.h:3530
OS services callback functions.
Definition: mmwavelink.h:1296

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