rl_monitoring.h
1 /****************************************************************************************
2  * FileName : rl_monitoring.h
3  *
4  * Description : This file defines the functions required for Monitoring.
5  *
6  ****************************************************************************************
7  * (C) Copyright 2014, Texas Instruments Incorporated. - TI web address www.ti.com
8  *---------------------------------------------------------------------------------------
9  *
10  * Redistribution and use in source and binary forms, with or without modification,
11  * are permitted provided that the following conditions are met:
12  *
13  * Redistributions of source code must retain the above copyright notice,
14  * this list of conditions and the following disclaimer.
15  *
16  * Redistributions in binary form must reproduce the above copyright notice,
17  * this list of conditions and the following disclaimer in the documentation
18  * and/or other materials provided with the distribution.
19  *
20  * Neither the name of Texas Instruments Incorporated nor the names of its
21  * contributors may be used to endorse or promote products derived from this
22  * software without specific prior written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
28  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34  * POSSIBILITY OF SUCH DAMAGE.
35  */
36 
37 /****************************************************************************************
38  * FILE INCLUSION PROTECTION
39  ****************************************************************************************
40  */
41 #ifndef RL_MONITORING_H
42 #define RL_MONITORING_H
43 
44 /******************************************************************************
45  * INCLUDE FILES
46  ******************************************************************************
47  */
48 
49 #ifdef __cplusplus
50 extern "C" {
51 #endif
52 
56 #define RL_MON_RF_FREQ_CNT (3U)
57 
61 #define RL_NUM_MON_SLICES_MAX (127U)
62 
63 
64 /******************************************************************************
65  * GLOBAL VARIABLES/DATA-TYPES DEFINITIONS
66  ******************************************************************************
67  */
68 
72 typedef struct rlMonDigEnables
73 {
104  rlUInt32_t enMask;
105 #ifndef MMWL_BIG_ENDIAN
106 
112  rlUInt8_t testMode;
116  rlUInt8_t reserved0;
117 #else
118 
121  rlUInt8_t reserved0;
131  rlUInt8_t testMode;
132 #endif
133 
136  rlUInt16_t reserved1;
140  rlUInt32_t reserved2;
142 
146 typedef struct rlDigMonPeriodicConf
147 {
148 #ifndef MMWL_BIG_ENDIAN
149 
155  rlUInt8_t reportMode;
159  rlUInt8_t reserved0;
160 #else
161 
164  rlUInt8_t reserved0;
171  rlUInt8_t reportMode;
172 #endif
173 
176  rlUInt16_t reserved1;
185  rlUInt32_t periodicEnableMask;
189  rlUInt32_t reserved2;
191 
195 typedef struct rlMonAnaEnables
196 {
230  rlUInt32_t enMask;
246  rlUInt32_t ldoVmonScEn;
248 
252 typedef struct rlTempMonConf
253 {
254 #ifndef MMWL_BIG_ENDIAN
255 
261  rlUInt8_t reportMode;
265  rlUInt8_t reserved0;
266 #else
267 
270  rlUInt8_t reserved0;
277  rlUInt8_t reportMode;
278 #endif
279 
287  rlInt16_t anaTempThreshMin;
296  rlInt16_t anaTempThreshMax;
306  rlInt16_t digTempThreshMin;
316  rlInt16_t digTempThreshMax;
327  rlUInt16_t tempDiffThresh;
331  rlUInt32_t reserved1;
335  rlUInt32_t reserved2;
337 
341 typedef struct rlRxGainPhaseMonConf
342 {
343 #ifndef MMWL_BIG_ENDIAN
344 
347  rlUInt8_t profileIndx;
363  rlUInt8_t rfFreqBitMask;
373  rlUInt8_t reportMode;
379  rlUInt8_t txSel;
380 #else
381 
396  rlUInt8_t rfFreqBitMask;
400  rlUInt8_t profileIndx;
406  rlUInt8_t txSel;
416  rlUInt8_t reportMode;
417 #endif
418 
428  rlUInt16_t rxGainAbsThresh;
479  rlInt16_t rxGainMismatchOffsetVal[RL_RX_CNT][RL_MON_RF_FREQ_CNT];
493  rlUInt16_t rxGainPhaseMismatchOffsetVal[RL_RX_CNT][RL_MON_RF_FREQ_CNT];
497  rlUInt32_t reserved0;
501  rlUInt32_t reserved1;
503 
507 typedef struct rlRxNoiseMonConf
508 {
509 #ifndef MMWL_BIG_ENDIAN
510 
513  rlUInt8_t profileIndx;
529  rlUInt8_t rfFreqBitMask;
530 #else
531 
546  rlUInt8_t rfFreqBitMask;
550  rlUInt8_t profileIndx;
551 #endif
552 
555  rlUInt16_t reserved0;
556 #ifndef MMWL_BIG_ENDIAN
557 
563  rlUInt8_t reportMode;
567  rlUInt8_t reserved1;
568 #else
569 
572  rlUInt8_t reserved1;
579  rlUInt8_t reportMode;
580 #endif
581 
589  rlUInt16_t noiseThresh;
593  rlUInt32_t reserved2;
595 
599 typedef struct rlRxIfStageMonConf
600 {
601 #ifndef MMWL_BIG_ENDIAN
602 
605  rlUInt8_t profileIndx;
612  rlUInt8_t reportMode;
613 #else
614 
620  rlUInt8_t reportMode;
624  rlUInt8_t profileIndx;
625 #endif
626 
629  rlUInt16_t reserved0;
633  rlUInt16_t reserved1;
642  rlUInt16_t hpfCutoffErrThresh;
643 #ifndef MMWL_BIG_ENDIAN
644 
665 #else
666 
676  rlUInt8_t lpfCutoffStopBandAttenThresh;
686  rlUInt8_t lpfCutoffBandEdgeDroopThresh;
687 #endif
688 
697  rlUInt16_t ifaGainErrThresh;
701  rlUInt32_t reserved2;
703 
707 typedef struct rlTxPowMonConf
708 {
709 #ifndef MMWL_BIG_ENDIAN
710 
713  rlUInt8_t profileIndx;
730  rlUInt8_t rfFreqBitMask;
731 #else
732 
748  rlUInt8_t rfFreqBitMask;
752  rlUInt8_t profileIndx;
753 #endif
754 
757  rlUInt16_t reserved0;
758 #ifndef MMWL_BIG_ENDIAN
759 
764  rlUInt8_t reportMode;
768  rlUInt8_t reserved1;
769 #else
770 
773  rlUInt8_t reserved1;
779  rlUInt8_t reportMode;
780 #endif
781 
789  rlUInt16_t txPowAbsErrThresh;
804  rlUInt16_t reserved2;
808  rlUInt32_t reserved3;
810 
811 
815 typedef struct rlAllTxPowMonConf
816 {
830 
834 typedef struct rlTxBallbreakMonConf
835 {
836 #ifndef MMWL_BIG_ENDIAN
837 
843  rlUInt8_t reportMode;
847  rlUInt8_t reserved0;
848 #else
849 
852  rlUInt8_t reserved0;
859  rlUInt8_t reportMode;
860 #endif
861 
868  rlInt16_t txReflCoeffMagThresh;
872  rlUInt32_t reserved1;
876  rlUInt32_t reserved2;
878 
882 typedef struct rlAllTxBallBreakMonCfg
883 {
897 
901 typedef struct rlTxGainPhaseMismatchMonConf
902 {
903 #ifndef MMWL_BIG_ENDIAN
904 
910  rlUInt8_t profileIndx;
927  rlUInt8_t rfFreqBitMask;
937  rlUInt8_t txEn;
948  rlUInt8_t rxEn;
955  rlUInt8_t reportMode;
974  rlInt8_t monChirpSlope;
975 #else
976 
992  rlUInt8_t rfFreqBitMask;
999  rlUInt8_t profileIndx;
1010  rlUInt8_t rxEn;
1020  rlUInt8_t txEn;
1039  rlInt8_t monChirpSlope;
1046  rlUInt8_t reportMode;
1047 #endif
1048 
1082  rlUInt16_t txGainMismatchOffsetVal[RL_TX_CNT][RL_MON_RF_FREQ_CNT];
1096  rlUInt16_t txPhaseMismatchOffsetVal[RL_TX_CNT][RL_MON_RF_FREQ_CNT];
1100  rlUInt16_t reserved1;
1104  rlUInt32_t reserved2;
1106 
1110 typedef struct rlSynthFreqMonConf
1111 {
1112 #ifndef MMWL_BIG_ENDIAN
1113 
1116  rlUInt8_t profileIndx;
1123  rlUInt8_t reportMode;
1124 #else
1125 
1131  rlUInt8_t reportMode;
1135  rlUInt8_t profileIndx;
1136 #endif
1137 
1146  rlUInt16_t freqErrThresh;
1147 #ifndef MMWL_BIG_ENDIAN
1148 
1155  rlInt8_t monStartTime;
1172  rlUInt8_t monitorMode;
1182  rlUInt8_t vcoMonEn;
1186  rlUInt8_t reserved1;
1187 #else
1188 
1204  rlUInt8_t monitorMode;
1212  rlInt8_t monStartTime;
1216  rlUInt8_t reserved1;
1226  rlUInt8_t vcoMonEn;
1227 #endif
1228 
1231  rlUInt32_t reserved2;
1233 
1237 typedef struct rlExtAnaSignalsMonConf
1238 {
1239 #ifndef MMWL_BIG_ENDIAN
1240 
1246  rlUInt8_t reportMode;
1250  rlUInt8_t reserved0;
1265  rlUInt8_t signalInpEnables;
1300  rlUInt8_t signalSettlingTime[6U];
1322  rlUInt8_t signalThresh[12U];
1323 #else
1324 
1327  rlUInt8_t reserved0;
1334  rlUInt8_t reportMode;
1349  rlUInt8_t signalBuffEnables;
1364  rlUInt8_t signalInpEnables;
1384  rlUInt8_t signalSettlingTime[6U];
1406  rlUInt8_t signalThresh[12U];
1407 #endif
1408 
1411  rlUInt16_t reserved1;
1415  rlUInt32_t reserved2;
1419  rlUInt32_t reserved3;
1421 
1425 typedef struct rlTxIntAnaSignalsMonConf
1426 {
1427 #ifndef MMWL_BIG_ENDIAN
1428 
1433  rlUInt8_t profileIndx;
1440  rlUInt8_t reportMode;
1441 #else
1442 
1448  rlUInt8_t reportMode;
1454  rlUInt8_t profileIndx;
1455 #endif
1456 
1466  rlUInt32_t reserved1;
1468 
1469 
1473 typedef struct rlAllTxIntAnaSignalsMonConf
1474 {
1488 
1489 typedef struct rlRxIntAnaSignalsMonConf
1490 {
1491 #ifndef MMWL_BIG_ENDIAN
1492 
1497  rlUInt8_t profileIndx;
1504  rlUInt8_t reportMode;
1505 #else
1506 
1512  rlUInt8_t reportMode;
1518  rlUInt8_t profileIndx;
1519 #endif
1520 
1523  rlUInt16_t reserved0;
1527  rlUInt32_t reserved1;
1528 } rlRxIntAnaSignalsMonConf_t;
1529 
1533 typedef struct rlPmClkLoIntAnaSignalsMonConf
1534 {
1535 #ifndef MMWL_BIG_ENDIAN
1536 
1546  rlUInt8_t profileIndx;
1553  rlUInt8_t reportMode;
1554 
1567  rlUInt8_t sync20GSigSel;
1568 
1575 
1582 
1586  rlUInt8_t reserved0;
1587 #else
1588 
1594  rlUInt8_t reportMode;
1605  rlUInt8_t profileIndx;
1606 
1612  rlInt8_t sync20GMinThresh;
1613 
1626  rlUInt8_t sync20GSigSel;
1627 
1631  rlUInt8_t reserved0;
1632 
1638  rlInt8_t sync20GMaxThresh;
1639 #endif
1640 
1643  rlUInt16_t reserved1;
1645 
1649 typedef struct rlGpadcIntAnaSignalsMonConf
1650 {
1651 #ifndef MMWL_BIG_ENDIAN
1652 
1658  rlUInt8_t reportMode;
1662  rlUInt8_t reserved0;
1663 #else
1664 
1667  rlUInt8_t reserved0;
1674  rlUInt8_t reportMode;
1675 #endif
1676 
1679  rlUInt16_t reserved1;
1683  rlUInt32_t reserved2;
1685 
1689 typedef struct rlPllContrlVoltMonConf
1690 {
1691 #ifndef MMWL_BIG_ENDIAN
1692 
1698  rlUInt8_t reportMode;
1702  rlUInt8_t reserved0;
1703 #else
1704 
1707  rlUInt8_t reserved0;
1714  rlUInt8_t reportMode;
1715 #endif
1716 
1738  rlUInt16_t signalEnables;
1742  rlUInt32_t reserved1;
1744 
1748 typedef struct rlDualClkCompMonConf
1749 {
1750 #ifndef MMWL_BIG_ENDIAN
1751 
1757  rlUInt8_t reportMode;
1761  rlUInt8_t reserved0;
1762 #else
1763 
1766  rlUInt8_t reserved0;
1773  rlUInt8_t reportMode;
1774 #endif
1775 
1790  rlUInt16_t dccPairEnables;
1794  rlUInt32_t reserved1;
1796 
1800 typedef struct rlRxSatMonConf
1801 {
1802 #ifndef MMWL_BIG_ENDIAN
1803 
1806  rlUInt8_t profileIndx;
1811  rlUInt8_t satMonSel;
1812 #else
1813 
1817  rlUInt8_t satMonSel;
1821  rlUInt8_t profileIndx;
1822 #endif
1823 
1826  rlUInt16_t reserved0;
1859  rlUInt16_t numSlices;
1860 #ifndef MMWL_BIG_ENDIAN
1861 
1870  rlUInt8_t rxChannelMask;
1874  rlUInt8_t reserved1;
1875 #else
1876 
1879  rlUInt8_t reserved1;
1889  rlUInt8_t rxChannelMask;
1890 #endif
1891 
1894  rlUInt16_t reserved2;
1898  rlUInt32_t reserved3;
1902  rlUInt32_t reserved4;
1904 
1908 typedef struct rlSigImgMonConf
1909 {
1910 #ifndef MMWL_BIG_ENDIAN
1911 
1914  rlUInt8_t profileIndx;
1918  rlUInt8_t numSlices;
1919 #else
1920 
1923  rlUInt8_t numSlices;
1927  rlUInt8_t profileIndx;
1928 #endif
1929 
1949  rlUInt32_t reserved0;
1953  rlUInt32_t reserved1;
1955 
1959 typedef struct rlRxMixInPwrMonConf
1960 {
1961 #ifndef MMWL_BIG_ENDIAN
1962 
1967  rlUInt8_t profileIndx;
1975  rlUInt8_t reportMode;
1986  rlUInt8_t txEnable;
1990  rlUInt8_t reserved0;
1991 #else
1992 
1999  rlUInt8_t reportMode;
2005  rlUInt8_t profileIndx;
2009  rlUInt8_t reserved0;
2020  rlUInt8_t txEnable;
2021 #endif
2022 
2034  rlUInt16_t thresholds;
2038  rlUInt16_t reserved1;
2042  rlUInt32_t reserved2;
2044 
2048 typedef struct rlRfSigImgPowerCqData
2049 {
2053  rlUInt16_t numSlices;
2079  rlUInt16_t sigImgPowerCqVal[RL_NUM_MON_SLICES_MAX];
2081 
2085 typedef struct rlRfRxSaturationCqData
2086 {
2090  rlUInt8_t numSlices;
2118  rlUInt8_t satCqVal[RL_NUM_MON_SLICES_MAX];
2120 
2121 typedef struct rlAnaFaultInj
2122 {
2123 #ifndef MMWL_BIG_ENDIAN
2124 
2127  rlUInt8_t reserved0;
2142  rlUInt8_t rxGainDrop;
2156  rlUInt8_t rxPhInv;
2171  rlUInt8_t rxHighNoise;
2189  rlUInt8_t rxIfStagesFault;
2202  rlUInt8_t rxLoAmpFault;
2216  rlUInt8_t txLoAmpFault;
2230  rlUInt8_t txGainDrop;
2251  rlUInt8_t txPhInv;
2270  rlUInt8_t synthFault;
2284  rlUInt8_t supplyLdoFault;
2295  rlUInt8_t miscFault;
2309  rlUInt8_t miscThreshFault;
2313  rlUInt8_t reserved1;
2314 #else
2315 
2329  rlUInt8_t rxGainDrop;
2333  rlUInt8_t reserved0;
2348  rlUInt8_t rxHighNoise;
2362  rlUInt8_t rxPhInv;
2374  rlUInt8_t rxLoAmpFault;
2392  rlUInt8_t rxIfStagesFault;
2406  rlUInt8_t txGainDrop;
2419  rlUInt8_t txLoAmpFault;
2438  rlUInt8_t synthFault;
2459  rlUInt8_t txPhInv;
2470  rlUInt8_t miscFault;
2484  rlUInt8_t supplyLdoFault;
2488  rlUInt8_t reserved1;
2502  rlUInt8_t miscThreshFault;
2503 #endif
2504 
2507  rlUInt16_t reserved2;
2511  rlUInt16_t reserved3;
2515  rlUInt16_t reserved4;
2516 } rlAnaFaultInj_t;
2517 
2521 typedef struct rlTxPhShiftMonConf
2522 {
2523 #ifndef MMWL_BIG_ENDIAN
2524 
2527  rlUInt8_t profileIndx;
2534  rlUInt8_t reportMode;
2535 #else
2536 
2542  rlUInt8_t reportMode;
2546  rlUInt8_t profileIndx;
2547 #endif
2548 
2551  rlUInt16_t reserved0;
2552 #ifndef MMWL_BIG_ENDIAN
2553 
2563  rlUInt8_t phShifterMonCfg;
2575  rlUInt8_t rxEn;
2594  rlInt8_t monChirpSlope;
2598  rlUInt8_t reserved1;
2609  rlUInt8_t phShifterIncVal1;
2620  rlUInt8_t phShifterIncVal2;
2631  rlUInt8_t phShifterIncVal3;
2642  rlUInt8_t phShifterIncVal4;
2650  rlUInt8_t phShifterMon1;
2658  rlUInt8_t phShifterMon2;
2666  rlUInt8_t phShifterMon3;
2674  rlUInt8_t phShifterMon4;
2675 #else
2676 
2687  rlUInt8_t rxEn;
2698  rlUInt8_t phShifterMonCfg;
2702  rlUInt8_t reserved1;
2721  rlInt8_t monChirpSlope;
2732  rlUInt8_t phShifterIncVal2;
2743  rlUInt8_t phShifterIncVal1;
2754  rlUInt8_t phShifterIncVal4;
2765  rlUInt8_t phShifterIncVal3;
2773  rlUInt8_t phShifterMon2;
2781  rlUInt8_t phShifterMon1;
2789  rlUInt8_t phShifterMon4;
2797  rlUInt8_t phShifterMon3;
2798 #endif
2799 
2818  rlUInt16_t txAmplErrorThresh;
2822  rlUInt32_t reserved2;
2826  rlUInt32_t reserved3;
2828 
2832 typedef struct rlAllTxPhShiftMonConf
2833 {
2847 
2938 /******************************************************************************
2939  * FUNCTION DECLARATIONS
2940  ******************************************************************************
2941  */
2942 
2943 /* Digital Monitoring Configuration */
2944 MMWL_EXPORT rlReturnVal_t rlRfDigMonEnableConfig(rlUInt8_t deviceMap,
2945  rlMonDigEnables_t* data);
2946 
2947 /* Digital Monitoring Periodic Configuration */
2948 MMWL_EXPORT rlReturnVal_t rlRfDigMonPeriodicConfig(rlUInt8_t deviceMap,
2949  rlDigMonPeriodicConf_t* data);
2950 /* Analog Monitoring Configuration */
2951 MMWL_EXPORT rlReturnVal_t rlRfAnaMonConfig(rlUInt8_t deviceMap,
2952  rlMonAnaEnables_t* data);
2953 /* TemperatureSsensor Monitoring Configuration */
2954 MMWL_EXPORT rlReturnVal_t rlRfTempMonConfig(rlUInt8_t deviceMap, rlTempMonConf_t* data);
2955 /* RX Gain and Phase Monitoring Configuration */
2956 MMWL_EXPORT rlReturnVal_t rlRfRxGainPhMonConfig(rlUInt8_t deviceMap,
2957  rlRxGainPhaseMonConf_t* data);
2958 /* RX Noise Monitoring Configuration */
2959 MMWL_EXPORT rlReturnVal_t rlRfRxNoiseMonConfig(rlUInt8_t deviceMap,
2960  rlRxNoiseMonConf_t* data);
2961 /* RX IF Stage Monitoring Configuration */
2962 MMWL_EXPORT rlReturnVal_t rlRfRxIfStageMonConfig(rlUInt8_t deviceMap,
2963  rlRxIfStageMonConf_t* data);
2964 /* TX Power Monitoring Configuration */
2965 MMWL_EXPORT rlReturnVal_t rlRfTxPowrMonConfig(rlUInt8_t deviceMap,
2966  rlAllTxPowMonConf_t *data);
2967 /* TX Ballbreak Monitoring Configuration */
2968 MMWL_EXPORT rlReturnVal_t rlRfTxBallbreakMonConfig(rlUInt8_t deviceMap,
2969  rlAllTxBallBreakMonCfg_t* data);
2970 /* TX Gain Phase Mismatch Monitoring Configuration */
2971 MMWL_EXPORT rlReturnVal_t rlRfTxGainPhaseMismatchMonConfig(rlUInt8_t deviceMap,
2973 /* Synth Freq Monitoring Configuration */
2974 MMWL_EXPORT rlReturnVal_t rlRfSynthFreqMonConfig(rlUInt8_t deviceMap,
2975  rlSynthFreqMonConf_t* data);
2976 /* External Analog Signals Monitoring Configuration */
2977 MMWL_EXPORT rlReturnVal_t rlRfExtAnaSignalsMonConfig(rlUInt8_t deviceMap,
2978  rlExtAnaSignalsMonConf_t* data);
2979 /* TX Internal Analog Signals Monitoring Configuration */
2980 MMWL_EXPORT rlReturnVal_t rlRfTxIntAnaSignalsMonConfig(rlUInt8_t deviceMap,
2982 /* RX Internal Analog Signals Monitoring Configuration */
2983 MMWL_EXPORT rlReturnVal_t rlRfRxIntAnaSignalsMonConfig(rlUInt8_t deviceMap,
2984  rlRxIntAnaSignalsMonConf_t* data);
2985 /* PM, CLK, LO Internal Analog Signals Monitoring Configuration */
2986 MMWL_EXPORT rlReturnVal_t rlRfPmClkLoIntAnaSignalsMonConfig(rlUInt8_t deviceMap,
2988 /* GPADC Internal Analog Signals Monitoring Configuration */
2989 MMWL_EXPORT rlReturnVal_t rlRfGpadcIntAnaSignalsMonConfig(rlUInt8_t deviceMap,
2991 /* PLL Control Voltage Monitoring Configuration */
2992 MMWL_EXPORT rlReturnVal_t rlRfPllContrlVoltMonConfig(rlUInt8_t deviceMap,
2993  rlPllContrVoltMonConf_t* data);
2994 /* Dual Clock Comparator Monitoring Configuration */
2995 MMWL_EXPORT rlReturnVal_t rlRfDualClkCompMonConfig(rlUInt8_t deviceMap,
2996  rlDualClkCompMonConf_t* data);
2997 /* RX Saturation Monitoring Configuration */
2998 MMWL_EXPORT rlReturnVal_t rlRfRxIfSatMonConfig(rlUInt8_t deviceMap,
2999  rlRxSatMonConf_t* data);
3000 /* RX Signal Image band Monitoring Configuration */
3001 MMWL_EXPORT rlReturnVal_t rlRfRxSigImgMonConfig(rlUInt8_t deviceMap,
3002  rlSigImgMonConf_t* data);
3003 /* RX mixer input power monitoring.Configuration */
3004 MMWL_EXPORT rlReturnVal_t rlRfRxMixerInPwrConfig(rlUInt8_t deviceMap,
3005  rlRxMixInPwrMonConf_t* data);
3006 /* Analog fault injection Configuration */
3007 MMWL_EXPORT rlReturnVal_t rlRfAnaFaultInjConfig(rlUInt8_t deviceMap,
3008  rlAnaFaultInj_t* data);
3009 /* TX Phase shifter monitoring Configuration */
3010 MMWL_EXPORT rlReturnVal_t rlRfTxPhShiftMonConfig(rlUInt8_t deviceMap,
3011  rlAllTxPhShiftMonConf_t* data);
3012 
3018 #ifdef __cplusplus
3019 }
3020 #endif
3021 
3022 #endif
3023 /*
3024  * END OF RL_MONITORING_H FILE
3025  */
rlUInt32_t reserved2
Reserved for Future use.
rlInt8_t sync20GMinThresh
Minimum threshold for 20GHz monitoring 1 LSB = 1 dBm Valid Range: -63 to +63 dBm.
rlUInt16_t reserved0
Reserved for Future use.
rlUInt32_t reserved2
Reserved for Future use.
rlUInt16_t reserved0
Reserved for Future use.
rlUInt8_t reserved1
Reserved for Future use.
rlUInt16_t reserved1
Reserved for Future use.
rlUInt32_t reserved1
Reserved for Future use.
rlUInt8_t reportMode
Value Definition 0 Report is sent every monitoring period without threshold check 1 Report is sen...
rlUInt8_t phShifterIncVal1
Phase shifter monitoring increment value for phase1, the monitoring phase will be incremented by this...
rlUInt8_t testMode
Value Definition 0 Production mode. Latent faults are tested and any failures are reported 1 Char...
rlUInt8_t reportMode
Value Definition 0 Report is sent every monitoring period without threshold check 1 Report is sen...
rlUInt8_t reportMode
Value Definition 0 Report is sent every monitoring period without threshold check 1 Report is sen...
rlUInt32_t reserved2
Reserved for Future use.
rlUInt16_t reserved0
Reserved for Future use.
TX power monitoring configuration.
Internal signals for DCC based clock monitoring configuration.
rlUInt16_t timeSliceNumSamples
This field specifies the number of samples constituting each time slice. The minimum allowed value ...
rlUInt16_t numSlices
Number of (primary + secondary) slices to monitor Valid range: 1 to 127.
Signal and image band energy monitoring configuration.
rlUInt8_t reserved0
Reserved for Future use.
External analog signals monitoring configuration.
rlUInt8_t reportMode
Value Definition 0 Report is sent every monitoring period without threshold check 1 Report is sen...
rlUInt16_t signalEnables
This field indicates the sets of signals which are to be monitored. When each bit in this field is ...
rlUInt16_t primarySliceDuration
It specifies the duration of each (primary) time slice. 1 LSB = 0.16us. Valid range: 4 to floor(A...
rlInt16_t txGainMismatchThresh
The magnitude of difference between measured TX powers across the enabled channels at each enabled ...
RX saturation monitoring configuration.
rlUInt8_t reportMode
Indicates the desired reporting verbosity and threshold usage. Value = 0 Report is sent every monit...
MMWL_EXPORT rlReturnVal_t rlRfTxBallbreakMonConfig(rlUInt8_t deviceMap, rlAllTxBallBreakMonCfg_t *data)
Sets information related to TX ball break detection.
MMWL_EXPORT rlReturnVal_t rlRfAnaMonConfig(rlUInt8_t deviceMap, rlMonAnaEnables_t *data)
This function contains the consolidated configuration of all analog monitoring. The enabled monitorin...
rlUInt32_t enMask
Bit Analog monitoring control 0 TEMPERATURE_MONITOR_EN 1 RX_GAIN_PHASE_MONITOR_EN 2 RX_NOISE_MO...
rlUInt32_t reserved1
Reserved for Future use.
rlUInt32_t reserved3
Reserved for Future use.
rlTxPhShiftMonConf_t * tx2PhShiftMonCfg
Tx-2 Phase shifter monitoring config.
rlUInt8_t reserved0
Reserved for Future use.
rlUInt32_t reserved2
Reserved for Future use.
rlUInt32_t ldoVmonScEn
LDO short circuit monitoring enable. There are no reports for these monitors. If there is any fault...
rlUInt16_t reserved1
Reserved for Future use.
rlUInt8_t numSlices
Number of (primary + secondary) slices to monitor Valid range: 1 to 127.
rlInt8_t monStartTime
This field determines when the monitoring starts in each chirp relative to the start of the ramp....
rlUInt16_t noiseThresh
The measured RX input referred noise figure at the enabled RF frequencies, for all channels,...
rlUInt8_t reserved1
Reserved for Future use.
rlUInt8_t reserved1
Reserved for Future use.
Digital monitoring latent fault reporting configuration.
rlUInt8_t numSlices
Number of (primary + secondary) slices to monitor Valid range: 1 to 127.
rlUInt8_t profileIndx
This field indicates the profile index for which this configuration applies.
rlUInt8_t reportMode
Value Definition 0 Report is sent every monitoring period 1 Report is sent only on a failure 2 ...
MMWL_EXPORT rlReturnVal_t rlRfRxGainPhMonConfig(rlUInt8_t deviceMap, rlRxGainPhaseMonConf_t *data)
This API is to set RX gain and phase monitoring config to device.
rlUInt8_t reserved1
Reserved for Future use.
MMWL_EXPORT rlReturnVal_t rlRfRxSigImgMonConfig(rlUInt8_t deviceMap, rlSigImgMonConf_t *data)
Sets information related to signal and image band energy.
rlTxBallbreakMonConf_t * tx0BallBrkMonCfg
Tx ballbreak monitoring config for Tx0.
rlUInt32_t reserved2
Reserved for Future use.
rlUInt8_t reportMode
Value Definition 0 RESERVED 1 Report is send only upon a failure (after checking for thresholds) ...
rlUInt8_t phShifterMon4
TXn Phase shifter phase4 monitor value. Bits Phase shift definition b1:0 Reserved (set it to 0b00...
rlInt8_t monChirpSlope
Frequency slope for each monitoring chirp is encoded in 1 bytes (8 bit signed number)....
Internal signals for PLL control voltage monitoring configuration.
rlUInt16_t reserved0
Reserved for Future use.
MMWL_EXPORT rlReturnVal_t rlRfRxIfStageMonConfig(rlUInt8_t deviceMap, rlRxIfStageMonConf_t *data)
Sets information related to RX IF filter attenuation monitoring.
rlUInt8_t rfFreqBitMask
This field indicates the exact RF frequencies inside the profile's RF band at which to measure the ...
rlUInt8_t profileIndx
This field indicates the Profile Index for which this configuration applies.
MMWL_EXPORT rlReturnVal_t rlRfTxPhShiftMonConfig(rlUInt8_t deviceMap, rlAllTxPhShiftMonConf_t *data)
Sets information related to TX Phase shifter monitoring.
rlUInt16_t reserved1
Reserved for Future use.
rlUInt8_t reserved0
Reserved for Future use.
rlUInt8_t profileIndx
This field indicates the Profile Index for which this monitoring configuration applies....
rlUInt8_t rxEn
This field indicates the RX channels that should be enabled for TX to RX loopback measurement....
rlTxBallbreakMonConf_t * tx1BallBrkMonCfg
Tx ballbreak monitoring config for Tx1.
rlUInt8_t reserved0
Reserved for Future use.
rlUInt8_t reserved0
Reserved for Future use.
rlUInt32_t reserved2
Reserved for Future use.
rlUInt16_t rxGainMismatchErrThresh
The magnitude of difference between measured RX gains across the enabled channels at each enabled R...
rlUInt32_t reserved0
Reserved for Future use.
rlUInt8_t profileIndx
This field indicates the profile Index for which this configuration applies.
MMWL_EXPORT rlReturnVal_t rlRfSynthFreqMonConfig(rlUInt8_t deviceMap, rlSynthFreqMonConf_t *data)
Sets information related to synthesizer frequency.
rlUInt8_t phShifterIncVal2
Phase shifter monitoring increment value for phase2, the monitoring phase will be incremented by this...
MMWL_EXPORT rlReturnVal_t rlRfDigMonEnableConfig(rlUInt8_t deviceMap, rlMonDigEnables_t *data)
Sets the consolidated configuration of all digital monitoring.
Definition: rl_monitoring.c:93
rlUInt32_t reserved3
Reserved for Future use.
rlUInt8_t txEnable
This field indicates if and which TX channels should be enabled while measuring RX mixer input powe...
rlUInt16_t reserved1
Reserved for Future use.
rlUInt8_t reserved0
Reserved for Future use.
rlUInt32_t reserved2
Reserved for Future use.
rlUInt8_t reportMode
Value Definition 0 RESERVED 1 Report is send only upon a failure(after checking for thresholds) ...
rlUInt32_t reserved2
Reserved for Future use.
rlUInt8_t profileIndx
The RF analog settings corresponding to this profile are used for monitoring the enabled signals,...
rlUInt16_t txPowFlatnessErrThresh
The magnitude of measured TX power flatness error, for each enabled channel, is compared against th...
rlUInt16_t rxGainFlatnessErrThresh
The magnitude of measured RX gain flatness error, for each enabled channel, is compared against thi...
rlUInt8_t rxChannelMask
This field is applicable only for SAT_MON_MODE = 0 Masks RX channels used for monitoring....
rlUInt8_t profileIndx
This field indicates the Profile Index for which this configuration applies.
MMWL_EXPORT rlReturnVal_t rlRfAnaFaultInjConfig(rlUInt8_t deviceMap, rlAnaFaultInj_t *data)
Sets information related to RF fault injection.
rlUInt8_t profileIndx
This field indicates the profile Index for which this configuration applies.
rlUInt8_t reportMode
Value Definition 0 Report is sent every monitoring period without threshold check 1 Report is sen...
rlUInt8_t reserved0
Reserved for Future use.
TX Phase shifter monitoring configuration.
rlUInt8_t reserved0
Reserved for Future use.
TX power monitoring configuration.
RX noise monitoring configuration.
RX IF stage monitoring configuration.
rlUInt8_t reportMode
Value Definition 0 Report is sent every monitoring period without threshold check 1 Report is sen...
rlTxIntAnaSignalsMonConf_t * tx2IntAnaSgnlMonCfg
Internal signals in the Tx-2 path monitoring config.
TX ballbreak monitoring configuration.
rlInt8_t sync20GMaxThresh
Maximum threshold for 20GHz monitoring 1 LSB = 1 dBm Valid Range: -63 to +63 dBm.
MMWL_EXPORT rlReturnVal_t rlRfPllContrlVoltMonConfig(rlUInt8_t deviceMap, rlPllContrVoltMonConf_t *data)
Sets information related to APLL and Synthesizer's control voltage signals monitoring.
rlUInt8_t txEn
This field indicates the TX channels that should be compared for gain and phase balance....
Internal signals in the TX path monitoring configuration.
rlUInt8_t profileIndx
This field indicates the profile Index for which this configuration applies.
rlUInt32_t reserved1
Reserved for Future use.
rlUInt8_t lpfCutoffBandEdgeDroopThresh
The LPF band edge droop of RX channels are compared against the corresponding thresholds given in t...
rlUInt8_t monitorMode
This field configures whether this monitor should be done for functional active chirps (mode 0) or ...
rlUInt16_t numSlices
Number of (primary + secondary) time slices to monitor. Valid range: 1 to 127 .
MMWL_EXPORT rlReturnVal_t rlRfRxIfSatMonConfig(rlUInt8_t deviceMap, rlRxSatMonConf_t *data)
Sets information related to RX saturation detector monitoring.
RX ADC and IF saturation information.
rlTxPowMonConf_t * tx1PowrMonCfg
Power Monitoring Configuration for Tx1.
MMWL_EXPORT rlReturnVal_t rlRfTempMonConfig(rlUInt8_t deviceMap, rlTempMonConf_t *data)
This API configure the on chip temperature monitors and report the soft results from the monitor....
TX gain and phase mismatch monitoring configuration.
rlUInt32_t reserved4
Reserved for Future use.
rlTxPhShiftMonConf_t * tx1PhShiftMonCfg
Tx-1 Phase shifter monitoring config.
rlUInt8_t vcoMonEn
This bit mask can be used to enable/disable the monitoring of non-live VCO profiles,...
rlUInt16_t reserved2
Reserved for Future use.
rlUInt16_t freqErrThresh
During the chirp, the error of the measured instantaneous chirp frequency w.r.t. the desired value ...
rlUInt8_t profileIndx
The RF analog settings corresponding to this profile are used for monitoring RX mixer input power u...
rlUInt8_t txSel
Value Definition 0 TX0 is used for generating loopback signal for RX gain measurement 1 TX1 is us...
MMWL_EXPORT rlReturnVal_t rlRfGpadcIntAnaSignalsMonConfig(rlUInt8_t deviceMap, rlGpadcIntAnaSignalsMonConf_t *data)
Sets information related to GPADC Internal Analog Signals monitoring.
rlUInt32_t reserved2
Reserved for Future use.
rlUInt16_t reserved1
Reserved for Future use.
MMWL_EXPORT rlReturnVal_t rlRfDigMonPeriodicConfig(rlUInt8_t deviceMap, rlDigMonPeriodicConf_t *data)
Sets the consolidated configuration.
TX ballbreak monitoring configuration.
MMWL_EXPORT rlReturnVal_t rlRfExtAnaSignalsMonConfig(rlUInt8_t deviceMap, rlExtAnaSignalsMonConf_t *data)
Sets information related to external DC signals monitoring.
rlUInt16_t txPhaseMismatchThresh
The magnitude of measured TX phase mismatch across the enabled channels at each enabled RF frequenc...
Synthesizer frequency monitoring configuration.
rlUInt8_t phShifterMonCfg
Enable at least two phase settings to measure phase error and to apply threshold in reporting mode 1 ...
rlUInt32_t reserved2
Reserved for Future use.
Digital monitoring configuration.
Definition: rl_monitoring.h:72
rlUInt16_t hpfCutoffErrThresh
The absolute values of RX IF HPF cutoff percentage frequency errors are compared against the corres...
rlTxIntAnaSignalsMonConf_t * tx1IntAnaSgnlMonCfg
Internal signals in the Tx-1 path monitoring config.
rlUInt8_t rfFreqBitMask
This field indicates the exact RF frequencies inside the profile's RF band at which to measure the ...
rlUInt16_t ifaGainErrThresh
The absolute deviation of RX IFA Gain from the expected gain for each enabled RX channel is compare...
MMWL_EXPORT rlReturnVal_t rlRfPmClkLoIntAnaSignalsMonConfig(rlUInt8_t deviceMap, rlPmClkLoIntAnaSignalsMonConf_t *data)
Sets information related to Power Management, Clock generation and LO distribution.
rlUInt8_t reportMode
Value Definition 0 Report is sent every monitoring period without threshold check 1 Report is sen...
Internal signals for GPADC monitoring configuration.
TX Phase shifter monitoring configuration.
rlUInt16_t txPhShiftDacMonThresh
The TX phase shifter DAC monitor delta threshold when TX_PS_DAC_MON is Enabled 1 LSB = 1....
rlInt16_t anaTempThreshMax
The temperatures read from near the sensors near the RF analog modules are compared against a maximum...
rlUInt16_t reserved1
Reserved for Future use.
rlUInt8_t profileIndx
The RF analog settings corresponding to this profile are used for monitoring the enabled signals,...
rlTxIntAnaSignalsMonConf_t * tx0IntAnaSgnlMonCfg
Internal signals in the Tx-0 path monitoring config.
RX mixer input power monitoring configuration.
rlUInt32_t reserved1
Reserved for Future use.
rlUInt8_t satMonSel
01 => Enable only the ADC saturation monitor 11 => Enable both the ADC and IFA1 saturation monitors
rlUInt16_t rxGainAbsThresh
The magnitude of difference between the programmed and measured RX gain for each enabled channel at...
rlUInt32_t reserved3
Reserved for Future use.
rlUInt16_t tempDiffThresh
The maximum difference across temperatures read from all the enabled sensors is compared against this...
MMWL_EXPORT rlReturnVal_t rlRfTxIntAnaSignalsMonConfig(rlUInt8_t deviceMap, rlAllTxIntAnaSignalsMonConf_t *data)
Sets information related to TX Internal Analog Signals monitoring.
rlUInt16_t dccPairEnables
This field indicates which pairs of clocks to monitor. When a bit in the field is set to 1,...
MMWL_EXPORT rlReturnVal_t rlRfRxNoiseMonConfig(rlUInt8_t deviceMap, rlRxNoiseMonConf_t *data)
Sets information related to RX noise monitoring.
rlUInt8_t phShifterIncVal3
Phase shifter monitoring increment value for phase3, the monitoring phase will be incremented by this...
rlUInt32_t reserved3
Reserved for Future use.
rlUInt8_t phShifterMon3
TXn Phase shifter phase3 monitor value. Bits Phase shift definition b1:0 Reserved (set it to 0b00...
rlUInt8_t rfFreqBitMask
This field indicates the exact RF frequencies inside the profile's RF band at which to measure the ...
rlUInt16_t txPowAbsErrThresh
The magnitude of difference between the programmed and measured TX power for each enabled channel a...
rlUInt16_t reserved0
Reserved for Future use.
rlTxBallbreakMonConf_t * tx2BallBrkMonCfg
Tx ballbreak monitoring config for Tx2.
Analog monitoring configuration.
rlUInt8_t profileIndx
This field indicates the profile Index for which this configuration applies.
rlUInt8_t signalBuffEnables
This field indicates the sets of externally fed DC signals which are to be buffered before being fe...
rlInt8_t monChirpSlope
Frequency slope for each monitoring chirp is encoded in 1 bytes (8 bit signed number) 1 LSB = 3....
rlUInt32_t reserved0
Reserved for Future use.
rlUInt32_t reserved2
Reserved for Future use.
rlTxPowMonConf_t * tx2PowrMonCfg
Power Monitoring Configuration for Tx2.
rlUInt8_t rxEn
This field indicates the RX channels that should be enabled for TX to RX loopback measurement....
RX signal and image band energy statistics.
MMWL_EXPORT rlReturnVal_t rlRfRxIntAnaSignalsMonConfig(rlUInt8_t deviceMap, rlRxIntAnaSignalsMonConf_t *data)
Sets information related to RX Internal Analog Signals monitoring.
rlUInt8_t reportMode
Value Definition 0 RESERVED 1 Report is send only upon a failure(after checking for thresholds) ...
rlUInt8_t signalInpEnables
This field indicates the sets of externally fed DC signals which are to be monitored using GPADC....
rlUInt32_t periodicEnableMask
Bit Monitoring 0 PERIODIC_CONFG_REGISTER_READ_EN 1 RESERVED 2 DFE_STC_EN 3 FRAME_TIMING_MONIT...
rlInt16_t anaTempThreshMin
The temperatures read from near the sensors near the RF analog modules are compared against a minimum...
Temperature sensor monitoring configuration.
rlUInt8_t reserved0
Reserved for Future use.
rlUInt8_t phShifterMon2
TXn Phase shifter phase2 monitor value. Bits Phase shift definition b1:0 Reserved (set it to 0b00...
rlUInt8_t lpfCutoffStopBandAttenThresh
The LPF stop band attenuation at 2x analog LPF’s band edge with respect to the analog LPF’s band ed...
rlInt16_t digTempThreshMax
The temperatures read from near the sensor near the digital module are compared against a maximum thr...
Internal signals in the TX path monitoring configuration.
rlUInt16_t rxGainPhaseMismatchErrThresh
The magnitude of measured RX phase mismatch across the enabled channels at each enabled RF frequenc...
Internal signals for PM, CLK and LO monitoring configuration.
rlUInt8_t sync20GSigSel
Value Definition 0 20GHz SYNC monitoring disabled 1 FMCW_SYNC_IN monitoring enabled 2 FMCW_SYNC...
MMWL_EXPORT rlReturnVal_t rlRfDualClkCompMonConfig(rlUInt8_t deviceMap, rlDualClkCompMonConf_t *data)
Sets information related to the DCC based clock frequency monitoring.
rlTxPowMonConf_t * tx0PowrMonCfg
Power Monitoring Configuration for Tx0.
rlTxPhShiftMonConf_t * tx0PhShiftMonCfg
Tx-0 Phase shifter monitoring config.
rlUInt8_t profileIndx
This field indicates the profile Index for which this configuration applies.
rlUInt16_t txPhaseErrorThresh
The threshold for deviation of the TX output phase difference between the measured phase values and c...
rlUInt8_t reserved1
Reserved for Future use.
MMWL_EXPORT rlReturnVal_t rlRfTxGainPhaseMismatchMonConfig(rlUInt8_t deviceMap, rlTxGainPhaseMismatchMonConf_t *data)
Sets information related to TX gain and phase mismatch monitoring.
rlUInt8_t reportMode
Value Definition 0 Report is sent every monitoring period without threshold check 1 Report is sen...
rlUInt8_t reportMode
Value Definition 0 RESERVED 1 Report is send only upon a failure (after checking for thresholds) ...
rlUInt32_t reserved2
Reserved for Future use.
rlUInt16_t thresholds
The measured RX mixer input voltage swings during this monitoring is compared against the minimum a...
RX gain and phase monitoring configuration.
rlUInt8_t reserved0
Reserved for Future use.
rlUInt8_t reportMode
Value Definition 0 RESERVED 1 Report is send only upon a failure (after checking for thresholds) ...
rlUInt16_t reserved1
Reserved for Future use.
rlInt16_t digTempThreshMin
The temperatures read from near the sensor near the digital module are compared against a minimum thr...
rlUInt8_t phShifterMon1
TXn Phase shifter phase1 monitor value. Bits Phase shift definition b1:0 Reserved (set it to 0b00...
rlUInt8_t reportMode
Value Definition 0 Report is sent every monitoring period without threshold check 1 Report is sen...
rlUInt16_t reserved2
Reserved for Future use.
rlUInt16_t reserved1
Reserved for Future use.
rlUInt32_t reserved1
Reserved for Future use.
rlUInt8_t phShifterIncVal4
Phase shifter monitoring increment value for phase4, the monitoring phase will be incremented by this...
rlUInt8_t rfFreqBitMask
This field indicates the RF frequencies inside the profile's RF band at which to measure the required...
rlUInt32_t reserved1
Reserved for Future use.
MMWL_EXPORT rlReturnVal_t rlRfTxPowrMonConfig(rlUInt8_t deviceMap, rlAllTxPowMonConf_t *data)
Sets information related to TX power monitoring.
rlUInt16_t txAmplErrorThresh
The threshold for deviation of the TX output amplitude difference between all enabled phase settings....
rlUInt32_t enMask
Bit: Dig Monitoring 0 Reserved 1 CR4 and VIM lockstep test of diagnostic 2 Reserved 3 VIM tes...
rlUInt32_t reserved1
Reserved for Future use.

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