315 #include <ti/control/mmwavelink/include/rl_datatypes.h> 327 #if defined(WIN32) || defined(WIN32_) || defined(_MSC_VER) 328 #define MMWL_EXPORT __declspec(dllexport) 334 #define RL_MMWAVELINK_VERSION "2.2.0.2.6.4.20" 335 #define RL_MMWAVELINK_VERSION_MAJOR (2U) 336 #define RL_MMWAVELINK_VERSION_MINOR (2U) 337 #define RL_MMWAVELINK_VERSION_BUILD (0U) 338 #define RL_MMWAVELINK_VERSION_DEBUG (2U) 339 #define RL_MMWAVELINK_VERSION_DAY (6U) 340 #define RL_MMWAVELINK_VERSION_MONTH (4U) 341 #define RL_MMWAVELINK_VERSION_YEAR (20U) 344 #define RL_RET_CODE_OK ((rlReturnVal_t)0) 345 #define RL_RET_CODE_PROTOCOL_ERROR (-1) 346 #define RL_RET_CODE_INVALID_INPUT (-2) 347 #define RL_RET_CODE_SELF_ERROR (-3) 348 #define RL_RET_CODE_RADAR_IF_ERROR (-4) 349 #define RL_RET_CODE_MALLOC_ERROR (-5) 350 #define RL_RET_CODE_CRC_FAILED (-6) 352 #define RL_RET_CODE_CHKSUM_FAILED (-7) 354 #define RL_RET_CODE_RESP_TIMEOUT (-8) 356 #define RL_RET_CODE_FATAL_ERROR (-9) 358 #define RL_RET_CODE_RADAR_OSIF_ERROR (-10) 359 #define RL_RET_CODE_INVALID_STATE_ERROR (-11) 360 #define RL_RET_CODE_API_NOT_SUPPORTED (-12) 361 #define RL_RET_CODE_MSGID_MISMATCHED (-13) 363 #define RL_RET_CODE_NULL_PTR (-14) 364 #define RL_RET_CODE_INTERFACE_CB_NULL (-15) 365 #define RL_RET_CODE_NACK_ERROR (-16) 366 #define RL_RET_CODE_HOSTIRQ_TIMEOUT (-17) 369 #define RL_RET_CODE_RX_SEQ_NUM_NOT_MATCH (-18) 373 #define RL_RET_CODE_INVLD_OPCODE (1U) 374 #define RL_RET_CODE_INVLD_NUM_SB (2U) 375 #define RL_RET_CODE_INVLD_SB_ID (3U) 376 #define RL_RET_CODE_INVLD_SB_LEN (4U) 377 #define RL_RET_CODE_SB_INVL_DATA (5U) 378 #define RL_RET_CODE_SB_PROCESS_ERR (6U) 379 #define RL_RET_CODE_MISMATCH_FILE_CRC (7U) 380 #define RL_RET_CODE_MISMATCH_FILE_TYPE (8U) 383 #define RL_RET_CODE_FRAME_ALREADY_STARTED (20U) 385 #define RL_RET_CODE_FRAME_ALREADY_ENDED (21U) 387 #define RL_RET_CODE_FRAME_CFG_NOT_RECVD (22U) 389 #define RL_RET_CODE_FRAME_TRIG_INVL_IN (23U) 393 #define RL_RET_CODE_CH_CFG_RX_INVAL_IN (24U) 395 #define RL_RET_CODE_CH_CFG_TX_INVAL_IN (25U) 397 #define RL_RET_CODE_CH_CFG_CASC_INVAL_IN (26U) 401 #define RL_RET_CODE_ADC_BITS_INVAL_IN (27U) 403 #define RL_RET_CODE_ADC_FORM_INVAL_IN (28U) 407 #define RL_RET_CODE_LP_ADC_INVAL_IN (29U) 411 #define RL_RET_CODE_DYN_PS_INVAL_IN (30U) 415 #define RL_RET_CODE_HSI_DIV_INVAL_IN (31U) 416 #define RL_RET_CODE_RESERVED0 (32U) 417 #define RL_RET_CODE_HSI_DIV_INVAL_1IN (33U) 419 #define RL_RET_CODE_HSI_DIV_INVAL_2IN (34U) 423 #define RL_RET_CODE_PF_IND_INVAL_IN (35U) 424 #define RL_RET_CODE_PF_START_FREQ_INVAL_IN (36U) 426 #define RL_RET_CODE_PF_IDLE_TIME_INVAL_IN (37U) 427 #define RL_RET_CODE_PF_IDLE_TIME_1INVAL_IN (38U) 431 #define RL_RET_CODE_PF_ADC_START_INVAL_IN (39U) 432 #define RL_RET_CODE_PF_RAMP_END_INVAL_IN (40U) 433 #define RL_RET_CODE_PF_RAMP_END_1INVAL_IN (41U) 435 #define RL_RET_CODE_PF_TX0_INVAL_IN (42U) 437 #define RL_RET_CODE_PF_TX1_INVAL_IN (43U) 439 #define RL_RET_CODE_PF_TX2_INVAL_IN (44U) 441 #define RL_RET_CODE_RESERVED1 (45U) 442 #define RL_RET_CODE_PF_FREQ_SLOPE_1INVAL_IN (46U) 444 #define RL_RET_CODE_PF_TX_START_INVAL_IN (47U) 446 #define RL_RET_CODE_PF_NUM_ADC_SMAP_INVAL_IN (48U) 448 #define RL_RET_CODE_PF_DFE_SAMP_RATE_INVAL_IN (49U) 450 #define RL_RET_CODE_PF_HPF1_CF_INVAL_IN (50U) 451 #define RL_RET_CODE_PF_HPF2_CF_INVAL_IN (51U) 452 #define RL_RET_CODE_PF_RX_GAIN_INVAL_IN (52U) 454 #define RL_RET_CODE_RESERVED2 (53U) 455 #define RL_RET_CODE_RESERVED3 (54U) 456 #define RL_RET_CODE_RESERVED4 (55U) 457 #define RL_RET_CODE_RESERVED5 (56U) 458 #define RL_RET_CODE_RESERVED6 (57U) 459 #define RL_RET_CODE_RESERVED7 (58U) 462 #define RL_RET_CODE_CHIRP_START_INVAL_IN (59U) 463 #define RL_RET_CODE_CHIRP_END_INVAL_IN (60U) 464 #define RL_RET_CODE_CHIRP_END_1INVAL_IN (61U) 465 #define RL_RET_CODE_CHIRP_PF_IND_INVAL_IN (62U) 466 #define RL_RET_CODE_CHIRP_PF_IND_1INVAL_IN (63U) 468 #define RL_RET_CODE_CHIRP_START_FREQ_INVAL_IN (64U) 469 #define RL_RET_CODE_CHIRP_SLOPE_INVAL_IN (65U) 470 #define RL_RET_CODE_CHIRP_SLOPE_1INVAL_IN (66U) 472 #define RL_RET_CODE_CHIRP_IDLE_TIME_INVAL_IN (67U) 473 #define RL_RET_CODE_CHIRP_ADC_START_INVAL_IN (68U) 474 #define RL_RET_CODE_CHIRP_ADC_START_1INVAL_IN (69U) 476 #define RL_RET_CODE_CHIRP_TX_ENA_INVAL_IN (70U) 477 #define RL_RET_CODE_CHIRP_TX_ENA_1INVAL_IN (71U) 482 #define RL_RET_CODE_FRAME_CHIRP_STR_INVAL_IN (72U) 483 #define RL_RET_CODE_FRAME_CHIRP_END_INVAL_IN (73U) 484 #define RL_RET_CODE_FRAME_CHIRP_END_1INVAL_IN (74U) 485 #define RL_RET_CODE_FRAME_CHIRP_END_2INVAL_IN (75U) 487 #define RL_RET_CODE_FRAME_CHIRP_PF_INVAL_IN (76U) 489 #define RL_RET_CODE_FRAME_CHIRP_LOOPS_INVAL_IN (77U) 490 #define RL_RET_CODE_RESERVED8 (78U) 491 #define RL_RET_CODE_FRAME_PERIOD_INVAL_IN (79U) 493 #define RL_RET_CODE_FRAME_PERIOD_1INVAL_IN (80U) 494 #define RL_RET_CODE_FRAME_TRIG_SEL_INVAL_IN (81U) 495 #define RL_RET_CODE_FRAME_TRIG_DELAY_INVAL_IN (82U) 496 #define RL_RET_CODE_FRAME_IS_ONGOING (83U) 497 #define RL_RET_CODE_FRAME_DUMMY_CHIRPS_INVAL_IN (160U) 501 #define RL_RET_CODE_AFRAME_NUM_SUBF_INVAL_IN (84U) 502 #define RL_RET_CODE_AFRAME_FORCE_PF_INVAL_IN (85U) 504 #define RL_RET_CODE_AFRAME_PF_IND_INVAL_IN (86U) 505 #define RL_RET_CODE_AFRAME_PF_IND_1INVAL_IN (87U) 507 #define RL_RET_CODE_AFRAME_CHIRP_STR_INVAL_IN (88U) 508 #define RL_RET_CODE_AFRAME_NCHIRP_INVAL_IN (89U) 510 #define RL_RET_CODE_AFRAME_NCHIRP_1INVAL_IN (90U) 512 #define RL_RET_CODE_AFRAME_CHIRP_PF_INVAL_IN (91U) 514 #define RL_RET_CODE_AFRAME_CHIRP_LOOPS_INVAL_IN (92U) 516 #define RL_RET_CODE_AFRAME_BURST_PERIOD_INVAL_IN (93U) 518 #define RL_RET_CODE_AFRAME_BURST_PER_1INVAL_IN (94U) 519 #define RL_RET_CODE_AFRAME_BURST_STIND_INVAL_IN (95U) 521 #define RL_RET_CODE_AFRAME_BURST_SIND_1INVAL_IN (96U) 525 #define RL_RET_CODE_AFRAME_NUM_BURSTS_INVAL_IN (97U) 527 #define RL_RET_CODE_AFRAME_BURST_LOOPS_INVAL_IN (98U) 529 #define RL_RET_CODE_AFRAME_SF_PERIOD_INVAL_IN (99U) 531 #define RL_RET_CODE_AFRAME_SF_PERIOD_1INVAL_IN (100U) 534 #define RL_RET_CODE_RESERVED9 (101U) 535 #define RL_RET_CODE_AFRAME_TRIG_SEL_INVAL_IN (102U) 536 #define RL_RET_CODE_AFRAME_TRIG_DELAY_INVAL_IN (103U) 537 #define RL_RET_CODE_AFRAME_IS_ONGOING (104U) 540 #define RL_RET_CODE_TS_POS_VECY_INVAL_IN (105U) 541 #define RL_RET_CODE_RESERVED10 (106U) 542 #define RL_RET_CODE_TS_VEL_VECXYZ_INVAL_IN (107U) 545 #define RL_RET_CODE_TS_SIG_LEVEL_INVAL_IN (108U) 546 #define RL_RET_CODE_TS_RX_ANT_POS_INVAL_IN (109U) 547 #define RL_RET_CODE_RESERVED11 (110U) 550 #define RL_RET_CODE_PROG_FILT_STARTINDX_INVALID (111U) 552 #define RL_RET_CODE_PROG_FILT_PROFILE_INVALID (112U) 553 #define RL_RET_CODE_PROG_FILT_UNSUPPORTED_DEV (113U) 556 #define RL_RET_CODE_PERCHIRPPHSHIFT_UNSUPPORTED_DEV (114U) 558 #define RL_RET_CODE_PERCHIRPPHSHIFT_STIND (115U) 559 #define RL_RET_CODE_PERCHIRPPHSHIFT_ENIND (116U) 560 #define RL_RET_CODE_PERCHIRPPHSHIFT_WRONG_STIND (117U) 563 #define RL_RET_CODE_RF_INIT_NOT_DONE (118U) 565 #define RL_RET_CODE_FORCE_TEMP_BIN_IDX_INVALID (286U) 567 #define RL_RET_CODE_FREQ_LIMIT_OUT_RANGE (119U) 569 #define RL_RET_CODE_CAL_MON_TIME_INVALID (120U) 570 #define RL_RET_CODE_RUN_CAL_PERIOD_INVALID (121U) 571 #define RL_RET_CODE_CONT_STREAM_MODE_EN (122U) 573 #define RL_RET_CODE_RX_GAIN_BOOT_CAL_NOT_DONE (123U) 576 #define RL_RET_CODE_LO_DIST_BOOT_CAL_NOT_DONE (124U) 579 #define RL_RET_CODE_TX_PWR_BOOT_CAL_NOT_DONE (125U) 582 #define RL_RET_CODE_PROG_FILTR_UNSUPPORTED_DFEMODE (126U) 583 #define RL_RET_CODE_ADC_BITS_FULL_SCALE_REDUC_INVAL (127U) 586 #define RL_RET_CODE_CAL_MON_NUM_CASC_DEV_INVALID (128U) 587 #define RL_RET_CODE_FRAME_TRIG_INVL_STOP_IN (129U) 589 #define RL_RET_CODE_RF_FREQBAND_INVALID (130U) 592 #define RL_RET_CODE_INVAL_LOOPBACK_TYPE (132U) 593 #define RL_RET_CODE_INVAL_LOOPBACK_BURST_IND (133U) 594 #define RL_RET_CODE_INVAL_LOOPBACK_CONFIG (134U) 595 #define RL_RET_CODE_DYN_CHIRP_INVAL_SEG (135U) 596 #define RL_RET_CODE_DYN_PERCHIRP_PHSHFT_INVA_SEG (136U) 597 #define RL_RET_CODE_INVALID_CAL_CHUNK_ID (137U) 598 #define RL_RET_CODE_INVALID_CAL_CHUNK_DATA (138U) 601 #define RL_RET_CODE_RX02_RF_TURN_OFF_TIME_INVALID (139U) 603 #define RL_RET_CODE_RX13_RF_TURN_OFF_TIME_INVALID (140U) 605 #define RL_RET_CODE_RX02_BB_TURN_OFF_TIME_INVALID (141U) 607 #define RL_RET_CODE_RX13_BB_TURN_OFF_TIME_INVALID (142U) 609 #define RL_RET_CODE_RX02_RF_PREENABLE_TIME_INVALID (143U) 611 #define RL_RET_CODE_RX13_RF_PREENABLE_TIME_INVALID (144U) 613 #define RL_RET_CODE_RX02_BB_PREENABLE_TIME_INVALID (145U) 615 #define RL_RET_CODE_RX13_BB_PREENABLE_TIME_INVALID (146U) 617 #define RL_RET_CODE_RX02_RF_TURN_ON_TIME_INVALID (147U) 619 #define RL_RET_CODE_RX13_RF_TURN_ON_TIME_INVALID (148U) 621 #define RL_RET_CODE_RX02_BB_TURN_ON_TIME_INVALID (149U) 623 #define RL_RET_CODE_RX13_BB_TURN_ON_TIME_INVALID (150U) 625 #define RL_RET_CODE_RX_LO_TURN_OFF_TIME_INVALID (151U) 627 #define RL_RET_CODE_TX_LO_TURN_OFF_TIME_INVALID (152U) 629 #define RL_RET_CODE_RX_LO_TURN_ON_TIME_INVALID (153U) 631 #define RL_RET_CODE_TX_LO_TURN_ON_TIME_INVALID (154U) 633 #define RL_RET_CODE_SUBFRAME_TRIGGER_INVALID (155U) 638 #define RL_RET_CODE_REGULAR_ADC_MODE_INVALID (156U) 640 #define RL_RET_CODE_CHIRP_ROW_SELECT_INVAL_IN (159U) 643 #define RL_RET_CODE_DEVICE_NOT_ASILB_TYPE (250U) 644 #define RL_RET_CODE_FRAME_ONGOING (251U) 647 #define RL_RET_CODE_INVLD_REPO_MODE (252U) 648 #define RL_RET_CODE_INVLD_PROFILE_ID (253U) 650 #define RL_RET_CODE_INVLD_PROFILE (254U) 652 #define RL_RET_CODE_INVLD_EXTSIG_SETLTIME (255U) 654 #define RL_RET_CODE_INVLD_NO_RX_ENABLED (256U) 655 #define RL_RET_CODE_INVLD_TX0_NOT_ENABLED (257U) 656 #define RL_RET_CODE_INVLD_TX1_NOT_ENABLED (258U) 657 #define RL_RET_CODE_INVLD_TX2_NOT_ENABLED (259U) 658 #define RL_RET_CODE_MON_INVALID_RF_BIT_MASK (260U) 659 #define RL_RET_CODE_RESERVED12 (261U) 660 #define RL_RET_CODE_RESERVED13 (262U) 661 #define RL_RET_CODE_MON_TX_EN_CHK_FAIL (263U) 662 #define RL_RET_CODE_MON_RX_CH_EN_CHK_FAIL (264U) 663 #define RL_RET_CODE_MON_TX_CH_PS_LB (265U) 666 #define RL_RET_CODE_INVLD_SAT_MON_SEL (266U) 667 #define RL_RET_CODE_INVLD_SAT_MON_PRI_SLICE_DUR (267U) 670 #define RL_RET_CODE_INVLD_SAT_MON_NUM_SLICES (268U) 672 #define RL_RET_CODE_INVLD_SIG_IMG_SLICENUM (269U) 674 #define RL_RET_CODE_INVLD_SIG_IMG_NUMSAMPPERSLICE (270U) 678 #define RL_RET_CODE_INVLD_SYNTH_L1_LIN (271U) 679 #define RL_RET_CODE_INVLD_SYNTH_L2_LIN (272U) 680 #define RL_RET_CODE_INVLD_SYNTH_N_LIN (273U) 681 #define RL_RET_CODE_INVLD_SYNTH_MON_START_TIME (274U) 683 #define RL_RET_CODE_INVLD_SYNTH_MON_LIN_RAM_ADDR (275U) 684 #define RL_RET_CODE_LDO_BYPASSED (279U) 686 #define RL_RET_CODE_INVLD_SIG_IMG_BAND_MONTR (280U) 688 #define RL_RET_CODE_ANALOG_MONITOR_NOT_SUPPORTED (281U) 689 #define RL_RET_CODE_ISSUE_TO_ENABLE_CASCASE_MODE (282U) 692 #define RL_RET_CODE_RX_SAT_MON_NOT_SUPPORTED (283U) 693 #define RL_API_NRESP_ANA_MON_MODE_NOT_API_BASED (284U) 696 #define RL_API_NRESP_ANA_MON_TRIG_TYPE_INVALID (285U) 700 #define RL_RET_CODE_CHIRP_FAIL (290U) 701 #define RL_RET_CODE_PD_PWR_LVL (291U) 703 #define RL_RET_CODE_ADC_PWR_LVL (292U) 704 #define RL_RET_CODE_NOISE_FIG_LOW (293U) 705 #define RL_RET_CODE_PD_CDS_ON_FAIL (294U) 707 #define RL_RET_CODE_PGA_GAIN_FAIL (295U) 708 #define RL_RET_CODE_20G_MONITOR_NOT_SUPPORTED (296U) 710 #define RL_RET_CODE_MONITOR_CONFIG_MODE_INVALID (297U) 711 #define RL_RET_CODE_LIVE_NONLIVE_TOGETHER_INVALID (298U) 716 #define RL_RET_CODE_CHIRP_PARAM_IND_INVALID (300U) 717 #define RL_RET_CODE_RESET_MODE_INVALID (301U) 718 #define RL_RET_CODE_DEL_LUT_PAR_UPT_PER_INVALID (303U) 721 #define RL_RET_CODE_SF_CHIRP_PAR_DEL_INVALID (304U) 723 #define RL_RET_CODE_DEL_LUT_RESET_PERIOD_INVALID (305U) 726 #define RL_RET_CODE_LUT_PAT_ADD_OFF_INVALID (306U) 728 #define RL_RET_CODE_LUT_NUM_PATTERNS_INVALID (307U) 730 #define RL_RET_CODE_LUT_SF_BURST_IND_OFF_INVALID (308U) 733 #define RL_RET_CODE_LUT_CHIRP_PAR_SCALE_SIZE_INVALID (309U) 735 #define RL_RET_CODE_LEGACY_API_INPUTS_INVALID (310U) 738 #define RL_RET_CODE_ALL_CHIRP_PARAMS_NOT_DEFINED (311U) 740 #define RL_RET_CODE_TX_PHASE_SHIF_INT_INVALID (312U) 742 #define RL_RET_CODE_NUM_PATTERNS_PROGRAM_INVALID (313U) 746 #define RL_RET_CODE_NUM_CHIRPS_PROGRAM_INVALID (315U) 748 #define RL_RET_CODE_TX_PH_SHIFT_PHASE_MASK_INVALID (316U) 751 #define RL_RET_CODE_TX_PH_SHIFT_RX_MASK_INVALID (317U) 756 #define RL_RET_CODE_NUM_BYTES_PROGRAM_INVALID (314U) 758 #define RL_RET_CODE_TX_IND_PH_SHIFT_RESTORE_INVALID (318U) 762 #define RL_RET_CODE_RX_CHAN_EN_OOR (1001U) 763 #define RL_RET_CODE_NUM_ADC_BITS_OOR (1002U) 764 #define RL_RET_CODE_ADC_OUT_FMT_OOR (1003U) 765 #define RL_RET_CODE_IQ_SWAP_SEL_OOR (1004U) 767 #define RL_RET_CODE_CHAN_INTERLEAVE_OOR (1005U) 771 #define RL_RET_CODE_DATA_INTF_SEL_OOR (1006U) 772 #define RL_RET_CODE_DATA_FMT_PKT0_INVALID (1007U) 774 #define RL_RET_CODE_DATA_FMT_PKT1_INVALID (1008U) 778 #define RL_RET_CODE_LANE_ENABLE_OOR (1009U) 779 #define RL_RET_CODE_LANE_ENABLE_INVALID (1010U) 782 #define RL_RET_CODE_LANE_CLK_CFG_OOR (1011U) 783 #define RL_RET_CODE_LANE_CLK_CFG_INVALID (1012U) 784 #define RL_RET_CODE_DATA_RATE_OOR (1013U) 787 #define RL_RET_CODE_LANE_FMT_MAP_OOR (1014U) 788 #define RL_RET_CODE_LANE_PARAM_CFG_OOR (1015U) 791 #define RL_RET_CODE_CONT_STREAM_MODE_OOR (1016U) 793 #define RL_RET_CODE_CONT_STREAM_MODE_INVALID (1017U) 797 #define RL_RET_CODE_LANE0_POS_POL_OOR (1018U) 798 #define RL_RET_CODE_LANE1_POS_POL_OOR (1019U) 799 #define RL_RET_CODE_LANE2_POS_POL_OOR (1020U) 800 #define RL_RET_CODE_LANE3_POS_POL_OOR (1021U) 801 #define RL_RET_CODE_CLOCK_POS_OOR (1022U) 804 #define RL_RET_CODE_HALF_WORDS_PER_CHIRP_OOR (1023U) 807 #define RL_RET_CODE_NUM_SUBFRAMES_OOR (1024U) 809 #define RL_RET_CODE_SF1_TOT_NUM_CHIRPS_OOR (1025U) 810 #define RL_RET_CODE_SF1_NUM_ADC_SAMP_OOR (1026U) 812 #define RL_RET_CODE_SF1_NUM_CHIRPS_OOR (1027U) 815 #define RL_RET_CODE_SF2_TOT_NUM_CHIRPS_OOR (1028U) 817 #define RL_RET_CODE_SF2_NUM_ADC_SAMP_OOR (1029U) 819 #define RL_RET_CODE_SF2_NUM_CHIRPS_OOR (1030U) 822 #define RL_RET_CODE_SF3_TOT_NUM_CHIRPS_OOR (1031U) 824 #define RL_RET_CODE_SF3_NUM_ADC_SAMP_OOR (1032U) 826 #define RL_RET_CODE_SF3_NUM_CHIRPS_OOR (1033U) 829 #define RL_RET_CODE_SF4_TOT_NUM_CHIRPS_OOR (1034U) 831 #define RL_RET_CODE_SF4_NUM_ADC_SAMP_OOR (1035U) 833 #define RL_RET_CODE_SF4_NUM_CHIRPS_OOR (1036U) 835 #define RL_RET_CODE_MCUCLOCK_CTRL_OOR (1040U) 836 #define RL_RET_CODE_MCUCLOCK_SRC_OOR (1041U) 838 #define RL_RET_CODE_PMICCLOCK_CTRL_OOR (1042U) 839 #define RL_RET_CODE_PMICCLOCK_SRC_OOR (1043U) 840 #define RL_RET_CODE_PMICMODE_SELECT_OOR (1044U) 841 #define RL_RET_CODE_PMICFREQ_SLOPE_OOR (1045U) 842 #define RL_RET_CODE_PMICCLK_DITHER_EN_OOR (1046U) 844 #define RL_RET_CODE_TESTPATTERN_EN_OOR (1047U) 846 #define RL_RET_CODE_LFAULTTEST_UNSUPPORTED_OOR (1048U) 850 #define RL_API_NRESP_LFAULTTEST_UNSUPPORTED_OOR (1051U) 853 #define RL_API_NRESP_DATACONFIG_NOTDONE (1052U) 863 #define RL_DISABLE_LOGGING 1 866 #define RL_OSI_RET_CODE_OK (0) 867 #define RL_IF_RET_CODE_OK (0) 869 #ifdef RL_EXTENDED_MESSAGE 872 #define RL_MAX_SIZE_MSG (2044U) 874 #define RL_MAX_SIZE_MSG (256U) 888 #define RL_DEVICE_MAP_NATIVE (0U) 889 #define RL_DEVICE_MAP_CASCADED_1 (1U) 890 #define RL_DEVICE_MAP_CASCADED_2 (2U) 891 #define RL_DEVICE_MAP_CASCADED_3 (4U) 892 #define RL_DEVICE_MAP_CASCADED_4 (8U) 895 #define RL_DEVICE_MAP_CASCADED_ALL (RL_DEVICE_MAP_CASCADED_1 |\ 896 RL_DEVICE_MAP_CASCADED_2 |\ 897 RL_DEVICE_MAP_CASCADED_3 |\ 898 RL_DEVICE_MAP_CASCADED_4) 901 #define RL_DEVICE_INDEX_INTERNAL_BSS (0U) 902 #define RL_DEVICE_INDEX_INTERNAL_DSS_MSS (1U) 903 #define RL_DEVICE_INDEX_INTERNAL_HOST (2U) 906 #define RL_DEVICE_MAP_INTERNAL_BSS (RL_DEVICE_MAP_CASCADED_1) 908 #define RL_DEVICE_MAP_INTERNAL_DSS_MSS (RL_DEVICE_MAP_CASCADED_2) 909 #define RL_DEVICE_MAP_INTERNAL_HOST (RL_DEVICE_MAP_CASCADED_3) 912 #define RL_DEVICE_CONNECTED_MAX (4U) 929 #ifndef RL_CASCADE_NUM_DEVICES 930 #define RL_CASCADE_NUM_DEVICES (1U) 936 #define RL_CRC_TYPE_16BIT_CCITT (0U) 937 #define RL_CRC_TYPE_32BIT (1U) 938 #define RL_CRC_TYPE_64BIT_ISO (2U) 939 #define RL_CRC_TYPE_NO_CRC (3U) 944 #define RL_PLATFORM_HOST (0x0U) 945 #define RL_PLATFORM_MSS (0x1U) 946 #define RL_PLATFORM_DSS (0x2U) 951 #define RL_AR_DEVICETYPE_12XX (0x0U) 952 #define RL_AR_DEVICETYPE_14XX (0x1U) 953 #define RL_AR_DEVICETYPE_16XX (0x2U) 954 #define RL_AR_DEVICETYPE_18XX (0x3U) 955 #define RL_AR_DEVICETYPE_68XX (0x4U) 956 #define RL_AR_DEVICETYPE_22XX (0x5U) 961 #define RL_DBG_LEVEL_NONE ((rlUInt8_t)0U) 962 #define RL_DBG_LEVEL_ERROR ((rlUInt8_t)1U) 963 #define RL_DBG_LEVEL_WARNING ((rlUInt8_t)2U) 964 #define RL_DBG_LEVEL_INFO ((rlUInt8_t)3U) 965 #define RL_DBG_LEVEL_DEBUG ((rlUInt8_t)4U) 966 #define RL_DBG_LEVEL_VERBOSE ((rlUInt8_t)5U) 971 #define RL_SENSOR_ANALOGTEST_ONE (0U) 972 #define RL_SENSOR_ANALOGTEST_TWO (1U) 973 #define RL_SENSOR_ANALOGTEST_THREE (2U) 974 #define RL_SENSOR_ANALOGTEST_FOUR (3U) 975 #define RL_SENSOR_ANAMUX (4U) 976 #define RL_SENSOR_VSENSE (5U) 977 #define RL_MAX_GPADC_SENSORS (6U) 982 #define RL_SWAP_32(x) (((x) & 0x0000FFFFU)<<16U)|(((x) & 0xFFFF0000U)>>16U); 999 typedef rlInt32_t rlReturnVal_t;
1004 typedef rlUInt8_t rlCrcType_t;
1011 typedef void (*RL_P_OSI_SPAWN_ENTRY)(
const void* pValue);
1016 typedef void (*RL_P_EVENT_HANDLER)(rlUInt8_t deviceIndex,
void* pValue);
1021 typedef struct rlComIfCbs
1035 rlComIfHdl_t (*rlComIfOpen)(rlUInt8_t deviceIndex, rlUInt32_t flags);
1050 rlInt32_t (*rlComIfRead)(rlComIfHdl_t fd, rlUInt8_t *pBuff, rlUInt16_t len);
1065 rlInt32_t (*rlComIfWrite)(rlComIfHdl_t fd, rlUInt8_t *pBuff, rlUInt16_t len);
1078 rlInt32_t (*rlComIfClose)(rlComIfHdl_t fd);
1084 typedef struct rlOsiMutexCbs
1098 rlInt32_t (*rlOsiMutexCreate)(rlOsiMutexHdl_t* mutexHdl, rlInt8_t* name);
1124 rlInt32_t (*rlOsiMutexLock)(rlOsiMutexHdl_t* mutexHdl, rlOsiTime_t timeout);
1138 rlInt32_t (*rlOsiMutexUnLock)(rlOsiMutexHdl_t* mutexHdl);
1151 rlInt32_t (*rlOsiMutexDelete)(rlOsiMutexHdl_t* mutexHdl);
1157 typedef struct rlOsiSemCbs
1171 rlInt32_t (*rlOsiSemCreate)(rlOsiSemHdl_t* semHdl, rlInt8_t* name);
1185 rlInt32_t (*rlOsiSemWait)(rlOsiSemHdl_t* semHdl, rlOsiTime_t timeout);
1198 rlInt32_t (*rlOsiSemSignal)(rlOsiSemHdl_t* semHdl);
1211 rlInt32_t (*rlOsiSemDelete)(rlOsiSemHdl_t* semHdl);
1217 typedef struct rlOsiMsgQCbs
1236 rlInt32_t (*rlOsiSpawn)(RL_P_OSI_SPAWN_ENTRY pEntry,
const void* pValue, rlUInt32_t flags);
1243 typedef struct rlOsiCbs
1262 typedef struct rlEventCbs
1279 void (*rlAsyncEvent)(rlUInt8_t devIndex, rlUInt16_t subId, rlUInt16_t subLen,
1280 rlUInt8_t *payload);
1286 typedef struct rlTimerCbs
1288 rlInt32_t (*rlDelay)(rlUInt32_t delay);
1294 typedef struct rlCmdParserCbs
1296 rlInt32_t (*rlCmdParser)(rlUInt8_t rxMsgClass, rlInt32_t inVal);
1297 rlInt32_t (*rlPostCnysStep)(rlUInt8_t devIndex);
1306 typedef struct rlCrcCbs
1324 rlInt32_t (*rlComputeCRC)(rlUInt8_t* data, rlUInt32_t dataLen, rlUInt8_t crcType,
1331 typedef struct rlDeviceCtrlCbs
1345 rlInt32_t (*rlDeviceEnable)(rlUInt8_t deviceIndex);
1359 rlInt32_t (*rlDeviceDisable)(rlUInt8_t deviceIndex);
1371 void (*rlDeviceMaskHostIrq)(rlComIfHdl_t fd);
1383 void (*rlDeviceUnMaskHostIrq)(rlComIfHdl_t fd);
1402 rlInt32_t (*rlDeviceWaitIrqStatus)(rlComIfHdl_t fd, rlUInt8_t highLow);
1415 rlUInt16_t (*rlCommIfAssertIrq)(rlUInt8_t highLow);
1434 rlInt32_t (*rlRegisterInterruptHandler)(rlUInt8_t deviceIndex,
1435 RL_P_EVENT_HANDLER pHandler,
void* pValue);
1440 typedef rlInt32_t (*rlPrintFptr)(
const rlInt8_t* format, ...);
1445 typedef struct rlDbgCb
1460 rlPrintFptr rlPrint;
1470 typedef struct rlClientCbs
1504 rlCrcType_t crcType;
1510 rlUInt32_t ackTimeout;
1521 rlUInt8_t arDevType;
1533 typedef struct rlInitComplete
1538 rlUInt32_t powerUpTime;
1594 rlUInt64_t powerUpStatus;
1637 rlUInt64_t bootTestStatus;
1644 typedef struct rlStartComplete
1682 rlUInt32_t powerUpTime;
1686 rlUInt32_t reserved0;
1690 rlUInt32_t reserved1;
1700 typedef struct rlMssEsmFault
1737 rlUInt32_t esmGrp1Err;
1773 rlUInt32_t esmGrp2Err;
1777 rlUInt32_t reserved0;
1781 rlUInt32_t reserved1;
1790 typedef struct rlMssBootErrStatus
1795 rlUInt32_t powerUpTime;
1851 rlUInt64_t powerUpStatus;
1894 rlUInt64_t bootTestStatus;
1901 typedef struct rlMssLatentFaultReport
1939 rlUInt32_t testStatusFlg1;
1950 rlUInt32_t testStatusFlg2;
1954 rlUInt32_t reserved;
1962 typedef struct rlMssPeriodicTestStatus
1971 rlUInt32_t testStatusFlg;
1975 rlUInt32_t reserved;
1983 typedef struct rlMssRfErrStatus
1996 rlUInt32_t errStatusFlg;
2000 rlUInt32_t reserved;
2009 typedef struct rlBssEsmFault
2038 rlUInt32_t esmGrp1Err;
2074 rlUInt32_t esmGrp2Err;
2080 typedef struct rlRfInitComplete
2102 rlUInt32_t calibStatus;
2107 rlUInt32_t calibUpdate;
2113 rlUInt16_t temperature;
2117 rlUInt16_t reserved0;
2123 rlUInt32_t timeStamp;
2127 rlUInt32_t reserved1;
2133 typedef struct rlRfRunTimeCalibReport
2154 rlUInt32_t calibErrorFlag;
2160 rlUInt32_t calibUpdateStatus;
2166 rlInt16_t temperature;
2170 rlUInt16_t reserved0;
2176 rlUInt32_t timeStamp;
2180 rlUInt32_t reserved1;
2192 typedef struct rlMonTypeTrigDoneStatus
2194 #ifndef MMWL_BIG_ENDIAN 2203 rlUInt8_t monTrigTypeDone;
2207 rlUInt8_t reserved0;
2212 rlUInt8_t reserved0;
2221 rlUInt8_t monTrigTypeDone;
2226 rlUInt16_t reserved1;
2231 rlUInt32_t timeStamp;
2235 rlUInt32_t reserved2;
2241 typedef struct rlRfApllCalDone
2243 rlUInt16_t apllClCalStatus;
2247 rlUInt16_t cccTolerance;
2251 rlUInt16_t cccCount0;
2255 rlUInt16_t measFreqCount;
2259 rlUInt32_t cccCount1;
2270 typedef struct rlCpuFault
2272 #ifndef MMWL_BIG_ENDIAN 2284 rlUInt8_t faultType;
2301 rlUInt8_t errorCode;
2319 rlUInt8_t errorCode;
2331 rlUInt8_t faultType;
2348 rlUInt32_t faultPrevLR;
2353 rlUInt32_t faultSpsr;
2362 rlUInt32_t faultAddr;
2375 rlUInt16_t faultErrStatus;
2376 #ifndef MMWL_BIG_ENDIAN 2383 rlUInt8_t faultErrSrc;
2389 rlUInt8_t faultAxiErrType;
2395 rlUInt8_t faultAccType;
2402 rlUInt8_t faultRecovType;
2409 rlUInt8_t faultAxiErrType;
2416 rlUInt8_t faultErrSrc;
2423 rlUInt8_t faultRecovType;
2429 rlUInt8_t faultAccType;
2434 rlUInt16_t reserved1;
2440 typedef struct rlFwVersionParam
2442 #ifndef MMWL_BIG_ENDIAN 2446 rlUInt8_t hwVarient;
2486 rlUInt8_t patchMajor;
2490 rlUInt8_t patchMinor;
2494 rlUInt8_t patchYear;
2498 rlUInt8_t patchMonth;
2508 rlUInt8_t patchBuildDebug;
2517 rlUInt8_t hwVarient;
2553 rlUInt8_t patchMinor;
2557 rlUInt8_t patchMajor;
2561 rlUInt8_t patchMonth;
2565 rlUInt8_t patchYear;
2571 rlUInt8_t patchBuildDebug;
2582 typedef struct rlSwVersionParam
2584 #ifndef MMWL_BIG_ENDIAN 2656 typedef struct rlVersion
2675 typedef struct rlGpAdcData
2694 typedef struct rlRecvdGpAdcData
2703 rlUInt16_t reserved0[4U];
2707 rlUInt32_t reserved1[7U];
2713 typedef struct rlAnalogFaultReportData
2715 #ifndef MMWL_BIG_ENDIAN 2723 rlUInt8_t faultType;
2727 rlUInt8_t reserved0;
2732 rlUInt8_t reserved0;
2740 rlUInt8_t faultType;
2745 rlUInt16_t reserved1;
2755 rlUInt32_t faultSig;
2759 rlUInt32_t reserved2;
2766 typedef struct rlCalMonTimingErrorReportData
2780 rlUInt16_t timingFailCode;
2781 rlUInt16_t reserved;
2787 typedef struct rlDigLatentFaultReportData
2820 rlUInt32_t digMonLatentFault;
2827 typedef struct rlMonReportHdrData
2832 rlUInt32_t fttiCount;
2841 rlUInt16_t reserved0;
2845 rlUInt32_t reserved1;
2852 typedef struct rlDigPeriodicReportData
2863 rlUInt32_t digMonPeriodicStatus;
2869 rlUInt32_t timeStamp;
2878 typedef struct rlMonTempReportData
2892 rlUInt16_t statusFlags;
2896 rlUInt16_t errorCode;
2914 rlInt16_t tempValues[10U];
2918 rlUInt32_t reserved;
2924 rlUInt32_t timeStamp;
2934 typedef struct rlMonRxGainPhRep
2947 rlUInt16_t statusFlags;
2951 rlUInt16_t errorCode;
2952 #ifndef MMWL_BIG_ENDIAN 2956 rlUInt8_t profIndex;
2967 rlUInt8_t loopbackPowerRF1;
2979 rlUInt8_t loopbackPowerRF2;
2990 rlUInt8_t loopbackPowerRF3;
3002 rlUInt8_t loopbackPowerRF1;
3006 rlUInt8_t profIndex;
3017 rlUInt8_t loopbackPowerRF3;
3028 rlUInt8_t loopbackPowerRF2;
3056 rlUInt16_t rxGainVal[12U];
3071 rlUInt16_t rxPhaseVal[12U];
3094 rlUInt32_t rxNoisePower1;
3117 rlUInt32_t rxNoisePower2;
3123 rlUInt32_t timeStamp;
3133 typedef struct rlMonRxNoiseFigRep
3143 rlUInt16_t statusFlags;
3147 rlUInt16_t errorCode;
3148 #ifndef MMWL_BIG_ENDIAN 3152 rlUInt8_t profIndex;
3156 rlUInt8_t reserved0;
3161 rlUInt8_t reserved0;
3165 rlUInt8_t profIndex;
3170 rlUInt16_t reserved1;
3184 rlUInt16_t rxNoiseFigVal[12U];
3188 rlUInt32_t reserved2;
3192 rlUInt32_t reserved3;
3196 rlUInt32_t reserved4;
3202 rlUInt32_t timeStamp;
3211 typedef struct rlMonRxIfStageRep
3223 rlUInt16_t statusFlags;
3227 rlUInt16_t errorCode;
3228 #ifndef MMWL_BIG_ENDIAN 3232 rlUInt8_t profIndex;
3236 rlUInt8_t reserved0;
3241 rlUInt8_t reserved0;
3245 rlUInt8_t profIndex;
3257 rlInt16_t lpfCutOffBandEdgeDroopValRx0;
3258 #ifndef MMWL_BIG_ENDIAN 3275 rlInt8_t hpfCutOffFreqEr[8U];
3289 rlInt8_t lpfCutOffStopBandAtten[8U];
3303 rlInt8_t rxIfaGainErVal[8U];
3312 rlUInt8_t reserved2;
3325 rlInt8_t lpfCutOffBandEdgeDroopValRx[6U];
3343 rlInt8_t hpfCutOffFreqEr[8U];
3357 rlInt8_t lpfCutOffStopBandAtten[8U];
3371 rlInt8_t rxIfaGainErVal[8U];
3375 rlUInt8_t reserved2;
3393 rlInt8_t lpfCutOffBandEdgeDroopValRx[6U];
3399 rlUInt32_t timeStamp;
3409 typedef struct rlMonTxPowRep
3420 rlUInt16_t statusFlags;
3424 rlUInt16_t errorCode;
3425 #ifndef MMWL_BIG_ENDIAN 3429 rlUInt8_t profIndex;
3433 rlUInt8_t reserved0;
3438 rlUInt8_t reserved0;
3442 rlUInt8_t profIndex;
3447 rlUInt16_t reserved1;
3459 rlInt16_t txPowVal[3U];
3463 rlUInt16_t reserved2;
3469 rlUInt32_t timeStamp;
3480 typedef struct rlMonTxBallBreakRep
3490 rlUInt16_t statusFlags;
3494 rlUInt16_t errorCode;
3499 rlInt16_t txReflCoefVal;
3503 rlUInt16_t reserved0;
3507 rlUInt32_t reserved1;
3513 rlUInt32_t timeStamp;
3522 typedef struct rlMonTxGainPhaMisRep
3533 rlUInt16_t statusFlags;
3537 rlUInt16_t errorCode;
3538 #ifndef MMWL_BIG_ENDIAN 3542 rlUInt8_t profIndex;
3546 rlUInt8_t noisePower00;
3550 rlUInt8_t noisePower01;
3554 rlUInt8_t noisePower02;
3559 rlUInt8_t noisePower00;
3563 rlUInt8_t profIndex;
3567 rlUInt8_t noisePower02;
3571 rlUInt8_t noisePower01;
3585 rlInt16_t txGainVal[9U];
3599 rlUInt16_t txPhaVal[9U];
3600 #ifndef MMWL_BIG_ENDIAN 3604 rlUInt8_t noisePower10;
3608 rlUInt8_t noisePower11;
3612 rlUInt8_t noisePower12;
3616 rlUInt8_t noisePower20;
3620 rlUInt8_t noisePower21;
3624 rlUInt8_t noisePower22;
3628 rlUInt8_t reserved0;
3632 rlUInt8_t reserved1;
3637 rlUInt8_t noisePower11;
3641 rlUInt8_t noisePower10;
3645 rlUInt8_t noisePower20;
3649 rlUInt8_t noisePower12;
3653 rlUInt8_t noisePower22;
3657 rlUInt8_t noisePower21;
3661 rlUInt8_t reserved1;
3665 rlUInt8_t reserved0;
3671 rlUInt32_t timeStamp;
3681 typedef struct rlMonTxPhShiftRep
3692 rlUInt16_t statusFlags;
3696 rlUInt16_t errorCode;
3697 #ifndef MMWL_BIG_ENDIAN 3701 rlUInt8_t profIndex;
3705 rlUInt8_t reserved0;
3710 rlUInt8_t reserved0;
3714 rlUInt8_t profIndex;
3719 rlUInt16_t reserved1;
3725 rlUInt16_t phaseShifterMonVal1;
3731 rlUInt16_t phaseShifterMonVal2;
3737 rlUInt16_t phaseShifterMonVal3;
3743 rlUInt16_t phaseShifterMonVal4;
3749 rlInt16_t txPsAmplitudeVal1;
3755 rlInt16_t txPsAmplitudeVal2;
3761 rlInt16_t txPsAmplitudeVal3;
3767 rlInt16_t txPsAmplitudeVal4;
3768 #ifndef MMWL_BIG_ENDIAN 3774 rlInt8_t txPsNoiseVal1;
3780 rlInt8_t txPsNoiseVal2;
3786 rlInt8_t txPsNoiseVal3;
3792 rlInt8_t txPsNoiseVal4;
3799 rlInt8_t txPsNoiseVal2;
3805 rlInt8_t txPsNoiseVal1;
3811 rlInt8_t txPsNoiseVal4;
3817 rlInt8_t txPsNoiseVal3;
3824 rlUInt32_t timeStamp;
3828 rlUInt32_t reserved2;
3832 rlUInt32_t reserved3;
3841 typedef struct rlMonSynthFreqRep
3851 rlUInt16_t statusFlags;
3855 rlUInt16_t errorCode;
3856 #ifndef MMWL_BIG_ENDIAN 3860 rlUInt8_t profIndex;
3864 rlUInt8_t reserved0;
3869 rlUInt8_t reserved0;
3873 rlUInt8_t profIndex;
3878 rlUInt16_t reserved1;
3886 rlInt32_t maxFreqErVal;
3896 rlUInt32_t freqFailCnt;
3900 rlUInt32_t reserved2;
3904 rlUInt32_t reserved3;
3910 rlUInt32_t timeStamp;
3919 typedef struct rlMonExtAnaSigRep
3934 rlUInt16_t statusFlags;
3938 rlUInt16_t errorCode;
3950 rlInt16_t extAnaSigVal[6U];
3954 rlUInt32_t reserved;
3960 rlUInt32_t timeStamp;
3969 typedef struct rlMonTxIntAnaSigRep
3980 rlUInt16_t statusFlags;
3984 rlUInt16_t errorCode;
3985 #ifndef MMWL_BIG_ENDIAN 3989 rlUInt8_t profIndex;
3993 rlUInt8_t reserved0;
3998 rlUInt8_t phShiftDacIdeltaMin;
4003 rlUInt8_t phShiftDacQdeltaMin;
4008 rlUInt8_t reserved0;
4012 rlUInt8_t profIndex;
4017 rlUInt8_t phShiftDacQdeltaMin;
4022 rlUInt8_t phShiftDacIdeltaMin;
4029 rlUInt32_t timeStamp;
4038 typedef struct rlMonRxIntAnaSigRep
4055 rlUInt16_t statusFlags;
4059 rlUInt16_t errorCode;
4060 #ifndef MMWL_BIG_ENDIAN 4064 rlUInt8_t profIndex;
4068 rlUInt8_t reserved0;
4073 rlUInt8_t reserved0;
4077 rlUInt8_t profIndex;
4082 rlUInt16_t reserved1;
4088 rlUInt32_t timeStamp;
4097 typedef struct rlMonPmclkloIntAnaSigRep
4111 rlUInt16_t statusFlags;
4115 rlUInt16_t errorCode;
4116 #ifndef MMWL_BIG_ENDIAN 4120 rlUInt8_t profIndex;
4126 rlInt8_t sync20GPower;
4133 rlInt8_t sync20GPower;
4137 rlUInt8_t profIndex;
4142 rlUInt16_t reserved;
4148 rlUInt32_t timeStamp;
4158 typedef struct rlMonGpadcIntAnaSigRep
4169 rlUInt16_t statusFlags;
4173 rlUInt16_t errorCode;
4179 rlInt16_t gpadcRef1Val;
4185 rlUInt16_t gpadcRef2Val;
4189 rlUInt32_t reserved;
4195 rlUInt32_t timeStamp;
4204 typedef struct rlMonPllConVoltRep
4220 rlUInt16_t statusFlags;
4224 rlUInt16_t errorCode;
4245 rlInt16_t pllContVoltVal[8U];
4249 rlUInt32_t reserved;
4255 rlUInt32_t timeStamp;
4264 typedef struct rlMonDccClkFreqRep
4278 rlUInt16_t statusFlags;
4282 rlUInt16_t errorCode;
4296 rlUInt16_t freqMeasVal[8U];
4300 rlUInt32_t reserved;
4306 rlUInt32_t timeStamp;
4316 typedef struct rlMonRxMixrInPwrRep
4329 rlUInt16_t statusFlags;
4333 rlUInt16_t errorCode;
4335 #ifndef MMWL_BIG_ENDIAN 4339 rlUInt8_t profIndex;
4343 rlUInt8_t reserved0;
4348 rlUInt8_t reserved0;
4352 rlUInt8_t profIndex;
4357 rlUInt16_t reserved1;
4370 rlUInt32_t rxMixInVolt;
4374 rlUInt32_t reserved2;
4379 rlUInt32_t timeStamp;
4389 typedef struct rlMonSynthFreqNonLiveRep
4400 rlUInt16_t statusFlags;
4404 rlUInt16_t errorCode;
4406 #ifndef MMWL_BIG_ENDIAN 4410 rlUInt8_t profIndex0;
4414 rlUInt8_t reserved0;
4419 rlUInt8_t reserved0;
4423 rlUInt8_t profIndex0;
4428 rlUInt16_t reserved1;
4436 rlInt32_t maxFreqErVal0;
4446 rlUInt32_t freqFailCnt0;
4452 rlUInt32_t maxFreqFailTime0;
4456 rlUInt32_t reserved2;
4458 #ifndef MMWL_BIG_ENDIAN 4462 rlUInt8_t profIndex1;
4466 rlUInt8_t reserved3;
4471 rlUInt8_t reserved3;
4475 rlUInt8_t profIndex1;
4480 rlUInt16_t reserved4;
4488 rlInt32_t maxFreqErVal1;
4498 rlUInt32_t freqFailCnt1;
4504 rlUInt32_t maxFreqFailTime1;
4508 rlUInt32_t reserved5;
4514 rlUInt32_t timeStamp;
4526 typedef struct rlMmwlErrorStatus
4531 #include <ti/control/mmwavelink/include/rl_device.h> 4532 #include <ti/control/mmwavelink/include/rl_sensor.h> 4533 #include <ti/control/mmwavelink/include/rl_monitoring.h> 4534 #include <ti/control/mmwavelink/include/rl_protocol.h> 4535 #include <ti/control/mmwavelink/include/rl_messages.h> This is the Monitoring report which RadarSS sends to the host, containing information about the relat...
mmWaveLink RF Run time calibration report for event RL_RF_AE_RUN_TIME_CALIB_REPORT_SB
This async event is sent periodically to indicate the status of periodic digital monitoring tests....
mmWaveLink client callback structure
This is the Monitoring report which RadarSS sends to the host, containing the measured RX noise figur...
mmWaveLink RF Init Complete data structure for event RL_RF_AE_INITCALIBSTATUS_SB
Sensors GPADC measurement data for event RL_RF_AE_GPADC_MEAS_DATA_SB.
Structure to hold the BSS ESM Fault data strucutre for event RL_RF_AE_ESMFAULT_SB.
mmWaveLink firmware version structure
Structure to hold the test status report of the latent fault tests data strucutre for event RL_DEV_AE...
mmWaveLink Report for event RL_RF_AE_MONITOR_TYPE_TRIGGER_DONE_SB. The triggered monitor types are do...
Communication interface(SPI, MailBox, UART etc) callback functions.
mmWaveLink CRC callback function
Calibration monitoring timing error data for event RL_RF_AE_MON_TIMING_FAIL_REPORT_SB.
This is the Monitoring report which RadarSS sends to the host, containing the measured temperature ne...
mmWaveLink Init Complete data structure for event RL_DEV_AE_MSSPOWERUPDONE_SB
This is the Monitoring report which RadarSS sends to the host, containing information about Internal ...
This API is a Monitoring report which RadarSS sends to the host, containing the measured RX gain and ...
This is an error status report internally generated from mmWaveLink when it finds any issue with the ...
This is the Monitoring report which RadarSS sends to the host, containing the measured TX reflection ...
This is the Monitoring report which RadarSS sends to the host, containing information about the measu...
This is the Monitoring report which the AWR device sends to the host, containing the measured TX phas...
OS semaphore callback functions.
mmWaveLink Device Control, Interrupt callback functions
This is the Monitoring report which RadarSS sends to the host, containing information related to meas...
mmWaveLink Timer callback functions
mmWaveLink debug callback structure
Analog fault strucure for event RL_RF_AE_ANALOG_FAULT_SB.
This is the Monitoring report which RadarSS sends to the host, containing the measured Tx gain and ph...
API APLL closed loop cal Status Get Sub block structure.
This is the Monitoring report which RadarSS sends to the host, containing information about Internal ...
This is the Monitoring report which RadarSS sends to the host, containing information about Internal ...
Structure to hold data strucutre for RF-error status send by MSS for event RL_DEV_AE_MSS_RF_ERROR_STA...
Latent fault digital monitoring status data for event RL_RF_AE_DIG_LATENTFAULT_REPORT_AE_SB.
This is the Monitoring report which RadarSS sends to the host, containing the measured PLL control vo...
GPADC measurement data for sensors.
This is a Non live Monitoring report which device sends to the host, containing information related t...
This is the Monitoring report which the xWR device sends to the host, containing the measured RX mixe...
Structure to hold the MSS Boot error status data strucutre when booted over SPI for event RL_DEV_AE_M...
Structure to hold the MSS ESM Fault data structure for event RL_DEV_AE_MSS_ESMFAULT_SB.
The report header includes common information across all enabled monitors like current FTTI number an...
mmwavelink software version structure
mmWaveLink callback functions for Command parser
OS mutex callback functions.
This is the Monitoring report which RadarSS sends to the host, containing the external signal voltage...
Structure to hold the MSS/radarSS CPU Fault data strucutre for event RL_DEV_AE_MSS_CPUFAULT_SB and RL...
mmwavelink version structure
Structure to hold data strucutre for test status of the periodic tests for event RL_DEV_AE_MSS_PERIOD...
mmWaveLink RF Start Complete data structure for event RL_DEV_AE_RFPOWERUPDONE_SB
mmWaveLink Asynchronous event callback function
This is the Monitoring report which RadarSS sends to the host, containing the measured RX IF filter a...
OS message queue/Spawn callback functions.
This is the Monitoring report which RadarSS sends to the host, containing the measured TX power value...
OS services callback functions.