Data Fields
rlCpuFault_t Struct Reference

Structure to hold the MSS/radarSS CPU Fault data strucutre for event RL_DEV_AE_MSS_CPUFAULT_SB and RL_RF_AE_CPUFAULT_SB. More...

#include <control/mmwavelink/mmwavelink.h>

Data Fields

rlUInt8_t faultType
 0x0 MSS/RF Processor Undefined Instruction Abort
0x1 MSS/RF Processor Instruction pre-fetch Abort
0x2 MSS/RF Processor Data Access Abort
0x3 MSS/RF Processor Firmware Fatal Error
0x4 MSS Processor Chirp Errors
0x5 MSS Processor Register Read-Back Error
0x6 - 0xFE Reserved
0xFF No Fault
More...
 
rlUInt8_t errorCode
 The error code for the fault occurred. The error code is defined only for few fatal errors generated either due to wrong configuration of the device or HW limitation.
Error code Definition
0 Undefined error code
1 Rampgen is not triggered from FRC or Hw pulse (FRC is running)
2 Burst start and end counts are not matching in rampgen
3 Chirp start and end counts are not matching in rampgen
4 Calibration/Monitoring chirps not finished at pre burst
5 RadarSS TX mailbox queue full
6 Sequencer extension copy error for a chirp
7 Temperature sensor data is invalid
8 Test source configuration time failure
Others Reserved
. More...
 
rlUInt16_t lineNum
 Valid only in case of FAULT type is 0x3, provides the source
line number at which fatal error occurred.
.
 
rlUInt32_t faultLR
 The instruction PC address at which Fault occurred in case FAULT_TYPE is 0x0-0x3
The register address in case FAULT_TYPE is 0x5
.
 
rlUInt32_t faultPrevLR
 The return address of the function from which fault function
has been called (Call stack LR) in case FAULT_TYPE is 0x0-0x3
The register read-back value in case FAULT_TYPE is 0x5
.
 
rlUInt32_t faultSpsr
 The CPSR register value at which fault occurred in case FAULT_TYPE is 0x0-0x3
The register write value in case FAULT_TYPE is 0x5
.
 
rlUInt32_t faultSp
 The SP register value at which fault occurred.
 
rlUInt32_t faultAddr
 The address access at which Fault occurred (valid only for fault
type 0x0 to 0x2)
.
 
rlUInt16_t faultErrStatus
 The status of Error (Error Cause type - valid only for
fault type 0x0 to 0x2)
0x000 BACKGROUND_ERR
0x001 ALIGNMENT_ERR
0x002 DEBUG_EVENT
0x00D PERMISSION_ERR
0x008 SYNCH_EXTER_ERR
0x406 ASYNCH_EXTER_ERR
0x409 SYNCH_ECC_ERR
0x408 ASYNCH_ECC_ERR
.
 
rlUInt8_t faultErrSrc
 The Source of the Error (Error Source type- valid only for fault type 0x0 to 0x2)
0x0 ERR_SOURCE_AXI_MASTER
0x1 ERR_SOURCE_ATCM
0x2 ERR_SOURCE_BTCM
.
 
rlUInt8_t faultAxiErrType
 The AXI Error type (Error Source type - valid only for fault type 0x0 to 0x2)
0x0 AXI_DECOD_ERR
0x1 AXI_SLAVE_ERR
.
 
rlUInt8_t faultAccType
 The Error Access type (Error Access type- valid only for fault type 0x0 to 0x2)
0x0 READ_ERR
0x1 WRITE_ERR
.
 
rlUInt8_t faultRecovType
 The Error Recovery type (Error Recovery type - Valid only for fault
type 0x0 to 0x2)
0x0 UNRECOVERY
0x1 RECOVERY
.
 
rlUInt16_t reserved1
 Reserved for future use.
 

Detailed Description

Structure to hold the MSS/radarSS CPU Fault data strucutre for event RL_DEV_AE_MSS_CPUFAULT_SB and RL_RF_AE_CPUFAULT_SB.

Note
: All the Monitoring Async events will be sent out periodically at calibMonTimeUnit frame rate (FTTI). The RadarSS/BSS has a queue to hold max 8 transmit API messages (AEs or Responses), the host shall service all the AEs before start of the next FTTI epoch to avoid RadarSS Queue full CPU fault fatal error.

Definition at line 2273 of file mmwavelink.h.

Field Documentation

◆ errorCode

rlUInt8_t rlCpuFault_t::errorCode

The error code for the fault occurred. The error code is defined only for few fatal errors generated either due to wrong configuration of the device or HW limitation.
Error code Definition
0 Undefined error code
1 Rampgen is not triggered from FRC or Hw pulse (FRC is running)
2 Burst start and end counts are not matching in rampgen
3 Chirp start and end counts are not matching in rampgen
4 Calibration/Monitoring chirps not finished at pre burst
5 RadarSS TX mailbox queue full
6 Sequencer extension copy error for a chirp
7 Temperature sensor data is invalid
8 Test source configuration time failure
Others Reserved
.

Note
: This field is RESERVED for RL_DEV_AE_MSS_CPUFAULT_SB event

Definition at line 2304 of file mmwavelink.h.

◆ faultType

rlUInt8_t rlCpuFault_t::faultType

0x0 MSS/RF Processor Undefined Instruction Abort
0x1 MSS/RF Processor Instruction pre-fetch Abort
0x2 MSS/RF Processor Data Access Abort
0x3 MSS/RF Processor Firmware Fatal Error
0x4 MSS Processor Chirp Errors
0x5 MSS Processor Register Read-Back Error
0x6 - 0xFE Reserved
0xFF No Fault

Note
: Values of 4 and 5 is valid only for RL_DEV_AE_MSS_CPUFAULT_SB event

Definition at line 2287 of file mmwavelink.h.


The documentation for this struct was generated from the following file:

Copyright 2020, Texas Instruments Incorporated