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API RF device Config SBC M_API_AR_RF_DEV_CONF_SBC. More...
#include <control/mmwavelink/include/rl_sensor.h>
Data Fields | |
rlUInt32_t | aeDirection |
Bit Definition b1:0 Global Async event direction 00 - radarSS to MSS 01 - radarSS to HOST 10 - radarSS to DSS 11 - RESERVED The ASYNC_EVENT_DIR controls the direction for following ASYNC_EVENTS [1.] CPU_FAULT [2.] ESM_FAULT [3.] ANALOG_FAULT All other ASYNC_EVENTs are sent to the subsystem which issues the API b3:2 Monitoring Async Event direction 00 - radarSS to MSS 01 - radarSS to HOST 10 - radarSS to DSS 11 - RESERVED b31:4 Reserved. | |
rlUInt8_t | aeControl |
Bit Definition b0: FRAME_START_ASYNC_EVENT_DIS 0 Frame Start async event enable 1 Frame Start async event disable b1: FRAME_STOP_ASYNC_EVENT_DIS 0 Frame Stop async event enable 1 Frame Stop async event disable b7:2 Reserved. | |
rlUInt8_t | bssAnaControl |
Bit Definition b0 INTER_BURST_POWER_SAVE_DIS 0 Inter burst power save enable (default) 1 Inter burst power save disable Default value: 0 This allows to disable inter burst power save feature for individual bursts in a advance frame config API to reduce inter-burst idle time requirement. The power save is done always in inter sub-frame and frame boundaries irrespective of this control bit configuration. The inter burst power save needs 55us burst idle time, please refer Table interBurstTime for more details on inter burst time. b7:1 Reserved . More... | |
rlUInt8_t | reserved1 |
Reserved for Future use. | |
rlUInt8_t | bssDigCtrl |
Bit Definition b0: Watchdog enable/disable 0 Keep watchdog disabled 1 Enable watch dog b7:1: Reserved . More... | |
rlUInt8_t | aeCrcConfig |
CRC Config for Asynchornous event message Value Description 0 16 bit CRC for radarSS async events 1 32 bit CRC for radarSS async events 2 64 bit CRC for radarSS async events . More... | |
rlUInt8_t | reserved2 |
Reserved for Future use. | |
rlUInt16_t | reserved3 |
Reserved for Future use. | |
API RF device Config SBC M_API_AR_RF_DEV_CONF_SBC.
Definition at line 1850 of file rl_sensor.h.
rlUInt8_t rlRfDevCfg_t::aeCrcConfig |
CRC Config for Asynchornous event message
Value Description
0 16 bit CRC for radarSS async events
1 32 bit CRC for radarSS async events
2 64 bit CRC for radarSS async events
.
Definition at line 1917 of file rl_sensor.h.
rlUInt8_t rlRfDevCfg_t::bssAnaControl |
Bit Definition
b0 INTER_BURST_POWER_SAVE_DIS
0 Inter burst power save enable (default)
1 Inter burst power save disable
Default value: 0 This allows to disable inter burst power save feature for individual bursts in a advance frame config API to reduce inter-burst idle time requirement. The power save is done always in inter sub-frame and frame boundaries irrespective of this control bit configuration.
The inter burst power save needs 55us burst idle time, please refer Table interBurstTime for more details on inter burst time.
b7:1 Reserved
.
Definition at line 1892 of file rl_sensor.h.
rlUInt8_t rlRfDevCfg_t::bssDigCtrl |
Bit Definition
b0: Watchdog enable/disable
0 Keep watchdog disabled
1 Enable watch dog
b7:1: Reserved
.
Definition at line 1908 of file rl_sensor.h.