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LVDS Lane configuration. More...
#include <control/mmwavelink/include/rl_device.h>
Data Fields | |
rlUInt16_t | laneFmtMap |
Lane format 0x0000 Format map 0 (Rx0,Rx1,...) 0x0001 Format map 1 (Rx3,Rx2,...) . | |
rlUInt16_t | laneParamCfg |
Lane Parameter configurations b0 - 0(LSB first), 1(MSB first) b1 - 0(Packet End Pulse Disable), 1(enable) b2 - 0(CRC disabled), 1(CRC enabled) b7:3 - Reserved b8 - Configures LSB/MSB first for CRC 0(CRC value swapped wrt to MSB_FIRST setting) 1(CRC value follows MSB_FIRST setting) b9 - Frame clock state during idle 0(Frame clock is held low) 1(Frame clock is held high) b10 - Frame clock period for CRC(when CRC enabled - b2) 0(32-bit CRC is trasmitted as single sample with frame clock set to 16high, 16low configuration) 1(32-bit CRC is trasmitted as single sample with frame clock set to 8high, 8low configuration) b11 - Bit clock state during idle 0(Bit clock toggles during idle when there are no transmission) 1(Bit clock doesn't toggle during idle when there are no transmission, the value of bit clock is held low) b12 - CRC inversion control(when CRC enabled - b2) 0(The calcualted value of 32-bit ethernet polynomial CRC is inverted and sent out) 1(The calcualted value of 32-bit ethernet polynomial CRC is sent without inversion) b15:13 - Reserved . | |
LVDS Lane configuration.
Definition at line 883 of file rl_device.h.