rl_monitoring.h
1 /****************************************************************************************
2  * FileName : rl_monitoring.h
3  *
4  * Description : This file defines the functions required for Monitoring.
5  *
6  ****************************************************************************************
7  * (C) Copyright 2014, Texas Instruments Incorporated. - TI web address www.ti.com
8  *---------------------------------------------------------------------------------------
9  *
10  * Redistribution and use in source and binary forms, with or without modification,
11  * are permitted provided that the following conditions are met:
12  *
13  * Redistributions of source code must retain the above copyright notice,
14  * this list of conditions and the following disclaimer.
15  *
16  * Redistributions in binary form must reproduce the above copyright notice,
17  * this list of conditions and the following disclaimer in the documentation
18  * and/or other materials provided with the distribution.
19  *
20  * Neither the name of Texas Instruments Incorporated nor the names of its
21  * contributors may be used to endorse or promote products derived from this
22  * software without specific prior written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
28  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34  * POSSIBILITY OF SUCH DAMAGE.
35  */
36 
37 /****************************************************************************************
38  * FILE INCLUSION PROTECTION
39  ****************************************************************************************
40  */
41 #ifndef RL_MONITORING_H
42 #define RL_MONITORING_H
43 
44 /******************************************************************************
45  * INCLUDE FILES
46  ******************************************************************************
47  */
48 
49 #ifdef __cplusplus
50 extern "C" {
51 #endif
52 
56 #define RL_MON_RF_FREQ_CNT (3U)
57 
61 #define RL_NUM_MON_SLICES_MAX (127U)
62 
63 
64 /******************************************************************************
65  * GLOBAL VARIABLES/DATA-TYPES DEFINITIONS
66  ******************************************************************************
67  */
68 
72 typedef struct rlMonDigEnables
73 {
104  rlUInt32_t enMask;
105 #ifndef MMWL_BIG_ENDIAN
106 
112  rlUInt8_t testMode;
116  rlUInt8_t reserved0;
117 #else
118 
121  rlUInt8_t reserved0;
131  rlUInt8_t testMode;
132 #endif
133 
136  rlUInt16_t reserved1;
140  rlUInt32_t reserved2;
142 
146 typedef struct rlDigMonPeriodicConf
147 {
148 #ifndef MMWL_BIG_ENDIAN
149 
155  rlUInt8_t reportMode;
159  rlUInt8_t reserved0;
160 #else
161 
164  rlUInt8_t reserved0;
171  rlUInt8_t reportMode;
172 #endif
173 
176  rlUInt16_t reserved1;
185  rlUInt32_t periodicEnableMask;
189  rlUInt32_t reserved2;
191 
195 typedef struct rlMonAnaEnables
196 {
230  rlUInt32_t enMask;
246  rlUInt32_t ldoVmonScEn;
248 
252 typedef struct rlTempMonConf
253 {
254 #ifndef MMWL_BIG_ENDIAN
255 
261  rlUInt8_t reportMode;
265  rlUInt8_t reserved0;
266 #else
267 
270  rlUInt8_t reserved0;
277  rlUInt8_t reportMode;
278 #endif
279 
287  rlInt16_t anaTempThreshMin;
296  rlInt16_t anaTempThreshMax;
305  rlInt16_t digTempThreshMin;
314  rlInt16_t digTempThreshMax;
323  rlUInt16_t tempDiffThresh;
327  rlUInt32_t reserved1;
331  rlUInt32_t reserved2;
333 
337 typedef struct rlRxGainPhaseMonConf
338 {
339 #ifndef MMWL_BIG_ENDIAN
340 
343  rlUInt8_t profileIndx;
359  rlUInt8_t rfFreqBitMask;
369  rlUInt8_t reportMode;
375  rlUInt8_t txSel;
376 #else
377 
392  rlUInt8_t rfFreqBitMask;
396  rlUInt8_t profileIndx;
402  rlUInt8_t txSel;
412  rlUInt8_t reportMode;
413 #endif
414 
424  rlUInt16_t rxGainAbsThresh;
475  rlInt16_t rxGainMismatchOffsetVal[RL_RX_CNT][RL_MON_RF_FREQ_CNT];
489  rlUInt16_t rxGainPhaseMismatchOffsetVal[RL_RX_CNT][RL_MON_RF_FREQ_CNT];
493  rlUInt32_t reserved0;
497  rlUInt32_t reserved1;
499 
503 typedef struct rlRxNoiseMonConf
504 {
505 #ifndef MMWL_BIG_ENDIAN
506 
509  rlUInt8_t profileIndx;
525  rlUInt8_t rfFreqBitMask;
526 #else
527 
542  rlUInt8_t rfFreqBitMask;
546  rlUInt8_t profileIndx;
547 #endif
548 
551  rlUInt16_t reserved0;
552 #ifndef MMWL_BIG_ENDIAN
553 
559  rlUInt8_t reportMode;
563  rlUInt8_t reserved1;
564 #else
565 
568  rlUInt8_t reserved1;
575  rlUInt8_t reportMode;
576 #endif
577 
585  rlUInt16_t noiseThresh;
589  rlUInt32_t reserved2;
591 
595 typedef struct rlRxIfStageMonConf
596 {
597 #ifndef MMWL_BIG_ENDIAN
598 
601  rlUInt8_t profileIndx;
608  rlUInt8_t reportMode;
609 #else
610 
616  rlUInt8_t reportMode;
620  rlUInt8_t profileIndx;
621 #endif
622 
625  rlUInt16_t reserved0;
629  rlUInt16_t reserved1;
638  rlUInt16_t hpfCutoffErrThresh;
639 #ifndef MMWL_BIG_ENDIAN
640 
661 #else
662 
672  rlUInt8_t lpfCutoffStopBandAttenThresh;
682  rlUInt8_t lpfCutoffBandEdgeDroopThresh;
683 #endif
684 
693  rlUInt16_t ifaGainErrThresh;
697  rlUInt32_t reserved2;
699 
703 typedef struct rlTxPowMonConf
704 {
705 #ifndef MMWL_BIG_ENDIAN
706 
709  rlUInt8_t profileIndx;
726  rlUInt8_t rfFreqBitMask;
727 #else
728 
744  rlUInt8_t rfFreqBitMask;
748  rlUInt8_t profileIndx;
749 #endif
750 
753  rlUInt16_t reserved0;
754 #ifndef MMWL_BIG_ENDIAN
755 
760  rlUInt8_t reportMode;
764  rlUInt8_t reserved1;
765 #else
766 
769  rlUInt8_t reserved1;
775  rlUInt8_t reportMode;
776 #endif
777 
785  rlUInt16_t txPowAbsErrThresh;
800  rlUInt16_t reserved2;
804  rlUInt32_t reserved3;
806 
807 
811 typedef struct rlAllTxPowMonConf
812 {
826 
830 typedef struct rlTxBallbreakMonConf
831 {
832 #ifndef MMWL_BIG_ENDIAN
833 
839  rlUInt8_t reportMode;
843  rlUInt8_t reserved0;
844 #else
845 
848  rlUInt8_t reserved0;
855  rlUInt8_t reportMode;
856 #endif
857 
864  rlInt16_t txReflCoeffMagThresh;
868  rlUInt32_t reserved1;
872  rlUInt32_t reserved2;
874 
878 typedef struct rlAllTxBallBreakMonCfg
879 {
893 
897 typedef struct rlTxGainPhaseMismatchMonConf
898 {
899 #ifndef MMWL_BIG_ENDIAN
900 
906  rlUInt8_t profileIndx;
923  rlUInt8_t rfFreqBitMask;
933  rlUInt8_t txEn;
944  rlUInt8_t rxEn;
951  rlUInt8_t reportMode;
967  rlInt8_t monChirpSlope;
968 #else
969 
985  rlUInt8_t rfFreqBitMask;
992  rlUInt8_t profileIndx;
1003  rlUInt8_t rxEn;
1013  rlUInt8_t txEn;
1029  rlInt8_t monChirpSlope;
1036  rlUInt8_t reportMode;
1037 #endif
1038 
1072  rlUInt16_t txGainMismatchOffsetVal[RL_TX_CNT][RL_MON_RF_FREQ_CNT];
1086  rlUInt16_t txPhaseMismatchOffsetVal[RL_TX_CNT][RL_MON_RF_FREQ_CNT];
1090  rlUInt16_t reserved1;
1094  rlUInt32_t reserved2;
1096 
1100 typedef struct rlSynthFreqMonConf
1101 {
1102 #ifndef MMWL_BIG_ENDIAN
1103 
1106  rlUInt8_t profileIndx;
1113  rlUInt8_t reportMode;
1114 #else
1115 
1121  rlUInt8_t reportMode;
1125  rlUInt8_t profileIndx;
1126 #endif
1127 
1136  rlUInt16_t freqErrThresh;
1137 #ifndef MMWL_BIG_ENDIAN
1138 
1145  rlInt8_t monStartTime;
1162  rlUInt8_t monitorMode;
1172  rlUInt8_t vcoMonEn;
1176  rlUInt8_t reserved1;
1177 #else
1178 
1194  rlUInt8_t monitorMode;
1202  rlInt8_t monStartTime;
1206  rlUInt8_t reserved1;
1216  rlUInt8_t vcoMonEn;
1217 #endif
1218 
1221  rlUInt32_t reserved2;
1223 
1227 typedef struct rlExtAnaSignalsMonConf
1228 {
1229 #ifndef MMWL_BIG_ENDIAN
1230 
1236  rlUInt8_t reportMode;
1240  rlUInt8_t reserved0;
1255  rlUInt8_t signalInpEnables;
1290  rlUInt8_t signalSettlingTime[6U];
1312  rlUInt8_t signalThresh[12U];
1313 #else
1314 
1317  rlUInt8_t reserved0;
1324  rlUInt8_t reportMode;
1339  rlUInt8_t signalBuffEnables;
1354  rlUInt8_t signalInpEnables;
1374  rlUInt8_t signalSettlingTime[6U];
1396  rlUInt8_t signalThresh[12U];
1397 #endif
1398 
1401  rlUInt16_t reserved1;
1405  rlUInt32_t reserved2;
1409  rlUInt32_t reserved3;
1411 
1415 typedef struct rlTxIntAnaSignalsMonConf
1416 {
1417 #ifndef MMWL_BIG_ENDIAN
1418 
1423  rlUInt8_t profileIndx;
1430  rlUInt8_t reportMode;
1431 #else
1432 
1438  rlUInt8_t reportMode;
1444  rlUInt8_t profileIndx;
1445 #endif
1446 
1455  rlUInt32_t reserved1;
1457 
1458 
1462 typedef struct rlAllTxIntAnaSignalsMonConf
1463 {
1477 
1478 typedef struct rlRxIntAnaSignalsMonConf
1479 {
1480 #ifndef MMWL_BIG_ENDIAN
1481 
1486  rlUInt8_t profileIndx;
1493  rlUInt8_t reportMode;
1494 #else
1495 
1501  rlUInt8_t reportMode;
1507  rlUInt8_t profileIndx;
1508 #endif
1509 
1512  rlUInt16_t reserved0;
1516  rlUInt32_t reserved1;
1517 } rlRxIntAnaSignalsMonConf_t;
1518 
1522 typedef struct rlPmClkLoIntAnaSignalsMonConf
1523 {
1524 #ifndef MMWL_BIG_ENDIAN
1525 
1530  rlUInt8_t profileIndx;
1537  rlUInt8_t reportMode;
1538 
1547  rlUInt8_t sync20GSigSel;
1548 
1554 
1560 
1564  rlUInt8_t reserved0;
1565 #else
1566 
1572  rlUInt8_t reportMode;
1578  rlUInt8_t profileIndx;
1579 
1584  rlInt8_t sync20GMinThresh;
1585 
1594  rlUInt8_t sync20GSigSel;
1595 
1599  rlUInt8_t reserved0;
1600 
1605  rlInt8_t sync20GMaxThresh;
1606 #endif
1607 
1610  rlUInt16_t reserved1;
1612 
1616 typedef struct rlGpadcIntAnaSignalsMonConf
1617 {
1618 #ifndef MMWL_BIG_ENDIAN
1619 
1625  rlUInt8_t reportMode;
1629  rlUInt8_t reserved0;
1630 #else
1631 
1634  rlUInt8_t reserved0;
1641  rlUInt8_t reportMode;
1642 #endif
1643 
1646  rlUInt16_t reserved1;
1650  rlUInt32_t reserved2;
1652 
1656 typedef struct rlPllContrlVoltMonConf
1657 {
1658 #ifndef MMWL_BIG_ENDIAN
1659 
1665  rlUInt8_t reportMode;
1669  rlUInt8_t reserved0;
1670 #else
1671 
1674  rlUInt8_t reserved0;
1681  rlUInt8_t reportMode;
1682 #endif
1683 
1705  rlUInt16_t signalEnables;
1709  rlUInt32_t reserved1;
1711 
1715 typedef struct rlDualClkCompMonConf
1716 {
1717 #ifndef MMWL_BIG_ENDIAN
1718 
1724  rlUInt8_t reportMode;
1728  rlUInt8_t reserved0;
1729 #else
1730 
1733  rlUInt8_t reserved0;
1740  rlUInt8_t reportMode;
1741 #endif
1742 
1757  rlUInt16_t dccPairEnables;
1761  rlUInt32_t reserved1;
1763 
1767 typedef struct rlRxSatMonConf
1768 {
1769 #ifndef MMWL_BIG_ENDIAN
1770 
1773  rlUInt8_t profileIndx;
1778  rlUInt8_t satMonSel;
1779 #else
1780 
1784  rlUInt8_t satMonSel;
1788  rlUInt8_t profileIndx;
1789 #endif
1790 
1793  rlUInt16_t reserved0;
1826  rlUInt16_t numSlices;
1827 #ifndef MMWL_BIG_ENDIAN
1828 
1837  rlUInt8_t rxChannelMask;
1841  rlUInt8_t reserved1;
1842 #else
1843 
1846  rlUInt8_t reserved1;
1856  rlUInt8_t rxChannelMask;
1857 #endif
1858 
1861  rlUInt16_t reserved2;
1865  rlUInt32_t reserved3;
1869  rlUInt32_t reserved4;
1871 
1875 typedef struct rlSigImgMonConf
1876 {
1877 #ifndef MMWL_BIG_ENDIAN
1878 
1881  rlUInt8_t profileIndx;
1885  rlUInt8_t numSlices;
1886 #else
1887 
1890  rlUInt8_t numSlices;
1894  rlUInt8_t profileIndx;
1895 #endif
1896 
1916  rlUInt32_t reserved0;
1920  rlUInt32_t reserved1;
1922 
1926 typedef struct rlRxMixInPwrMonConf
1927 {
1928 #ifndef MMWL_BIG_ENDIAN
1929 
1934  rlUInt8_t profileIndx;
1942  rlUInt8_t reportMode;
1953  rlUInt8_t txEnable;
1957  rlUInt8_t reserved0;
1958 #else
1959 
1966  rlUInt8_t reportMode;
1972  rlUInt8_t profileIndx;
1976  rlUInt8_t reserved0;
1987  rlUInt8_t txEnable;
1988 #endif
1989 
2001  rlUInt16_t thresholds;
2005  rlUInt16_t reserved1;
2009  rlUInt32_t reserved2;
2011 
2015 typedef struct rlRfSigImgPowerCqData
2016 {
2020  rlUInt16_t numSlices;
2046  rlUInt16_t sigImgPowerCqVal[RL_NUM_MON_SLICES_MAX];
2048 
2052 typedef struct rlRfRxSaturationCqData
2053 {
2057  rlUInt8_t numSlices;
2085  rlUInt8_t satCqVal[RL_NUM_MON_SLICES_MAX];
2087 
2088 typedef struct rlAnaFaultInj
2089 {
2090 #ifndef MMWL_BIG_ENDIAN
2091 
2094  rlUInt8_t reserved0;
2108  rlUInt8_t rxGainDrop;
2121  rlUInt8_t rxPhInv;
2135  rlUInt8_t rxHighNoise;
2152  rlUInt8_t rxIfStagesFault;
2165  rlUInt8_t rxLoAmpFault;
2179  rlUInt8_t txLoAmpFault;
2192  rlUInt8_t txGainDrop;
2211  rlUInt8_t txPhInv;
2228  rlUInt8_t synthFault;
2241  rlUInt8_t supplyLdoFault;
2251  rlUInt8_t miscFault;
2264  rlUInt8_t miscThreshFault;
2268  rlUInt8_t reserved1;
2269 #else
2270 
2283  rlUInt8_t rxGainDrop;
2287  rlUInt8_t reserved0;
2301  rlUInt8_t rxHighNoise;
2314  rlUInt8_t rxPhInv;
2326  rlUInt8_t rxLoAmpFault;
2343  rlUInt8_t rxIfStagesFault;
2356  rlUInt8_t txGainDrop;
2369  rlUInt8_t txLoAmpFault;
2386  rlUInt8_t synthFault;
2405  rlUInt8_t txPhInv;
2415  rlUInt8_t miscFault;
2426  rlUInt8_t supplyLdoFault;
2430  rlUInt8_t reserved1;
2443  rlUInt8_t miscThreshFault;
2444 #endif
2445 
2448  rlUInt16_t reserved2;
2452  rlUInt16_t reserved3;
2456  rlUInt16_t reserved4;
2457 } rlAnaFaultInj_t;
2458 
2462 typedef struct rlTxPhShiftMonConf
2463 {
2464 #ifndef MMWL_BIG_ENDIAN
2465 
2468  rlUInt8_t profileIndx;
2475  rlUInt8_t reportMode;
2476 #else
2477 
2483  rlUInt8_t reportMode;
2487  rlUInt8_t profileIndx;
2488 #endif
2489 
2492  rlUInt16_t reserved0;
2493 #ifndef MMWL_BIG_ENDIAN
2494 
2504  rlUInt8_t phShifterMonCfg;
2516  rlUInt8_t rxEn;
2532  rlInt8_t monChirpSlope;
2536  rlUInt8_t reserved1;
2545  rlUInt8_t phShifterIncVal1;
2554  rlUInt8_t phShifterIncVal2;
2563  rlUInt8_t phShifterIncVal3;
2572  rlUInt8_t phShifterIncVal4;
2580  rlUInt8_t phShifterMon1;
2588  rlUInt8_t phShifterMon2;
2596  rlUInt8_t phShifterMon3;
2604  rlUInt8_t phShifterMon4;
2605 #else
2606 
2617  rlUInt8_t rxEn;
2628  rlUInt8_t phShifterMonCfg;
2632  rlUInt8_t reserved1;
2648  rlInt8_t monChirpSlope;
2657  rlUInt8_t phShifterIncVal2;
2666  rlUInt8_t phShifterIncVal1;
2675  rlUInt8_t phShifterIncVal4;
2684  rlUInt8_t phShifterIncVal3;
2692  rlUInt8_t phShifterMon2;
2700  rlUInt8_t phShifterMon1;
2708  rlUInt8_t phShifterMon4;
2716  rlUInt8_t phShifterMon3;
2717 #endif
2718 
2737  rlUInt16_t txAmplErrorThresh;
2741  rlUInt32_t reserved2;
2745  rlUInt32_t reserved3;
2747 
2751 typedef struct rlAllTxPhShiftMonConf
2752 {
2766 
2842 /******************************************************************************
2843  * FUNCTION DECLARATIONS
2844  ******************************************************************************
2845  */
2846 
2847 /* Digital Monitoring Configuration */
2848 MMWL_EXPORT rlReturnVal_t rlRfDigMonEnableConfig(rlUInt8_t deviceMap,
2849  rlMonDigEnables_t* data);
2850 
2851 /* Digital Monitoring Periodic Configuration */
2852 MMWL_EXPORT rlReturnVal_t rlRfDigMonPeriodicConfig(rlUInt8_t deviceMap,
2853  rlDigMonPeriodicConf_t* data);
2854 /* Analog Monitoring Configuration */
2855 MMWL_EXPORT rlReturnVal_t rlRfAnaMonConfig(rlUInt8_t deviceMap,
2856  rlMonAnaEnables_t* data);
2857 /* TemperatureSsensor Monitoring Configuration */
2858 MMWL_EXPORT rlReturnVal_t rlRfTempMonConfig(rlUInt8_t deviceMap, rlTempMonConf_t* data);
2859 /* RX Gain and Phase Monitoring Configuration */
2860 MMWL_EXPORT rlReturnVal_t rlRfRxGainPhMonConfig(rlUInt8_t deviceMap,
2861  rlRxGainPhaseMonConf_t* data);
2862 /* RX Noise Monitoring Configuration */
2863 MMWL_EXPORT rlReturnVal_t rlRfRxNoiseMonConfig(rlUInt8_t deviceMap,
2864  rlRxNoiseMonConf_t* data);
2865 /* RX IF Stage Monitoring Configuration */
2866 MMWL_EXPORT rlReturnVal_t rlRfRxIfStageMonConfig(rlUInt8_t deviceMap,
2867  rlRxIfStageMonConf_t* data);
2868 /* TX Power Monitoring Configuration */
2869 MMWL_EXPORT rlReturnVal_t rlRfTxPowrMonConfig(rlUInt8_t deviceMap,
2870  rlAllTxPowMonConf_t *data);
2871 /* TX Ballbreak Monitoring Configuration */
2872 MMWL_EXPORT rlReturnVal_t rlRfTxBallbreakMonConfig(rlUInt8_t deviceMap,
2873  rlAllTxBallBreakMonCfg_t* data);
2874 /* TX Gain Phase Mismatch Monitoring Configuration */
2875 MMWL_EXPORT rlReturnVal_t rlRfTxGainPhaseMismatchMonConfig(rlUInt8_t deviceMap,
2877 /* Synth Freq Monitoring Configuration */
2878 MMWL_EXPORT rlReturnVal_t rlRfSynthFreqMonConfig(rlUInt8_t deviceMap,
2879  rlSynthFreqMonConf_t* data);
2880 /* External Analog Signals Monitoring Configuration */
2881 MMWL_EXPORT rlReturnVal_t rlRfExtAnaSignalsMonConfig(rlUInt8_t deviceMap,
2882  rlExtAnaSignalsMonConf_t* data);
2883 /* TX Internal Analog Signals Monitoring Configuration */
2884 MMWL_EXPORT rlReturnVal_t rlRfTxIntAnaSignalsMonConfig(rlUInt8_t deviceMap,
2886 /* RX Internal Analog Signals Monitoring Configuration */
2887 MMWL_EXPORT rlReturnVal_t rlRfRxIntAnaSignalsMonConfig(rlUInt8_t deviceMap,
2888  rlRxIntAnaSignalsMonConf_t* data);
2889 /* PM, CLK, LO Internal Analog Signals Monitoring Configuration */
2890 MMWL_EXPORT rlReturnVal_t rlRfPmClkLoIntAnaSignalsMonConfig(rlUInt8_t deviceMap,
2892 /* GPADC Internal Analog Signals Monitoring Configuration */
2893 MMWL_EXPORT rlReturnVal_t rlRfGpadcIntAnaSignalsMonConfig(rlUInt8_t deviceMap,
2895 /* PLL Control Voltage Monitoring Configuration */
2896 MMWL_EXPORT rlReturnVal_t rlRfPllContrlVoltMonConfig(rlUInt8_t deviceMap,
2897  rlPllContrVoltMonConf_t* data);
2898 /* Dual Clock Comparator Monitoring Configuration */
2899 MMWL_EXPORT rlReturnVal_t rlRfDualClkCompMonConfig(rlUInt8_t deviceMap,
2900  rlDualClkCompMonConf_t* data);
2901 /* RX Saturation Monitoring Configuration */
2902 MMWL_EXPORT rlReturnVal_t rlRfRxIfSatMonConfig(rlUInt8_t deviceMap,
2903  rlRxSatMonConf_t* data);
2904 /* RX Signal Image band Monitoring Configuration */
2905 MMWL_EXPORT rlReturnVal_t rlRfRxSigImgMonConfig(rlUInt8_t deviceMap,
2906  rlSigImgMonConf_t* data);
2907 /* RX mixer input power monitoring.Configuration */
2908 MMWL_EXPORT rlReturnVal_t rlRfRxMixerInPwrConfig(rlUInt8_t deviceMap,
2909  rlRxMixInPwrMonConf_t* data);
2910 /* Analog fault injection Configuration */
2911 MMWL_EXPORT rlReturnVal_t rlRfAnaFaultInjConfig(rlUInt8_t deviceMap,
2912  rlAnaFaultInj_t* data);
2913 /* TX Phase shifter monitoring Configuration */
2914 MMWL_EXPORT rlReturnVal_t rlRfTxPhShiftMonConfig(rlUInt8_t deviceMap,
2915  rlAllTxPhShiftMonConf_t* data);
2916 
2922 #ifdef __cplusplus
2923 }
2924 #endif
2925 
2926 #endif
2927 /*
2928  * END OF RL_MONITORING_H FILE
2929  */
rlUInt32_t reserved2
Reserved for Future use.
rlInt8_t sync20GMinThresh
Minimum threshold for 20GHz monitoring 1 LSB = 1 dBm.
rlUInt16_t reserved0
Reserved for Future use.
rlUInt32_t reserved2
Reserved for Future use.
rlUInt16_t reserved0
Reserved for Future use.
rlUInt8_t reserved1
Reserved for Future use.
rlUInt16_t reserved1
Reserved for Future use.
rlUInt32_t reserved1
Reserved for Future use.
rlUInt8_t reportMode
Value Definition 0 Report is sent every monitoring period without threshold check 1 Report is sen...
rlUInt8_t phShifterIncVal1
Phase shifter monitoring increment value for phase1, the monitoring phase will be incremented by this...
rlUInt8_t testMode
Value Definition 0 Production mode. Latent faults are tested and any failures are reported 1 Char...
rlUInt8_t reportMode
Value Definition 0 Report is sent every monitoring period without threshold check 1 Report is sen...
rlUInt8_t reportMode
Value Definition 0 Report is sent every monitoring period without threshold check 1 Report is sen...
rlUInt32_t reserved2
Reserved for Future use.
rlUInt16_t reserved0
Reserved for Future use.
TX power monitoring configuration.
Internal signals for DCC based clock monitoring configuration.
rlUInt16_t timeSliceNumSamples
This field specifies the number of samples constituting each time slice. The minimum allowed value ...
rlUInt16_t numSlices
Number of (primary + secondary) slices to monitor Valid range: 1 to 127.
Signal and image band energy monitoring configuration.
rlUInt8_t reserved0
Reserved for Future use.
External analog signals monitoring configuration.
rlUInt8_t reportMode
Value Definition 0 Report is sent every monitoring period without threshold check 1 Report is sen...
rlUInt16_t signalEnables
This field indicates the sets of signals which are to be monitored. When each bit in this field is ...
rlUInt16_t primarySliceDuration
It specifies the duration of each (primary) time slice. 1 LSB = 0.16us. Valid range: 4 to floor(A...
rlInt16_t txGainMismatchThresh
The magnitude of difference between measured TX powers across the enabled channels at each enabled ...
RX saturation monitoring configuration.
rlUInt8_t reportMode
Indicates the desired reporting verbosity and threshold usage. Value = 0 Report is sent every monit...
MMWL_EXPORT rlReturnVal_t rlRfTxBallbreakMonConfig(rlUInt8_t deviceMap, rlAllTxBallBreakMonCfg_t *data)
Sets information related to TX ball break detection.
MMWL_EXPORT rlReturnVal_t rlRfAnaMonConfig(rlUInt8_t deviceMap, rlMonAnaEnables_t *data)
This function contains the consolidated configuration of all analog monitoring. The enabled monitorin...
rlUInt32_t enMask
Bit Analog monitoring control 0 TEMPERATURE_MONITOR_EN 1 RX_GAIN_PHASE_MONITOR_EN 2 RX_NOISE_MO...
rlUInt32_t reserved1
Reserved for Future use.
rlUInt32_t reserved3
Reserved for Future use.
rlTxPhShiftMonConf_t * tx2PhShiftMonCfg
Tx-2 Phase shifter monitoring config.
rlUInt8_t reserved0
Reserved for Future use.
rlUInt32_t reserved2
Reserved for Future use.
rlUInt32_t ldoVmonScEn
LDO short circuit monitoring enable. There are no reports for these monitors. If there is any fault...
rlUInt16_t reserved1
Reserved for Future use.
rlUInt8_t numSlices
Number of (primary + secondary) slices to monitor Valid range: 1 to 127.
rlInt8_t monStartTime
This field determines when the monitoring starts in each chirp relative to the start of the ramp....
rlUInt16_t noiseThresh
The measured RX input referred noise figure at the enabled RF frequencies, for all channels,...
rlUInt8_t reserved1
Reserved for Future use.
rlUInt8_t reserved1
Reserved for Future use.
Digital monitoring latent fault reporting configuration.
rlUInt8_t numSlices
Number of (primary + secondary) slices to monitor Valid range: 1 to 127.
rlUInt8_t profileIndx
This field indicates the profile index for which this configuration applies.
rlUInt8_t reportMode
Value Definition 0 Report is sent every monitoring period 1 Report is sent only on a failure 2 ...
MMWL_EXPORT rlReturnVal_t rlRfRxGainPhMonConfig(rlUInt8_t deviceMap, rlRxGainPhaseMonConf_t *data)
This API is to set RX gain and phase monitoring config to device.
rlUInt8_t reserved1
Reserved for Future use.
MMWL_EXPORT rlReturnVal_t rlRfRxSigImgMonConfig(rlUInt8_t deviceMap, rlSigImgMonConf_t *data)
Sets information related to signal and image band energy.
rlTxBallbreakMonConf_t * tx0BallBrkMonCfg
Tx ballbreak monitoring config for Tx0.
rlUInt32_t reserved2
Reserved for Future use.
rlUInt8_t reportMode
Value Definition 0 RESERVED 1 Report is send only upon a failure (after checking for thresholds) ...
rlUInt8_t phShifterMon4
TXn Phase shifter phase4 monitor value. Bits Phase shift definition b1:0 Reserved (set it to 0b00...
rlInt8_t monChirpSlope
Frequency slope for each monitoring chirp is encoded in 1 bytes (8 bit signed number)....
Internal signals for PLL control voltage monitoring configuration.
rlUInt16_t reserved0
Reserved for Future use.
MMWL_EXPORT rlReturnVal_t rlRfRxIfStageMonConfig(rlUInt8_t deviceMap, rlRxIfStageMonConf_t *data)
Sets information related to RX IF filter attenuation monitoring.
rlUInt8_t rfFreqBitMask
This field indicates the exact RF frequencies inside the profile's RF band at which to measure the ...
rlUInt8_t profileIndx
This field indicates the Profile Index for which this configuration applies.
MMWL_EXPORT rlReturnVal_t rlRfTxPhShiftMonConfig(rlUInt8_t deviceMap, rlAllTxPhShiftMonConf_t *data)
Sets information related to TX Phase shifter monitoring.
rlUInt16_t reserved1
Reserved for Future use.
rlUInt8_t reserved0
Reserved for Future use.
rlUInt8_t profileIndx
This field indicates the Profile Index for which this monitoring configuration applies....
rlUInt8_t rxEn
This field indicates the RX channels that should be enabled for TX to RX loopback measurement....
rlTxBallbreakMonConf_t * tx1BallBrkMonCfg
Tx ballbreak monitoring config for Tx1.
rlUInt8_t reserved0
Reserved for Future use.
rlUInt8_t reserved0
Reserved for Future use.
rlUInt32_t reserved2
Reserved for Future use.
rlUInt16_t rxGainMismatchErrThresh
The magnitude of difference between measured RX gains across the enabled channels at each enabled R...
rlUInt32_t reserved0
Reserved for Future use.
rlUInt8_t profileIndx
This field indicates the profile Index for which this configuration applies.
MMWL_EXPORT rlReturnVal_t rlRfSynthFreqMonConfig(rlUInt8_t deviceMap, rlSynthFreqMonConf_t *data)
Sets information related to synthesizer frequency.
rlUInt8_t phShifterIncVal2
Phase shifter monitoring increment value for phase2, the monitoring phase will be incremented by this...
MMWL_EXPORT rlReturnVal_t rlRfDigMonEnableConfig(rlUInt8_t deviceMap, rlMonDigEnables_t *data)
Sets the consolidated configuration of all digital monitoring.
Definition: rl_monitoring.c:92
rlUInt32_t reserved3
Reserved for Future use.
rlUInt8_t txEnable
This field indicates if and which TX channels should be enabled while measuring RX mixer input powe...
rlUInt16_t reserved1
Reserved for Future use.
rlUInt8_t reserved0
Reserved for Future use.
rlUInt32_t reserved2
Reserved for Future use.
rlUInt8_t reportMode
Value Definition 0 RESERVED 1 Report is send only upon a failure(after checking for thresholds) ...
rlUInt32_t reserved2
Reserved for Future use.
rlUInt8_t profileIndx
The RF analog settings corresponding to this profile are used for monitoring the enabled signals,...
rlUInt16_t txPowFlatnessErrThresh
The magnitude of measured TX power flatness error, for each enabled channel, is compared against th...
rlUInt16_t rxGainFlatnessErrThresh
The magnitude of measured RX gain flatness error, for each enabled channel, is compared against thi...
rlUInt8_t rxChannelMask
This field is applicable only for SAT_MON_MODE = 0 Masks RX channels used for monitoring....
rlUInt8_t profileIndx
This field indicates the Profile Index for which this configuration applies.
MMWL_EXPORT rlReturnVal_t rlRfAnaFaultInjConfig(rlUInt8_t deviceMap, rlAnaFaultInj_t *data)
Sets information related to RF fault injection.
rlUInt8_t profileIndx
This field indicates the profile Index for which this configuration applies.
rlUInt8_t reportMode
Value Definition 0 Report is sent every monitoring period without threshold check 1 Report is sen...
rlUInt8_t reserved0
Reserved for Future use.
TX Phase shifter monitoring configuration.
rlUInt8_t reserved0
Reserved for Future use.
TX power monitoring configuration.
RX noise monitoring configuration.
RX IF stage monitoring configuration.
rlUInt8_t reportMode
Value Definition 0 Report is sent every monitoring period without threshold check 1 Report is sen...
rlTxIntAnaSignalsMonConf_t * tx2IntAnaSgnlMonCfg
Internal signals in the Tx-2 path monitoring config.
TX ballbreak monitoring configuration.
rlInt8_t sync20GMaxThresh
Maximum threshold for 20GHz monitoring 1 LSB = 1 dBm.
MMWL_EXPORT rlReturnVal_t rlRfPllContrlVoltMonConfig(rlUInt8_t deviceMap, rlPllContrVoltMonConf_t *data)
Sets information related to APLL and Synthesizer's control voltage signals monitoring.
rlUInt8_t txEn
This field indicates the TX channels that should be compared for gain and phase balance....
Internal signals in the TX path monitoring configuration.
rlUInt8_t profileIndx
This field indicates the profile Index for which this configuration applies.
rlUInt32_t reserved1
Reserved for Future use.
rlUInt8_t lpfCutoffBandEdgeDroopThresh
The LPF band edge droop of RX channels are compared against the corresponding thresholds given in t...
rlUInt8_t monitorMode
This field configures whether this monitor should be done for functional active chirps (mode 0) or ...
rlUInt16_t numSlices
Number of (primary + secondary) time slices to monitor. Valid range: 1 to 127 .
MMWL_EXPORT rlReturnVal_t rlRfRxIfSatMonConfig(rlUInt8_t deviceMap, rlRxSatMonConf_t *data)
Sets information related to RX saturation detector monitoring.
RX ADC and IF saturation information.
rlTxPowMonConf_t * tx1PowrMonCfg
Power Monitoring Configuration for Tx1.
MMWL_EXPORT rlReturnVal_t rlRfTempMonConfig(rlUInt8_t deviceMap, rlTempMonConf_t *data)
This API configure the on chip temperature monitors and report the soft results from the monitor....
TX gain and phase mismatch monitoring configuration.
rlUInt32_t reserved4
Reserved for Future use.
rlTxPhShiftMonConf_t * tx1PhShiftMonCfg
Tx-1 Phase shifter monitoring config.
rlUInt8_t vcoMonEn
This bit mask can be used to enable/disable the monitoring of non-live VCO profiles,...
rlUInt16_t reserved2
Reserved for Future use.
rlUInt16_t freqErrThresh
During the chirp, the error of the measured instantaneous chirp frequency w.r.t. the desired value ...
rlUInt8_t profileIndx
The RF analog settings corresponding to this profile are used for monitoring RX mixer input power u...
rlUInt8_t txSel
Value Definition 0 TX0 is used for generating loopback signal for RX gain measurement 1 TX1 is us...
MMWL_EXPORT rlReturnVal_t rlRfGpadcIntAnaSignalsMonConfig(rlUInt8_t deviceMap, rlGpadcIntAnaSignalsMonConf_t *data)
Sets information related to GPADC Internal Analog Signals monitoring.
rlUInt32_t reserved2
Reserved for Future use.
rlUInt16_t reserved1
Reserved for Future use.
MMWL_EXPORT rlReturnVal_t rlRfDigMonPeriodicConfig(rlUInt8_t deviceMap, rlDigMonPeriodicConf_t *data)
Sets the consolidated configuration.
TX ballbreak monitoring configuration.
MMWL_EXPORT rlReturnVal_t rlRfExtAnaSignalsMonConfig(rlUInt8_t deviceMap, rlExtAnaSignalsMonConf_t *data)
Sets information related to external DC signals monitoring.
rlUInt16_t txPhaseMismatchThresh
The magnitude of measured TX phase mismatch across the enabled channels at each enabled RF frequenc...
Synthesizer frequency monitoring configuration.
rlUInt8_t phShifterMonCfg
Enable at least two phase settings to measure phase error and to apply threshold in reporting mode 1 ...
rlUInt32_t reserved2
Reserved for Future use.
Digital monitoring configuration.
Definition: rl_monitoring.h:72
rlUInt16_t hpfCutoffErrThresh
The absolute values of RX IF HPF cutoff percentage frequency errors are compared against the corres...
rlTxIntAnaSignalsMonConf_t * tx1IntAnaSgnlMonCfg
Internal signals in the Tx-1 path monitoring config.
rlUInt8_t rfFreqBitMask
This field indicates the exact RF frequencies inside the profile's RF band at which to measure the ...
rlUInt16_t ifaGainErrThresh
The absolute deviation of RX IFA Gain from the expected gain for each enabled RX channel is compare...
MMWL_EXPORT rlReturnVal_t rlRfPmClkLoIntAnaSignalsMonConfig(rlUInt8_t deviceMap, rlPmClkLoIntAnaSignalsMonConf_t *data)
Sets information related to Power Management, Clock generation and LO distribution.
rlUInt8_t reportMode
Value Definition 0 Report is sent every monitoring period without threshold check 1 Report is sen...
Internal signals for GPADC monitoring configuration.
TX Phase shifter monitoring configuration.
rlUInt16_t txPhShiftDacMonThresh
The TX phase shifter DAC monitor delta threshold 1 LSB = 1.8V/1024 valid range : 0V to 1....
rlInt16_t anaTempThreshMax
The temperatures read from near the sensors near the RF analog modules are compared against a maximum...
rlUInt16_t reserved1
Reserved for Future use.
rlUInt8_t profileIndx
The RF analog settings corresponding to this profile are used for monitoring the enabled signals,...
rlTxIntAnaSignalsMonConf_t * tx0IntAnaSgnlMonCfg
Internal signals in the Tx-0 path monitoring config.
RX mixer input power monitoring configuration.
rlUInt32_t reserved1
Reserved for Future use.
rlUInt8_t satMonSel
01 => Enable only the ADC saturation monitor 11 => Enable both the ADC and IFA1 saturation monitors
rlUInt16_t rxGainAbsThresh
The magnitude of difference between the programmed and measured RX gain for each enabled channel at...
rlUInt32_t reserved3
Reserved for Future use.
rlUInt16_t tempDiffThresh
The maximum difference across temperatures read from all the enabled sensors is compared against this...
MMWL_EXPORT rlReturnVal_t rlRfTxIntAnaSignalsMonConfig(rlUInt8_t deviceMap, rlAllTxIntAnaSignalsMonConf_t *data)
Sets information related to TX Internal Analog Signals monitoring.
rlUInt16_t dccPairEnables
This field indicates which pairs of clocks to monitor. When a bit in the field is set to 1,...
MMWL_EXPORT rlReturnVal_t rlRfRxNoiseMonConfig(rlUInt8_t deviceMap, rlRxNoiseMonConf_t *data)
Sets information related to RX noise monitoring.
rlUInt8_t phShifterIncVal3
Phase shifter monitoring increment value for phase3, the monitoring phase will be incremented by this...
rlUInt32_t reserved3
Reserved for Future use.
rlUInt8_t phShifterMon3
TXn Phase shifter phase3 monitor value. Bits Phase shift definition b1:0 Reserved (set it to 0b00...
rlUInt8_t rfFreqBitMask
This field indicates the exact RF frequencies inside the profile's RF band at which to measure the ...
rlUInt16_t txPowAbsErrThresh
The magnitude of difference between the programmed and measured TX power for each enabled channel a...
rlUInt16_t reserved0
Reserved for Future use.
rlTxBallbreakMonConf_t * tx2BallBrkMonCfg
Tx ballbreak monitoring config for Tx2.
Analog monitoring configuration.
rlUInt8_t profileIndx
This field indicates the profile Index for which this configuration applies.
rlUInt8_t signalBuffEnables
This field indicates the sets of externally fed DC signals which are to be buffered before being fe...
rlInt8_t monChirpSlope
Frequency slope for each monitoring chirp is encoded in 1 bytes (8 bit signed number) 1 LSB = 3....
rlUInt32_t reserved0
Reserved for Future use.
rlUInt32_t reserved2
Reserved for Future use.
rlTxPowMonConf_t * tx2PowrMonCfg
Power Monitoring Configuration for Tx2.
rlUInt8_t rxEn
This field indicates the RX channels that should be enabled for TX to RX loopback measurement....
RX signal and image band energy statistics.
MMWL_EXPORT rlReturnVal_t rlRfRxIntAnaSignalsMonConfig(rlUInt8_t deviceMap, rlRxIntAnaSignalsMonConf_t *data)
Sets information related to RX Internal Analog Signals monitoring.
rlUInt8_t reportMode
Value Definition 0 RESERVED 1 Report is send only upon a failure(after checking for thresholds) ...
rlUInt8_t signalInpEnables
This field indicates the sets of externally fed DC signals which are to be monitored using GPADC....
rlUInt32_t periodicEnableMask
Bit Monitoring 0 PERIODIC_CONFG_REGISTER_READ_EN 1 RESERVED 2 DFE_STC_EN 3 FRAME_TIMING_MONIT...
rlInt16_t anaTempThreshMin
The temperatures read from near the sensors near the RF analog modules are compared against a minimum...
Temperature sensor monitoring configuration.
rlUInt8_t reserved0
Reserved for Future use.
rlUInt8_t phShifterMon2
TXn Phase shifter phase2 monitor value. Bits Phase shift definition b1:0 Reserved (set it to 0b00...
rlUInt8_t lpfCutoffStopBandAttenThresh
The LPF stop band attenuation at 2x analog LPF’s band edge with respect to the analog LPF’s band ed...
rlInt16_t digTempThreshMax
The temperatures read from near the sensor near the digital module are compared against a maximum thr...
Internal signals in the TX path monitoring configuration.
rlUInt16_t rxGainPhaseMismatchErrThresh
The magnitude of measured RX phase mismatch across the enabled channels at each enabled RF frequenc...
Internal signals for PM, CLK and LO monitoring configuration.
rlUInt8_t sync20GSigSel
Value Definition 0 20GHz SYNC monitoring disabled 1 FMCW_SYNC_IN monitoring enabled 2 FMCW_SYNC...
MMWL_EXPORT rlReturnVal_t rlRfDualClkCompMonConfig(rlUInt8_t deviceMap, rlDualClkCompMonConf_t *data)
Sets information related to the DCC based clock frequency monitoring.
rlTxPowMonConf_t * tx0PowrMonCfg
Power Monitoring Configuration for Tx0.
rlTxPhShiftMonConf_t * tx0PhShiftMonCfg
Tx-0 Phase shifter monitoring config.
rlUInt8_t profileIndx
This field indicates the profile Index for which this configuration applies.
rlUInt16_t txPhaseErrorThresh
The threshold for deviation of the TX output phase difference between the measured phase values and c...
rlUInt8_t reserved1
Reserved for Future use.
MMWL_EXPORT rlReturnVal_t rlRfTxGainPhaseMismatchMonConfig(rlUInt8_t deviceMap, rlTxGainPhaseMismatchMonConf_t *data)
Sets information related to TX gain and phase mismatch monitoring.
rlUInt8_t reportMode
Value Definition 0 Report is sent every monitoring period without threshold check 1 Report is sen...
rlUInt8_t reportMode
Value Definition 0 RESERVED 1 Report is send only upon a failure (after checking for thresholds) ...
rlUInt32_t reserved2
Reserved for Future use.
rlUInt16_t thresholds
The measured RX mixer input voltage swings during this monitoring is compared against the minimum a...
RX gain and phase monitoring configuration.
rlUInt8_t reserved0
Reserved for Future use.
rlUInt8_t reportMode
Value Definition 0 RESERVED 1 Report is send only upon a failure (after checking for thresholds) ...
rlUInt16_t reserved1
Reserved for Future use.
rlInt16_t digTempThreshMin
The temperatures read from near the sensor near the digital module are compared against a minimum thr...
rlUInt8_t phShifterMon1
TXn Phase shifter phase1 monitor value. Bits Phase shift definition b1:0 Reserved (set it to 0b00...
rlUInt8_t reportMode
Value Definition 0 Report is sent every monitoring period without threshold check 1 Report is sen...
rlUInt16_t reserved2
Reserved for Future use.
rlUInt16_t reserved1
Reserved for Future use.
rlUInt32_t reserved1
Reserved for Future use.
rlUInt8_t phShifterIncVal4
Phase shifter monitoring increment value for phase4, the monitoring phase will be incremented by this...
rlUInt8_t rfFreqBitMask
This field indicates the RF frequencies inside the profile's RF band at which to measure the required...
rlUInt32_t reserved1
Reserved for Future use.
MMWL_EXPORT rlReturnVal_t rlRfTxPowrMonConfig(rlUInt8_t deviceMap, rlAllTxPowMonConf_t *data)
Sets information related to TX power monitoring.
rlUInt16_t txAmplErrorThresh
The threshold for deviation of the TX output amplitude difference between all enabled phase settings....
rlUInt32_t enMask
Bit: Dig Monitoring 0 Reserved 1 CR4 and VIM lockstep test of diagnostic 2 Reserved 3 VIM tes...
rlUInt32_t reserved1
Reserved for Future use.

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