mmwavelink.h
1 /*************************************************************************************************
2  * FileName : mmwavelink.h
3  *
4  * Description : This file includes all the header files which needs to be included by application
5  *
6  *************************************************************************************************
7  * (C) Copyright 2014, Texas Instruments Incorporated. - TI web address www.ti.com
8  *------------------------------------------------------------------------------------------------
9  *
10  * Redistribution and use in source and binary forms, with or without modification, are permitted
11  * provided that the following conditions are met:
12  *
13  * Redistributions of source code must retain the above copyright notice, this list of
14  * conditions and the following disclaimer.
15  *
16  * Redistributions in binary form must reproduce the above copyright notice, this list of
17  * conditions and the following disclaimer in the documentation and/or other materials provided
18  * with the distribution.
19  *
20  * Neither the name of Texas Instruments Incorporated nor the names of its contributors may be
21  * used to endorse or promote products derived from this software without specific prior
22  * written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
25  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
26  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
27  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
31  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32  * POSSIBILITY OF SUCH DAMAGE.
33  *
34  */
35 
36 /*************************************************************************************************
37  * FILE INCLUSION PROTECTION
38  *************************************************************************************************
39  */
40 #ifndef MMWAVELINK_H
41 #define MMWAVELINK_H
42 /*LDRA_NOANALYSIS*/
308 /*LDRA_ANALYSIS*/
309 
310  /****************************************************************************************
311  * INCLUDE FILES
312  *****************************************************************************************
313  */
314 #include <stdint.h>
315 #include <ti/control/mmwavelink/include/rl_datatypes.h>
316 
317 #ifdef __cplusplus
318 extern "C" {
319 #endif
320 
321 /*****************************************************************************************
322  * MACRO DEFINITIONS
323  *****************************************************************************************
324  */
325 
326 /* Export Macro for DLL */
327 #if defined(WIN32) || defined(WIN32_) || defined(_MSC_VER)
328 #define MMWL_EXPORT __declspec(dllexport)
329 #else
330 #define MMWL_EXPORT
331 #endif
332 
334 #define RL_MMWAVELINK_VERSION "2.2.0.2.6.4.20"
335 #define RL_MMWAVELINK_VERSION_MAJOR (2U)
336 #define RL_MMWAVELINK_VERSION_MINOR (2U)
337 #define RL_MMWAVELINK_VERSION_BUILD (0U)
338 #define RL_MMWAVELINK_VERSION_DEBUG (2U)
339 #define RL_MMWAVELINK_VERSION_DAY (6U)
340 #define RL_MMWAVELINK_VERSION_MONTH (4U)
341 #define RL_MMWAVELINK_VERSION_YEAR (20U)
342 
344 #define RL_RET_CODE_OK ((rlReturnVal_t)0) /* no-error */
345 #define RL_RET_CODE_PROTOCOL_ERROR (-1) /* mmWaveLink Protocol error */
346 #define RL_RET_CODE_INVALID_INPUT (-2) /* invalid input from the application */
347 #define RL_RET_CODE_SELF_ERROR (-3) /* error in mmWaveLink itself */
348 #define RL_RET_CODE_RADAR_IF_ERROR (-4) /* Radar HW/SW interface error */
349 #define RL_RET_CODE_MALLOC_ERROR (-5) /* memory allocation error */
350 #define RL_RET_CODE_CRC_FAILED (-6) /* CRC value mismatched wrt
351  received data */
352 #define RL_RET_CODE_CHKSUM_FAILED (-7) /* Checksum value mismatched wrt to
353  received data */
354 #define RL_RET_CODE_RESP_TIMEOUT (-8) /* device failed to send response
355  within time */
356 #define RL_RET_CODE_FATAL_ERROR (-9) /* Fatal error internal to
357  mmWaveLink APIs */
358 #define RL_RET_CODE_RADAR_OSIF_ERROR (-10) /* OS interface failure */
359 #define RL_RET_CODE_INVALID_STATE_ERROR (-11) /* Invalid state within mmWaveLink */
360 #define RL_RET_CODE_API_NOT_SUPPORTED (-12) /* API called is not supported */
361 #define RL_RET_CODE_MSGID_MISMATCHED (-13) /* Message-ID mismatched in
362  response data */
363 #define RL_RET_CODE_NULL_PTR (-14) /* Null pointer error */
364 #define RL_RET_CODE_INTERFACE_CB_NULL (-15) /* Interface callback passed as NULL */
365 #define RL_RET_CODE_NACK_ERROR (-16) /* If device sends NACK message */
366 #define RL_RET_CODE_HOSTIRQ_TIMEOUT (-17) /* If post writing CNYS HostIRQ is not
367  down within time limit and re-writing
368  CNYS also has same result */
369 #define RL_RET_CODE_RX_SEQ_NUM_NOT_MATCH (-18) /* ACK sequence number is not matching with
370  CMD sequence number */
371 
373 #define RL_RET_CODE_INVLD_OPCODE (1U) /* Incorrect opcode/Msg ID */
374 #define RL_RET_CODE_INVLD_NUM_SB (2U) /* Incorrect no. of Sub-Block */
375 #define RL_RET_CODE_INVLD_SB_ID (3U) /* Incorrect Sub-Block ID */
376 #define RL_RET_CODE_INVLD_SB_LEN (4U) /* Incorrect Sub-Block Length */
377 #define RL_RET_CODE_SB_INVL_DATA (5U) /* Incorrect Sub-Block Data */
378 #define RL_RET_CODE_SB_PROCESS_ERR (6U) /* Error in Sub Block processing */
379 #define RL_RET_CODE_MISMATCH_FILE_CRC (7U) /* Mismatch in File CRC */
380 #define RL_RET_CODE_MISMATCH_FILE_TYPE (8U) /* Mismatch in File Type */
381 
383 #define RL_RET_CODE_FRAME_ALREADY_STARTED (20U) /* Frames are already started when the
384  FRAME_START command was issued */
385 #define RL_RET_CODE_FRAME_ALREADY_ENDED (21U) /* Frames are already stopped when the
386  FRAME_STOP command was issued */
387 #define RL_RET_CODE_FRAME_CFG_NOT_RECVD (22U) /* No valid frame configuration API was
388  issued and frames are started */
389 #define RL_RET_CODE_FRAME_TRIG_INVL_IN (23U) /* START_STOP_CMD parameter is out of
390  range*/
391 
393 #define RL_RET_CODE_CH_CFG_RX_INVAL_IN (24U) /* RX_CHAN_EN parameter is out of range
394  may vary based on device */
395 #define RL_RET_CODE_CH_CFG_TX_INVAL_IN (25U) /* TX_CHAN_EN parameter is out of range
396  may vary based on device */
397 #define RL_RET_CODE_CH_CFG_CASC_INVAL_IN (26U) /* CASCADING_CFG parameter is out of
398  range [0, 2] */
399 
401 #define RL_RET_CODE_ADC_BITS_INVAL_IN (27U) /* NUM_ADC_BITS parameter is out of
402  range [0, 2] */
403 #define RL_RET_CODE_ADC_FORM_INVAL_IN (28U) /* ADC_OUT_FMT parameter is out of
404  range [0, 3] */
405 
407 #define RL_RET_CODE_LP_ADC_INVAL_IN (29U) /* LP_ADC_MODE parameter is out of
408  range [0, 1] */
409 
411 #define RL_RET_CODE_DYN_PS_INVAL_IN (30U) /* BLOCK_CFG parameter is out of
412  range [0, 7] */
413 
415 #define RL_RET_CODE_HSI_DIV_INVAL_IN (31U) /* HSI clock rate code[1:0] is 0 */
416 #define RL_RET_CODE_RESERVED0 (32U)
417 #define RL_RET_CODE_HSI_DIV_INVAL_1IN (33U) /* HSI clock rate code[3:2] is 3 &
418  HSI clock rate code[1:0] is 2 */
419 #define RL_RET_CODE_HSI_DIV_INVAL_2IN (34U) /* HSI clock rate code[3:2] is 3 &
420  HSI clock rate code[1:0] is 2 */
421 
423 #define RL_RET_CODE_PF_IND_INVAL_IN (35U) /* PF indx >= 4 */
424 #define RL_RET_CODE_PF_START_FREQ_INVAL_IN (36U) /* PF freq const is not
425  with[76GHz,81GHz] in limit */
426 #define RL_RET_CODE_PF_IDLE_TIME_INVAL_IN (37U) /* PF idle time const > 5.24ms */
427 #define RL_RET_CODE_PF_IDLE_TIME_1INVAL_IN (38U) /* Maximum DFE spill time (refer
428  rampgen calculator in mmWaveStudio
429  for more details) > PF idle
430  time const */
431 #define RL_RET_CODE_PF_ADC_START_INVAL_IN (39U) /* PF ADC start time const > 4095 */
432 #define RL_RET_CODE_PF_RAMP_END_INVAL_IN (40U) /* PF ramp end time > 524287 */
433 #define RL_RET_CODE_PF_RAMP_END_1INVAL_IN (41U) /* PF ramp end time < PF ADC start
434  time const + ADC sampling time */
435 #define RL_RET_CODE_PF_TX0_INVAL_IN (42U) /* PF_TX_OUTPUT_POWER_BACKOFF for
436  TX0 > 30 */
437 #define RL_RET_CODE_PF_TX1_INVAL_IN (43U) /* PF_TX_OUTPUT_POWER_BACKOFF for
438  TX1 > 30 */
439 #define RL_RET_CODE_PF_TX2_INVAL_IN (44U) /* PF_TX_OUTPUT_POWER_BACKOFF for
440  TX2 > 30 */
441 #define RL_RET_CODE_RESERVED1 (45U)
442 #define RL_RET_CODE_PF_FREQ_SLOPE_1INVAL_IN (46U) /* Ramp end freq is not
443  with[76GHz,81GHz] in limits */
444 #define RL_RET_CODE_PF_TX_START_INVAL_IN (47U) /* Absolute value of TX_START_TIME
445  is > 38.45us */
446 #define RL_RET_CODE_PF_NUM_ADC_SMAP_INVAL_IN (48U) /* Number of ADC samples is not
447  within [2,8192] */
448 #define RL_RET_CODE_PF_DFE_SAMP_RATE_INVAL_IN (49U) /* Output sampling rate is not
449  within [2, 37.5]Msps */
450 #define RL_RET_CODE_PF_HPF1_CF_INVAL_IN (50U) /* HPF1 corner frequency > 700 kHz */
451 #define RL_RET_CODE_PF_HPF2_CF_INVAL_IN (51U) /* HPF2 corner frequency > 2.8 MHz */
452 #define RL_RET_CODE_PF_RX_GAIN_INVAL_IN (52U) /* PF_RX_GAIN is not within [24, 52] dB
453  orPF_RX_GAIN is an odd number */
454 #define RL_RET_CODE_RESERVED2 (53U)
455 #define RL_RET_CODE_RESERVED3 (54U)
456 #define RL_RET_CODE_RESERVED4 (55U)
457 #define RL_RET_CODE_RESERVED5 (56U)
458 #define RL_RET_CODE_RESERVED6 (57U)
459 #define RL_RET_CODE_RESERVED7 (58U)
460 
462 #define RL_RET_CODE_CHIRP_START_INVAL_IN (59U) /* Chirp Start indx >= 512 */
463 #define RL_RET_CODE_CHIRP_END_INVAL_IN (60U) /* Chirp End indx >= 512 */
464 #define RL_RET_CODE_CHIRP_END_1INVAL_IN (61U) /* Chirp Start indx > Chirp End indx */
465 #define RL_RET_CODE_CHIRP_PF_IND_INVAL_IN (62U) /* PF indx >= 4 */
466 #define RL_RET_CODE_CHIRP_PF_IND_1INVAL_IN (63U) /* PF corresponding to PF indx is not
467  defined */
468 #define RL_RET_CODE_CHIRP_START_FREQ_INVAL_IN (64U) /* Chirp freq start > 8388607 */
469 #define RL_RET_CODE_CHIRP_SLOPE_INVAL_IN (65U) /* Chirp freq slope > 63 */
470 #define RL_RET_CODE_CHIRP_SLOPE_1INVAL_IN (66U) /* Chirp start or end
471  freq[76GHz,81GHz] is outside */
472 #define RL_RET_CODE_CHIRP_IDLE_TIME_INVAL_IN (67U) /* Chirp Idle time > 4095 */
473 #define RL_RET_CODE_CHIRP_ADC_START_INVAL_IN (68U) /* Chirp ADC start time > 4095 */
474 #define RL_RET_CODE_CHIRP_ADC_START_1INVAL_IN (69U) /* Ramp end time < ADC start time +
475  ADC sampling time */
476 #define RL_RET_CODE_CHIRP_TX_ENA_INVAL_IN (70U) /* Chirp TX enable > 7 */
477 #define RL_RET_CODE_CHIRP_TX_ENA_1INVAL_IN (71U) /* Chirp TX enable indicates to enable
478  a TX which is not enabled in
479  Channel config */
480 
482 #define RL_RET_CODE_FRAME_CHIRP_STR_INVAL_IN (72U) /* Chirp Start indx >= 512 */
483 #define RL_RET_CODE_FRAME_CHIRP_END_INVAL_IN (73U) /* Chirp End indx >= 512 */
484 #define RL_RET_CODE_FRAME_CHIRP_END_1INVAL_IN (74U) /* Chirp Start indx > Chirp End indx */
485 #define RL_RET_CODE_FRAME_CHIRP_END_2INVAL_IN (75U) /* Chirp used in frame is not
486  configured by Chirp config */
487 #define RL_RET_CODE_FRAME_CHIRP_PF_INVAL_IN (76U) /* Profile used in frame is not
488  configured by PF config */
489 #define RL_RET_CODE_FRAME_CHIRP_LOOPS_INVAL_IN (77U) /* No. of loops is outside[1,255] */
490 #define RL_RET_CODE_RESERVED8 (78U)
491 #define RL_RET_CODE_FRAME_PERIOD_INVAL_IN (79U) /* Frame periodicity is
492  outside[100us,1.342s] */
493 #define RL_RET_CODE_FRAME_PERIOD_1INVAL_IN (80U) /* Frame ON time > Frame periodicity */
494 #define RL_RET_CODE_FRAME_TRIG_SEL_INVAL_IN (81U) /* Trigger select is outside[1,2] */
495 #define RL_RET_CODE_FRAME_TRIG_DELAY_INVAL_IN (82U) /* Frame Trigger delay > 100us */
496 #define RL_RET_CODE_FRAME_IS_ONGOING (83U) /* API issued when frame is ongoing */
497 #define RL_RET_CODE_FRAME_DUMMY_CHIRPS_INVAL_IN (160U) /* The Dummy chirps at end of frame
498  is not supported */
499 
501 #define RL_RET_CODE_AFRAME_NUM_SUBF_INVAL_IN (84U) /* No. Sub Frames is outside[1,4] */
502 #define RL_RET_CODE_AFRAME_FORCE_PF_INVAL_IN (85U) /* Force single Profile is
503  outside[1,4] */
504 #define RL_RET_CODE_AFRAME_PF_IND_INVAL_IN (86U) /* Force single Profile >= 4 */
505 #define RL_RET_CODE_AFRAME_PF_IND_1INVAL_IN (87U) /* Profile defined by Force Single
506  Profile is not defined */
507 #define RL_RET_CODE_AFRAME_CHIRP_STR_INVAL_IN (88U) /* Sub Frame Chirp Start indx >= 512 */
508 #define RL_RET_CODE_AFRAME_NCHIRP_INVAL_IN (89U) /* Sub Frame NO. of unique chirps per
509  Burst is outside[1,512] */
510 #define RL_RET_CODE_AFRAME_NCHIRP_1INVAL_IN (90U) /* Chirp used in frame is not
511  configured by Chirp config */
512 #define RL_RET_CODE_AFRAME_CHIRP_PF_INVAL_IN (91U) /* Profie used in the frame is not
513  configured by profile config */
514 #define RL_RET_CODE_AFRAME_CHIRP_LOOPS_INVAL_IN (92U) /* Sub Frame No. of loops is
515  outside[1,225] */
516 #define RL_RET_CODE_AFRAME_BURST_PERIOD_INVAL_IN (93U) /* Sub Frame burst period is
517  outside[100us,1.342s] */
518 #define RL_RET_CODE_AFRAME_BURST_PER_1INVAL_IN (94U) /* Burst ON time > Burst period */
519 #define RL_RET_CODE_AFRAME_BURST_STIND_INVAL_IN (95U) /* Sub Frame Chirp start indx
520  offset >= 512 */
521 #define RL_RET_CODE_AFRAME_BURST_SIND_1INVAL_IN (96U) /* Sub Frame Chirp start indx >= 512
522  or (Sub Frame Chirp start indx +
523  Sub Frame No. unique Chirps per
524  burst - 1) >= 512*/
525 #define RL_RET_CODE_AFRAME_NUM_BURSTS_INVAL_IN (97U) /* Sub Frame No. bursts is
526  outside[1,512] */
527 #define RL_RET_CODE_AFRAME_BURST_LOOPS_INVAL_IN (98U) /* Sub Frame No. outer loops is
528  outside[1,64] */
529 #define RL_RET_CODE_AFRAME_SF_PERIOD_INVAL_IN (99U) /* Sub Frame period is
530  outside[100us,1.342s] */
531 #define RL_RET_CODE_AFRAME_SF_PERIOD_1INVAL_IN (100U) /* Sub Frame ontime > Sub Frame period
532  or when test source enabled, Sub
533  Frame idale time < 150us */
534 #define RL_RET_CODE_RESERVED9 (101U)
535 #define RL_RET_CODE_AFRAME_TRIG_SEL_INVAL_IN (102U) /* Trigger select is outside[1,2] */
536 #define RL_RET_CODE_AFRAME_TRIG_DELAY_INVAL_IN (103U) /* Frame trigger delay is > 100us */
537 #define RL_RET_CODE_AFRAME_IS_ONGOING (104U) /* API issued when frame is ongoing */
538 
540 #define RL_RET_CODE_TS_POS_VECY_INVAL_IN (105U) /* position vector x[y] < 0 */
541 #define RL_RET_CODE_RESERVED10 (106U)
542 #define RL_RET_CODE_TS_VEL_VECXYZ_INVAL_IN (107U) /* position vector x[x] < 5000 or
543  position vector x[y] < 5000 or
544  position vector x[x] < 5000 */
545 #define RL_RET_CODE_TS_SIG_LEVEL_INVAL_IN (108U) /* SIG_LEV_VECx > 950 */
546 #define RL_RET_CODE_TS_RX_ANT_POS_INVAL_IN (109U) /* RX_ANT_POS_XZ[Bytex] > 120 */
547 #define RL_RET_CODE_RESERVED11 (110U)
548 
550 #define RL_RET_CODE_PROG_FILT_STARTINDX_INVALID (111U) /* Prog. Filter coefficient start
551  indx is odd number */
552 #define RL_RET_CODE_PROG_FILT_PROFILE_INVALID (112U) /* Pro indx >= 4 */
553 #define RL_RET_CODE_PROG_FILT_UNSUPPORTED_DEV (113U) /* API issued for non AWR1642 device*/
554 
556 #define RL_RET_CODE_PERCHIRPPHSHIFT_UNSUPPORTED_DEV (114U) /* API issued for non AWR1243/AWR2243
557  device */
558 #define RL_RET_CODE_PERCHIRPPHSHIFT_STIND (115U) /* Chirp Start indx >= 512 */
559 #define RL_RET_CODE_PERCHIRPPHSHIFT_ENIND (116U) /* Chirp End indx >= 512 */
560 #define RL_RET_CODE_PERCHIRPPHSHIFT_WRONG_STIND (117U) /* Chirp Start indx > End indx */
561 
563 #define RL_RET_CODE_RF_INIT_NOT_DONE (118U) /* Boot time calibrations are not
564  done so cannot run runtime calibrations */
565 #define RL_RET_CODE_FORCE_TEMP_BIN_IDX_INVALID (286U) /* The forced temperature bin index
566  is invalid */
567 #define RL_RET_CODE_FREQ_LIMIT_OUT_RANGE (119U) /* Freq. is outside[76GHz,81GHz] or
568  Freq. low limit > high limit */
569 #define RL_RET_CODE_CAL_MON_TIME_INVALID (120U) /* CALIB_MON_TIME_UNIT <= 0 */
570 #define RL_RET_CODE_RUN_CAL_PERIOD_INVALID (121U) /* CALIBRATION_ PERIODICITY = 0 */
571 #define RL_RET_CODE_CONT_STREAM_MODE_EN (122U) /* API is issued when continuous
572  streaming mode is on */
573 #define RL_RET_CODE_RX_GAIN_BOOT_CAL_NOT_DONE (123U) /* RX gain run time calibration was
574  requested but boot time calibration
575  was not performed */
576 #define RL_RET_CODE_LO_DIST_BOOT_CAL_NOT_DONE (124U) /* LO distribution run time
577  calibration was requested but boot time
578  calibration was not performed */
579 #define RL_RET_CODE_TX_PWR_BOOT_CAL_NOT_DONE (125U) /* TX power run time calibration was
580  requested but boot time calibration
581  was not performed */
582 #define RL_RET_CODE_PROG_FILTR_UNSUPPORTED_DFEMODE (126U) /* DFE mode is pseudo real */
583 #define RL_RET_CODE_ADC_BITS_FULL_SCALE_REDUC_INVAL (127U) /* FULL_SCALE_REDUCTION_FACTOR is > 0
584  for 16 bit ADC, or > 2 for 14 bit
585  ADC mode or > 4 for 12 bit ADC mode */
586 #define RL_RET_CODE_CAL_MON_NUM_CASC_DEV_INVALID (128U) /* NUM_OF_CASCADED_DEV <= 0 */
587 #define RL_RET_CODE_FRAME_TRIG_INVL_STOP_IN (129U)/* Frame stop option-4 cannot be used
588  in SW Triggered mode */
589 #define RL_RET_CODE_RF_FREQBAND_INVALID (130U) /* Minimum RF frequency is < 200MHz */
590 
592 #define RL_RET_CODE_INVAL_LOOPBACK_TYPE (132U)
593 #define RL_RET_CODE_INVAL_LOOPBACK_BURST_IND (133U)
594 #define RL_RET_CODE_INVAL_LOOPBACK_CONFIG (134U)
595 #define RL_RET_CODE_DYN_CHIRP_INVAL_SEG (135U)
596 #define RL_RET_CODE_DYN_PERCHIRP_PHSHFT_INVA_SEG (136U)
597 #define RL_RET_CODE_INVALID_CAL_CHUNK_ID (137U)
598 #define RL_RET_CODE_INVALID_CAL_CHUNK_DATA (138U)
599 
601 #define RL_RET_CODE_RX02_RF_TURN_OFF_TIME_INVALID (139U) /* RX02_RF_TURN_OFF_TIME is not
602  within the range [-1024, 1023] */
603 #define RL_RET_CODE_RX13_RF_TURN_OFF_TIME_INVALID (140U) /* RX13_RF_TURN_OFF_TIME is not
604  within the range [-1024, 1023] */
605 #define RL_RET_CODE_RX02_BB_TURN_OFF_TIME_INVALID (141U) /* RX02_BB_TURN_OFF_TIME is not
606  within the range [-1024, 1023] */
607 #define RL_RET_CODE_RX13_BB_TURN_OFF_TIME_INVALID (142U) /* RX13_BB_TURN_OFF_TIME is not
608  within the range [-1024, 1023] */
609 #define RL_RET_CODE_RX02_RF_PREENABLE_TIME_INVALID (143U) /* RX02_RF_PREENABLE_TIME is not
610  within the range [-1024, 1023] */
611 #define RL_RET_CODE_RX13_RF_PREENABLE_TIME_INVALID (144U) /* RX13_RF_PREENABLE_TIME is not
612  within the range [-1024, 1023] */
613 #define RL_RET_CODE_RX02_BB_PREENABLE_TIME_INVALID (145U) /* RX02_BB_PREENABLE_TIME is not
614  within the range [-1024, 1023] */
615 #define RL_RET_CODE_RX13_BB_PREENABLE_TIME_INVALID (146U) /* RX13_BB_PREENABLE_TIME is not
616  within the range [-1024, 1023] */
617 #define RL_RET_CODE_RX02_RF_TURN_ON_TIME_INVALID (147U) /* RX02_RF_TURN_ON_TIME is not
618  within the range [-1024, 1023] */
619 #define RL_RET_CODE_RX13_RF_TURN_ON_TIME_INVALID (148U) /* RX13_RF_TURN_ON_TIME is not
620  within the range [-1024, 1023] */
621 #define RL_RET_CODE_RX02_BB_TURN_ON_TIME_INVALID (149U) /* RX02_BB_TURN_ON_TIME is not
622  within the range [-1024, 1023] */
623 #define RL_RET_CODE_RX13_BB_TURN_ON_TIME_INVALID (150U) /* RX13_BB_TURN_ON_TIME is not
624  within the range [-1024, 1023] */
625 #define RL_RET_CODE_RX_LO_TURN_OFF_TIME_INVALID (151U) /* RX_LO_TURN_OFF_TIME is not
626  within the range [-1024, 1023] */
627 #define RL_RET_CODE_TX_LO_TURN_OFF_TIME_INVALID (152U) /* TX_LO_TURN_OFF_TIME is not
628  within the range [-1024, 1023] */
629 #define RL_RET_CODE_RX_LO_TURN_ON_TIME_INVALID (153U) /* RX_LO_TURN_ON_TIME is not
630  within the range [-1024, 1023] */
631 #define RL_RET_CODE_TX_LO_TURN_ON_TIME_INVALID (154U) /* TX_LO_TURN_ON_TIME is not
632  within the range [-1024, 1023] */
633 #define RL_RET_CODE_SUBFRAME_TRIGGER_INVALID (155U) /* Sub frame trigger option is not
634  enabled but sub frame trigger API
635  is issued or frame is configured
636  for software trigger mode and
637  sub-frame trigger API is issued */
638 #define RL_RET_CODE_REGULAR_ADC_MODE_INVALID (156U) /* Regular ADC mode is issued on a
639  5 MHz part variant */
640 #define RL_RET_CODE_CHIRP_ROW_SELECT_INVAL_IN (159U) /* Chirp row select is not with in
641  the range [0x00, 0x30] */
642 
643 #define RL_RET_CODE_DEVICE_NOT_ASILB_TYPE (250U) /* Device type is not ASILB */
644 #define RL_RET_CODE_FRAME_ONGOING (251U) /* Fault injection API or Digital
645  latent fault API is issued when
646  frames are ongoing */
647 #define RL_RET_CODE_INVLD_REPO_MODE (252U) /* Invalid reporting mode */
648 #define RL_RET_CODE_INVLD_PROFILE_ID (253U) /* Configured profile ID is not
649  within [0,3] */
650 #define RL_RET_CODE_INVLD_PROFILE (254U) /* Monitoring profile ID is not
651  configured yet */
652 #define RL_RET_CODE_INVLD_EXTSIG_SETLTIME (255U) /* Settling time is configured is
653  more than 12us */
654 #define RL_RET_CODE_INVLD_NO_RX_ENABLED (256U) /* None of the RXs are enabled */
655 #define RL_RET_CODE_INVLD_TX0_NOT_ENABLED (257U) /* TX0 is not enabled */
656 #define RL_RET_CODE_INVLD_TX1_NOT_ENABLED (258U) /* TX1 is not enabled */
657 #define RL_RET_CODE_INVLD_TX2_NOT_ENABLED (259U) /* TX2 is not enabled */
658 #define RL_RET_CODE_MON_INVALID_RF_BIT_MASK (260U) /* Invalid RF bit mask */
659 #define RL_RET_CODE_RESERVED12 (261U)
660 #define RL_RET_CODE_RESERVED13 (262U)
661 #define RL_RET_CODE_MON_TX_EN_CHK_FAIL (263U) /* Monitored TX is not enabled */
662 #define RL_RET_CODE_MON_RX_CH_EN_CHK_FAIL (264U) /* Monitored RX is not enabled */
663 #define RL_RET_CODE_MON_TX_CH_PS_LB (265U) /* TX selected for RX gain phase
664  monitor is TX2 (Only TX0 or TX1 is
665  allowed) */
666 #define RL_RET_CODE_INVLD_SAT_MON_SEL (266U) /* SAT_MON_SEL is not in [0, 3] */
667 #define RL_RET_CODE_INVLD_SAT_MON_PRI_SLICE_DUR (267U) /* SAT_MON_PRIMARY_TIME_SLICE_DURATION
668  is less than 0.64us or greater
669  than ADC sampling time */
670 #define RL_RET_CODE_INVLD_SAT_MON_NUM_SLICES (268U) /* SAT_MON_NUM_SLICES is 0 or
671  greater than 127 */
672 #define RL_RET_CODE_INVLD_SIG_IMG_SLICENUM (269U) /* SIG_IMG_MON_NUM_SLICES is 0 or
673  greater than 127 */
674 #define RL_RET_CODE_INVLD_SIG_IMG_NUMSAMPPERSLICE (270U) /* NUM_SAMPLES_ PER_PRIMARY_TIME_SLICE
675  is odd, or less than 4 in Complex1x
676  mode or less than 8 in non-Complex1x
677  modes or greater than NUM_ADC_SAMPLES*/
678 #define RL_RET_CODE_INVLD_SYNTH_L1_LIN (271U)
679 #define RL_RET_CODE_INVLD_SYNTH_L2_LIN (272U)
680 #define RL_RET_CODE_INVLD_SYNTH_N_LIN (273U)
681 #define RL_RET_CODE_INVLD_SYNTH_MON_START_TIME (274U) /* MONITOR_START_TIME is outside the
682  specified range. */
683 #define RL_RET_CODE_INVLD_SYNTH_MON_LIN_RAM_ADDR (275U)
684 #define RL_RET_CODE_LDO_BYPASSED (279U) /* LDO fault inject is requested but
685  LDOs are bypassed */
686 #define RL_RET_CODE_INVLD_SIG_IMG_BAND_MONTR (280U) /* Signal and image band monitor is
687  not supported */
688 #define RL_RET_CODE_ANALOG_MONITOR_NOT_SUPPORTED (281U)
689 #define RL_RET_CODE_ISSUE_TO_ENABLE_CASCASE_MODE (282U) /* Device variant does not allow
690  cascading but API is issued to
691  enable cascading mode */
692 #define RL_RET_CODE_RX_SAT_MON_NOT_SUPPORTED (283U)
693 #define RL_API_NRESP_ANA_MON_MODE_NOT_API_BASED (284U) /* Monitoring trigger API is not
694  supported in autonomous mode
695  of operation */
696 #define RL_API_NRESP_ANA_MON_TRIG_TYPE_INVALID (285U) /* Monitoring trigger bit masks
697  are all zeros in
698  AWR_MONITOR_TYPE_TRIG_CONF_SB */
699 
700 #define RL_RET_CODE_CHIRP_FAIL (290U) /* Monitoring chirp error */
701 #define RL_RET_CODE_PD_PWR_LVL (291U) /* Loopback power measured by PD
702  is below -40 dBm */
703 #define RL_RET_CODE_ADC_PWR_LVL (292U) /* ADC power is higher than 7 dBm */
704 #define RL_RET_CODE_NOISE_FIG_LOW (293U) /* Noise figure is less than 0 */
705 #define RL_RET_CODE_PD_CDS_ON_FAIL (294U) /* PD measurement with RF on is less
706  than with RF off */
707 #define RL_RET_CODE_PGA_GAIN_FAIL (295U) /* Incorrect PGA gain for monitoring*/
708 #define RL_RET_CODE_20G_MONITOR_NOT_SUPPORTED (296U) /* The 20G monitor is not supported
709  in single chip configuration */
710 #define RL_RET_CODE_MONITOR_CONFIG_MODE_INVALID (297U) /* MONITOR_CONFIG_MODE is invalid. */
711 #define RL_RET_CODE_LIVE_NONLIVE_TOGETHER_INVALID (298U) /* Both Live and Non-live synth
712  frequency monitors are cannot be
713  enabled together. */
714 
715 /* Advanced Chirp config API */
716 #define RL_RET_CODE_CHIRP_PARAM_IND_INVALID (300U) /* Invalid CHIRP_PARAM_INDEX */
717 #define RL_RET_CODE_RESET_MODE_INVALID (301U) /* Invalid GLOBAL_RESET_MODE */
718 #define RL_RET_CODE_DEL_LUT_PAR_UPT_PER_INVALID (303U) /* Invalid update period
719  DELTA_PARAM_UPDATE_PERIOD or
720  LUT_PARAM_UPDATE_PERIOD */
721 #define RL_RET_CODE_SF_CHIRP_PAR_DEL_INVALID (304U) /* Invalid fixed delta parameter
722  SFn_CHIRP_PARAM_DELTA */
723 #define RL_RET_CODE_DEL_LUT_RESET_PERIOD_INVALID (305U) /* Invalid reset period
724  DELTA_RESET_PERIOD or
725  LUT_RESET_PERIOD*/
726 #define RL_RET_CODE_LUT_PAT_ADD_OFF_INVALID (306U) /* Invalid LUT address
727  LUT_PATTERN_ADDRESS_OFFSET */
728 #define RL_RET_CODE_LUT_NUM_PATTERNS_INVALID (307U) /* Invalid number of patterns in
729  LUT NUM_OF_PATTERNS */
730 #define RL_RET_CODE_LUT_SF_BURST_IND_OFF_INVALID (308U) /* Invalid LUT index offset value
731  BURST_LUT_INDEX_OFFSET or
732  SF_LUT_INDEX_OFFSET */
733 #define RL_RET_CODE_LUT_CHIRP_PAR_SCALE_SIZE_INVALID (309U) /* Invalid LUT_CHIRP_PARAM_SIZE and
734  LUT_CHIRP_PARAM_SCALE */
735 #define RL_RET_CODE_LEGACY_API_INPUTS_INVALID (310U) /* Invalid legacy APIs are issued
736  when advance chirp config API is
737  enabled or vice-versa */
738 #define RL_RET_CODE_ALL_CHIRP_PARAMS_NOT_DEFINED (311U) /* All chirp parameters are not
739  defined in advance chirp API */
740 #define RL_RET_CODE_TX_PHASE_SHIF_INT_INVALID (312U) /* Invalid TX phase shifter dither
741  value */
742 #define RL_RET_CODE_NUM_PATTERNS_PROGRAM_INVALID (313U) /* Insufficient number of
743  NUM_OF_PATTERNS programmed compared
744  to actual programmed chirps
745  (array out of bound error) */
746 #define RL_RET_CODE_NUM_CHIRPS_PROGRAM_INVALID (315U) /* Invalid num of chirps programmed
747  in frame config API */
748 #define RL_RET_CODE_TX_PH_SHIFT_PHASE_MASK_INVALID (316U) /* Invalid phase mask or at least one
749  of the phase should be enabled for
750  monitoring */
751 #define RL_RET_CODE_TX_PH_SHIFT_RX_MASK_INVALID (317U) /* Invalid RX mask or the RX mask is
752  not enabled in channel
753  configuration API */
754 
755 /* Advanced Chirp Generic LUT Load API */
756 #define RL_RET_CODE_NUM_BYTES_PROGRAM_INVALID (314U) /* Invalid num of bytes */
757 
758 #define RL_RET_CODE_TX_IND_PH_SHIFT_RESTORE_INVALID (318U) /* Invalid TX index in phase shifter
759  restore API */
760 
761 /* ADC Config API */
762 #define RL_RET_CODE_RX_CHAN_EN_OOR (1001U) /* numADCBits out of Range */
763 #define RL_RET_CODE_NUM_ADC_BITS_OOR (1002U) /* rxChannelEn out of Range */
764 #define RL_RET_CODE_ADC_OUT_FMT_OOR (1003U) /* adcOutFormat out of Range */
765 #define RL_RET_CODE_IQ_SWAP_SEL_OOR (1004U) /* sampleInterleave out of
766  Range */
767 #define RL_RET_CODE_CHAN_INTERLEAVE_OOR (1005U) /* channelInterleave out of
768  Range */
769 
770 /* Data Path Config API */
771 #define RL_RET_CODE_DATA_INTF_SEL_OOR (1006U) /* dataIntfSel out of Range */
772 #define RL_RET_CODE_DATA_FMT_PKT0_INVALID (1007U) /* dataTransPkt0Format
773  Unsupporetd */
774 #define RL_RET_CODE_DATA_FMT_PKT1_INVALID (1008U) /* dataTransPkt1Format
775  Unsupporetd */
776 
777 /* Lane Enable config API */
778 #define RL_RET_CODE_LANE_ENABLE_OOR (1009U) /* laneEnable is out of range */
779 #define RL_RET_CODE_LANE_ENABLE_INVALID (1010U) /* laneEnable is not supported */
780 
781 /* Lane Clock config API */
782 #define RL_RET_CODE_LANE_CLK_CFG_OOR (1011U) /* laneClkCfg is out of range */
783 #define RL_RET_CODE_LANE_CLK_CFG_INVALID (1012U) /* laneClkCfg is not supported */
784 #define RL_RET_CODE_DATA_RATE_OOR (1013U) /* dataRate is out of range */
785 
786 /* LVDS config API */
787 #define RL_RET_CODE_LANE_FMT_MAP_OOR (1014U) /* laneFmtMap is out of range */
788 #define RL_RET_CODE_LANE_PARAM_CFG_OOR (1015U) /* laneParamCfg is out of range */
789 
790 /* Continuous Streaming Mode API */
791 #define RL_RET_CODE_CONT_STREAM_MODE_OOR (1016U) /* contStreamMode is out of
792  range */
793 #define RL_RET_CODE_CONT_STREAM_MODE_INVALID (1017U) /* contStreamMode is already
794  in requested mode */
795 
796 /* CSI2 Lane Config API */
797 #define RL_RET_CODE_LANE0_POS_POL_OOR (1018U) /* lane0 pos is out of range */
798 #define RL_RET_CODE_LANE1_POS_POL_OOR (1019U) /* lane1 pos is out of range */
799 #define RL_RET_CODE_LANE2_POS_POL_OOR (1020U) /* lane2 pos is out of range */
800 #define RL_RET_CODE_LANE3_POS_POL_OOR (1021U) /* lane3 pos is out of range */
801 #define RL_RET_CODE_CLOCK_POS_OOR (1022U) /* ClockPos is out of range */
802 
803 /* Frame Config Apply API */
804 #define RL_RET_CODE_HALF_WORDS_PER_CHIRP_OOR (1023U) /* adcOutSize is out of range */
805 
806 /* Advanced Frame Config API */
807 #define RL_RET_CODE_NUM_SUBFRAMES_OOR (1024U) /* numSubFrames is out of range */
808 
809 #define RL_RET_CODE_SF1_TOT_NUM_CHIRPS_OOR (1025U) /* totNumChirps is out of range */
810 #define RL_RET_CODE_SF1_NUM_ADC_SAMP_OOR (1026U) /* numADCSamplesInPkt is out
811  of range */
812 #define RL_RET_CODE_SF1_NUM_CHIRPS_OOR (1027U) /* numChirpsInPkt is out of
813  range */
814 
815 #define RL_RET_CODE_SF2_TOT_NUM_CHIRPS_OOR (1028U) /* totNumChirps is out of
816  range */
817 #define RL_RET_CODE_SF2_NUM_ADC_SAMP_OOR (1029U) /* numADCSamplesInPkt is out
818  of range */
819 #define RL_RET_CODE_SF2_NUM_CHIRPS_OOR (1030U) /* numChirpsInPkt is out of
820  range */
821 
822 #define RL_RET_CODE_SF3_TOT_NUM_CHIRPS_OOR (1031U) /* totNumChirps is out of
823  range */
824 #define RL_RET_CODE_SF3_NUM_ADC_SAMP_OOR (1032U) /* numADCSamplesInPkt is out of
825  range */
826 #define RL_RET_CODE_SF3_NUM_CHIRPS_OOR (1033U) /* numChirpsInPkt is out of
827  range */
828 
829 #define RL_RET_CODE_SF4_TOT_NUM_CHIRPS_OOR (1034U) /* totNumChirps is out of
830  range */
831 #define RL_RET_CODE_SF4_NUM_ADC_SAMP_OOR (1035U) /* numADCSamplesInPkt is out of
832  range */
833 #define RL_RET_CODE_SF4_NUM_CHIRPS_OOR (1036U) /* numChirpsInPkt is out of range */
834 
835 #define RL_RET_CODE_MCUCLOCK_CTRL_OOR (1040U) /* mcuClkOutEn is out of range */
836 #define RL_RET_CODE_MCUCLOCK_SRC_OOR (1041U) /* mcuClkOutSrc is out of range */
837 
838 #define RL_RET_CODE_PMICCLOCK_CTRL_OOR (1042U) /* pmicClkOutEn is out of range */
839 #define RL_RET_CODE_PMICCLOCK_SRC_OOR (1043U) /* pmicClkOutSrc is out of range */
840 #define RL_RET_CODE_PMICMODE_SELECT_OOR (1044U) /* modeSel is out of range */
841 #define RL_RET_CODE_PMICFREQ_SLOPE_OOR (1045U) /* freqSlope is out of range */
842 #define RL_RET_CODE_PMICCLK_DITHER_EN_OOR (1046U) /* clkDitherEn is out of range */
843 
844 #define RL_RET_CODE_TESTPATTERN_EN_OOR (1047U) /* testPatternGenEn is out of
845  range */
846 #define RL_RET_CODE_LFAULTTEST_UNSUPPORTED_OOR (1048U) /* Data interface selected in
847  RL_DEV_RX_DATA_PATH_CONF_SET_SB
848  is SPI */
849 
850 #define RL_API_NRESP_LFAULTTEST_UNSUPPORTED_OOR (1051U) /* Unsupported Latent Fault test
851  selected in
852  RL_DEV_LATENTFAULT_TEST_CONF_SB */
853 #define RL_API_NRESP_DATACONFIG_NOTDONE (1052U) /* Invoking
854  AWR_DEV_ADV_FRAME_CONFIG_APPLY_SB
855  message without configuring
856  data path */
857 
863 #define RL_DISABLE_LOGGING 1
864 
865 /* mmwavelink MACROs for Error Checks */
866 #define RL_OSI_RET_CODE_OK (0)
867 #define RL_IF_RET_CODE_OK (0)
868 
869 #ifdef RL_EXTENDED_MESSAGE /* build time MACRO to change message size */
870 /* if mmWaveLink instance is running inside xWR1443/1642 device then Max size of packet can
871  be (2048 -4) bytes, where 4 bytes are reserved for mailbox header */
872 #define RL_MAX_SIZE_MSG (2044U)
873 #else
874 #define RL_MAX_SIZE_MSG (256U)
875 #endif
876 
877 
888 #define RL_DEVICE_MAP_NATIVE (0U)
889 #define RL_DEVICE_MAP_CASCADED_1 (1U)
890 #define RL_DEVICE_MAP_CASCADED_2 (2U)
891 #define RL_DEVICE_MAP_CASCADED_3 (4U)
892 #define RL_DEVICE_MAP_CASCADED_4 (8U)
894 /* AWR2243 Device Map - Max Cascading */
895 #define RL_DEVICE_MAP_CASCADED_ALL (RL_DEVICE_MAP_CASCADED_1 |\
896  RL_DEVICE_MAP_CASCADED_2 |\
897  RL_DEVICE_MAP_CASCADED_3 |\
898  RL_DEVICE_MAP_CASCADED_4)
899 
900 /* Device Index for SubSystem */
901 #define RL_DEVICE_INDEX_INTERNAL_BSS (0U)
902 #define RL_DEVICE_INDEX_INTERNAL_DSS_MSS (1U)
903 #define RL_DEVICE_INDEX_INTERNAL_HOST (2U)
906 #define RL_DEVICE_MAP_INTERNAL_BSS (RL_DEVICE_MAP_CASCADED_1)
908 #define RL_DEVICE_MAP_INTERNAL_DSS_MSS (RL_DEVICE_MAP_CASCADED_2)
909 #define RL_DEVICE_MAP_INTERNAL_HOST (RL_DEVICE_MAP_CASCADED_3)
912 #define RL_DEVICE_CONNECTED_MAX (4U)
913 
929 #ifndef RL_CASCADE_NUM_DEVICES
930 #define RL_CASCADE_NUM_DEVICES (1U)
931 #endif
932 
936 #define RL_CRC_TYPE_16BIT_CCITT (0U)
937 #define RL_CRC_TYPE_32BIT (1U)
938 #define RL_CRC_TYPE_64BIT_ISO (2U)
939 #define RL_CRC_TYPE_NO_CRC (3U)
944 #define RL_PLATFORM_HOST (0x0U)
945 #define RL_PLATFORM_MSS (0x1U)
946 #define RL_PLATFORM_DSS (0x2U)
951 #define RL_AR_DEVICETYPE_12XX (0x0U)
952 #define RL_AR_DEVICETYPE_14XX (0x1U)
953 #define RL_AR_DEVICETYPE_16XX (0x2U)
954 #define RL_AR_DEVICETYPE_18XX (0x3U)
955 #define RL_AR_DEVICETYPE_68XX (0x4U)
956 #define RL_AR_DEVICETYPE_22XX (0x5U)
961 #define RL_DBG_LEVEL_NONE ((rlUInt8_t)0U)
962 #define RL_DBG_LEVEL_ERROR ((rlUInt8_t)1U)
963 #define RL_DBG_LEVEL_WARNING ((rlUInt8_t)2U)
964 #define RL_DBG_LEVEL_INFO ((rlUInt8_t)3U)
965 #define RL_DBG_LEVEL_DEBUG ((rlUInt8_t)4U)
966 #define RL_DBG_LEVEL_VERBOSE ((rlUInt8_t)5U)
967 
971 #define RL_SENSOR_ANALOGTEST_ONE (0U)
972 #define RL_SENSOR_ANALOGTEST_TWO (1U)
973 #define RL_SENSOR_ANALOGTEST_THREE (2U)
974 #define RL_SENSOR_ANALOGTEST_FOUR (3U)
975 #define RL_SENSOR_ANAMUX (4U)
976 #define RL_SENSOR_VSENSE (5U)
977 #define RL_MAX_GPADC_SENSORS (6U)
978 
982 #define RL_SWAP_32(x) (((x) & 0x0000FFFFU)<<16U)|(((x) & 0xFFFF0000U)>>16U);
983 
984 /******************************************************************************
985  * TYPE-DEFINE STRUCT/ENUM/UNION DEFINITIONS
986  ******************************************************************************
987  */
988 
989 /* DesignId : MMWL_DesignId_001 */
990 /* Requirements : AUTORADAR_REQ-697, AUTORADAR_REQ-698, AUTORADAR_REQ-699, AUTORADAR_REQ-700,
991  AUTORADAR_REQ-701, AUTORADAR_REQ-702, AUTORADAR_REQ-703, AUTORADAR_REQ-704,
992  AUTORADAR_REQ-705, AUTORADAR_REQ-706, AUTORADAR_REQ-830, AUTORADAR_REQ-831,
993  AUTORADAR_REQ-832, AUTORADAR_REQ-888, AUTORADAR_REQ-889, AUTORADAR_REQ-890
994 */
995 
999 typedef rlInt32_t rlReturnVal_t;
1000 
1004 typedef rlUInt8_t rlCrcType_t;
1005 
1006 /* Function pointers for spawn task function and event handlers*/
1007 
1011 typedef void (*RL_P_OSI_SPAWN_ENTRY)(const void* pValue);
1012 
1016 typedef void (*RL_P_EVENT_HANDLER)(rlUInt8_t deviceIndex, void* pValue);
1017 
1021 typedef struct rlComIfCbs
1022 {
1033  /* DesignId : MMWL_DesignId_004 */
1034  /* Requirements : AUTORADAR_REQ-785 */
1035  rlComIfHdl_t (*rlComIfOpen)(rlUInt8_t deviceIndex, rlUInt32_t flags);
1036 
1048  /* DesignId : MMWL_DesignId_004 */
1049  /* Requirements : AUTORADAR_REQ-785 */
1050  rlInt32_t (*rlComIfRead)(rlComIfHdl_t fd, rlUInt8_t *pBuff, rlUInt16_t len);
1051 
1063  /* DesignId : */
1064  /* Requirements : AUTORADAR_REQ-785 */
1065  rlInt32_t (*rlComIfWrite)(rlComIfHdl_t fd, rlUInt8_t *pBuff, rlUInt16_t len);
1066 
1076  /* DesignId : MMWL_DesignId_004 */
1077  /* Requirements : AUTORADAR_REQ-785 */
1078  rlInt32_t (*rlComIfClose)(rlComIfHdl_t fd);
1079 }rlComIfCbs_t;
1080 
1084 typedef struct rlOsiMutexCbs
1085 {
1096  /* DesignId : MMWL_DesignId_004 */
1097  /* Requirements : AUTORADAR_REQ-784 */
1098  rlInt32_t (*rlOsiMutexCreate)(rlOsiMutexHdl_t* mutexHdl, rlInt8_t* name);
1099 
1122  /* DesignId : MMWL_DesignId_004 */
1123  /* Requirements : AUTORADAR_REQ-784 */
1124  rlInt32_t (*rlOsiMutexLock)(rlOsiMutexHdl_t* mutexHdl, rlOsiTime_t timeout);
1125 
1136  /* DesignId : MMWL_DesignId_004 */
1137  /* Requirements : AUTORADAR_REQ-784 */
1138  rlInt32_t (*rlOsiMutexUnLock)(rlOsiMutexHdl_t* mutexHdl);
1139 
1149  /* DesignId : MMWL_DesignId_004 */
1150  /* Requirements : AUTORADAR_REQ-784 */
1151  rlInt32_t (*rlOsiMutexDelete)(rlOsiMutexHdl_t* mutexHdl);
1153 
1157 typedef struct rlOsiSemCbs
1158 {
1169  /* DesignId : MMWL_DesignId_004 */
1170  /* Requirements : AUTORADAR_REQ-784 */
1171  rlInt32_t (*rlOsiSemCreate)(rlOsiSemHdl_t* semHdl, rlInt8_t* name);
1172 
1183  /* DesignId : MMWL_DesignId_004 */
1184  /* Requirements : AUTORADAR_REQ-784 */
1185  rlInt32_t (*rlOsiSemWait)(rlOsiSemHdl_t* semHdl, rlOsiTime_t timeout);
1186 
1196  /* DesignId : MMWL_DesignId_004 */
1197  /* Requirements : AUTORADAR_REQ-784 */
1198  rlInt32_t (*rlOsiSemSignal)(rlOsiSemHdl_t* semHdl);
1199 
1209  /* DesignId : MMWL_DesignId_004 */
1210  /* Requirements : AUTORADAR_REQ-784 */
1211  rlInt32_t (*rlOsiSemDelete)(rlOsiSemHdl_t* semHdl);
1212 }rlOsiSemCbs_t;
1213 
1217 typedef struct rlOsiMsgQCbs
1218 {
1234  /* DesignId : MMWL_DesignId_004 */
1235  /* Requirements : AUTORADAR_REQ-784 */
1236  rlInt32_t (*rlOsiSpawn)(RL_P_OSI_SPAWN_ENTRY pEntry, const void* pValue, rlUInt32_t flags);
1238 
1239 
1243 typedef struct rlOsiCbs
1244 {
1248  rlOsiMutexCbs_t mutex;
1252  rlOsiSemCbs_t sem;
1256  rlOsiMsgQCbs_t queue;
1257 }rlOsiCbs_t;
1258 
1262 typedef struct rlEventCbs
1263 {
1277  /* DesignId : MMWL_DesignId_004 */
1278  /* Requirements : AUTORADAR_REQ-783 */
1279  void (*rlAsyncEvent)(rlUInt8_t devIndex, rlUInt16_t subId, rlUInt16_t subLen,
1280  rlUInt8_t *payload);
1281 }rlEventCbs_t;
1286 typedef struct rlTimerCbs
1287 {
1288  rlInt32_t (*rlDelay)(rlUInt32_t delay);
1290 
1294 typedef struct rlCmdParserCbs
1295 {
1296  rlInt32_t (*rlCmdParser)(rlUInt8_t rxMsgClass, rlInt32_t inVal);
1297  rlInt32_t (*rlPostCnysStep)(rlUInt8_t devIndex);
1299 
1306 typedef struct rlCrcCbs
1307 {
1322  /* DesignId : */
1323  /* Requirements : */
1324  rlInt32_t (*rlComputeCRC)(rlUInt8_t* data, rlUInt32_t dataLen, rlUInt8_t crcType,
1325  rlUInt8_t* crc);
1326 }rlCrcCbs_t;
1327 
1331 typedef struct rlDeviceCtrlCbs
1332 {
1343  /* DesignId : MMWL_DesignId_004 */
1344  /* Requirements : AUTORADAR_REQ-786 */
1345  rlInt32_t (*rlDeviceEnable)(rlUInt8_t deviceIndex);
1346 
1357  /* DesignId : MMWL_DesignId_004 */
1358  /* Requirements : AUTORADAR_REQ-786 */
1359  rlInt32_t (*rlDeviceDisable)(rlUInt8_t deviceIndex);
1360 
1369  /* DesignId : MMWL_DesignId_004 */
1370  /* Requirements : AUTORADAR_REQ-787 */
1371  void (*rlDeviceMaskHostIrq)(rlComIfHdl_t fd);
1372 
1381  /* DesignId : MMWL_DesignId_004 */
1382  /* Requirements : AUTORADAR_REQ-787 */
1383  void (*rlDeviceUnMaskHostIrq)(rlComIfHdl_t fd);
1384 
1400  /* DesignId :MMWL_DesignId_004 */
1401  /* Requirements : AUTORADAR_REQ-787 */
1402  rlInt32_t (*rlDeviceWaitIrqStatus)(rlComIfHdl_t fd, rlUInt8_t highLow);
1403 
1413  /* DesignId : MMWL_DesignId_004 */
1414  /* Requirements : AUTORADAR_REQ-787 */
1415  rlUInt16_t (*rlCommIfAssertIrq)(rlUInt8_t highLow);
1416 
1432  /* DesignId : MMWL_DesignId_026 */
1433  /* Requirements : AUTORADAR_REQ-777 */
1434  rlInt32_t (*rlRegisterInterruptHandler)(rlUInt8_t deviceIndex,
1435  RL_P_EVENT_HANDLER pHandler, void* pValue);
1440 typedef rlInt32_t (*rlPrintFptr)(const rlInt8_t* format, ...);
1441 
1445 typedef struct rlDbgCb
1446 {
1458  /* DesignId : */
1459  /* Requirements : */
1460  rlPrintFptr rlPrint;
1464  rlUInt8_t dbgLevel;
1465 }rlDbgCb_t;
1466 
1470 typedef struct rlClientCbs
1471 {
1475  rlComIfCbs_t comIfCb;
1479  rlOsiCbs_t osiCb;
1483  rlEventCbs_t eventCb;
1487  rlDeviceCtrlCbs_t devCtrlCb;
1491  rlTimerCbs_t timerCb;
1496  rlCmdParserCbs_t cmdParserCb;
1500  rlCrcCbs_t crcCb;
1504  rlCrcType_t crcType;
1510  rlUInt32_t ackTimeout;
1516  rlUInt8_t platform;
1521  rlUInt8_t arDevType;
1525  rlDbgCb_t dbgCb;
1526 }rlClientCbs_t;
1527 
1533 typedef struct rlInitComplete
1534 {
1538  rlUInt32_t powerUpTime;
1594  rlUInt64_t powerUpStatus;
1637  rlUInt64_t bootTestStatus;
1639 
1644 typedef struct rlStartComplete
1645 {
1678  rlUInt32_t status;
1682  rlUInt32_t powerUpTime;
1686  rlUInt32_t reserved0;
1690  rlUInt32_t reserved1;
1692 
1700 typedef struct rlMssEsmFault
1701 {
1737  rlUInt32_t esmGrp1Err;
1773  rlUInt32_t esmGrp2Err;
1777  rlUInt32_t reserved0;
1781  rlUInt32_t reserved1;
1783 
1790 typedef struct rlMssBootErrStatus
1791 {
1795  rlUInt32_t powerUpTime;
1851  rlUInt64_t powerUpStatus;
1894  rlUInt64_t bootTestStatus;
1896 
1901 typedef struct rlMssLatentFaultReport
1902 {
1939  rlUInt32_t testStatusFlg1;
1950  rlUInt32_t testStatusFlg2;
1954  rlUInt32_t reserved;
1956 
1962 typedef struct rlMssPeriodicTestStatus
1963 {
1971  rlUInt32_t testStatusFlg;
1975  rlUInt32_t reserved;
1977 
1983 typedef struct rlMssRfErrStatus
1984 {
1996  rlUInt32_t errStatusFlg;
2000  rlUInt32_t reserved;
2002 
2009 typedef struct rlBssEsmFault
2010 {
2038  rlUInt32_t esmGrp1Err;
2074  rlUInt32_t esmGrp2Err;
2076 
2080 typedef struct rlRfInitComplete
2081 {
2102  rlUInt32_t calibStatus;
2107  rlUInt32_t calibUpdate;
2113  rlUInt16_t temperature;
2117  rlUInt16_t reserved0;
2123  rlUInt32_t timeStamp;
2127  rlUInt32_t reserved1;
2129 
2133 typedef struct rlRfRunTimeCalibReport
2134 {
2154  rlUInt32_t calibErrorFlag;
2160  rlUInt32_t calibUpdateStatus;
2166  rlInt16_t temperature;
2170  rlUInt16_t reserved0;
2176  rlUInt32_t timeStamp;
2180  rlUInt32_t reserved1;
2182 
2192 typedef struct rlMonTypeTrigDoneStatus
2193 {
2194 #ifndef MMWL_BIG_ENDIAN
2203  rlUInt8_t monTrigTypeDone;
2207  rlUInt8_t reserved0;
2208 #else
2209 
2212  rlUInt8_t reserved0;
2221  rlUInt8_t monTrigTypeDone;
2222 #endif
2223 
2226  rlUInt16_t reserved1;
2231  rlUInt32_t timeStamp;
2235  rlUInt32_t reserved2;
2237 
2241 typedef struct rlRfApllCalDone
2242 {
2243  rlUInt16_t apllClCalStatus;
2247  rlUInt16_t cccTolerance;
2251  rlUInt16_t cccCount0;
2255  rlUInt16_t measFreqCount;
2259  rlUInt32_t cccCount1;
2261 
2270 typedef struct rlCpuFault
2271 {
2272 #ifndef MMWL_BIG_ENDIAN
2284  rlUInt8_t faultType;
2301  rlUInt8_t errorCode;
2302 #else
2303 
2319  rlUInt8_t errorCode;
2331  rlUInt8_t faultType;
2332 #endif
2333 
2337  rlUInt16_t lineNum;
2342  rlUInt32_t faultLR;
2348  rlUInt32_t faultPrevLR;
2353  rlUInt32_t faultSpsr;
2357  rlUInt32_t faultSp;
2362  rlUInt32_t faultAddr;
2375  rlUInt16_t faultErrStatus;
2376 #ifndef MMWL_BIG_ENDIAN
2377 
2383  rlUInt8_t faultErrSrc;
2389  rlUInt8_t faultAxiErrType;
2395  rlUInt8_t faultAccType;
2402  rlUInt8_t faultRecovType;
2403 #else
2404 
2409  rlUInt8_t faultAxiErrType;
2416  rlUInt8_t faultErrSrc;
2423  rlUInt8_t faultRecovType;
2429  rlUInt8_t faultAccType;
2430 #endif
2431 
2434  rlUInt16_t reserved1;
2435 }rlCpuFault_t;
2436 
2440 typedef struct rlFwVersionParam
2441 {
2442 #ifndef MMWL_BIG_ENDIAN
2446  rlUInt8_t hwVarient;
2450  rlUInt8_t hwMajor;
2454  rlUInt8_t hwMinor;
2458  rlUInt8_t fwMajor;
2462  rlUInt8_t fwMinor;
2466  rlUInt8_t fwBuild;
2470  rlUInt8_t fwDebug;
2474  rlUInt8_t fwYear;
2478  rlUInt8_t fwMonth;
2482  rlUInt8_t fwDay;
2486  rlUInt8_t patchMajor;
2490  rlUInt8_t patchMinor;
2494  rlUInt8_t patchYear;
2498  rlUInt8_t patchMonth;
2502  rlUInt8_t patchDay;
2508  rlUInt8_t patchBuildDebug;
2509 #else
2510 
2513  rlUInt8_t hwMajor;
2517  rlUInt8_t hwVarient;
2521  rlUInt8_t fwMajor;
2525  rlUInt8_t hwMinor;
2529  rlUInt8_t fwBuild;
2533  rlUInt8_t fwMinor;
2537  rlUInt8_t fwYear;
2541  rlUInt8_t fwDebug;
2545  rlUInt8_t fwDay;
2549  rlUInt8_t fwMonth;
2553  rlUInt8_t patchMinor;
2557  rlUInt8_t patchMajor;
2561  rlUInt8_t patchMonth;
2565  rlUInt8_t patchYear;
2571  rlUInt8_t patchBuildDebug;
2575  rlUInt8_t patchDay;
2576 #endif
2578 
2582 typedef struct rlSwVersionParam
2583 {
2584 #ifndef MMWL_BIG_ENDIAN
2588  rlUInt8_t major;
2592  rlUInt8_t minor;
2596  rlUInt8_t build;
2600  rlUInt8_t debug;
2604  rlUInt8_t year;
2608  rlUInt8_t month;
2612  rlUInt8_t day;
2616  rlUInt8_t reserved;
2617 #else
2618 
2621  rlUInt8_t minor;
2625  rlUInt8_t major;
2629  rlUInt8_t debug;
2633  rlUInt8_t build;
2637  rlUInt8_t month;
2641  rlUInt8_t year;
2645  rlUInt8_t reserved;
2649  rlUInt8_t day;
2650 #endif
2652 
2656 typedef struct rlVersion
2657 {
2661  rlFwVersionParam_t master;
2665  rlFwVersionParam_t rf;
2669  rlSwVersionParam_t mmWaveLink;
2670 }rlVersion_t;
2671 
2675 typedef struct rlGpAdcData
2676 {
2680  rlUInt16_t min;
2684  rlUInt16_t max;
2688  rlUInt16_t avg;
2689 } rlGpAdcData_t;
2690 
2694 typedef struct rlRecvdGpAdcData
2695 {
2699  rlGpAdcData_t sensor[RL_MAX_GPADC_SENSORS];
2703  rlUInt16_t reserved0[4U];
2707  rlUInt32_t reserved1[7U];
2709 
2713 typedef struct rlAnalogFaultReportData
2714 {
2715 #ifndef MMWL_BIG_ENDIAN
2723  rlUInt8_t faultType;
2727  rlUInt8_t reserved0;
2728 #else
2729 
2732  rlUInt8_t reserved0;
2740  rlUInt8_t faultType;
2741 #endif
2742 
2745  rlUInt16_t reserved1;
2755  rlUInt32_t faultSig;
2759  rlUInt32_t reserved2;
2761 
2766 typedef struct rlCalMonTimingErrorReportData
2767 {
2780  rlUInt16_t timingFailCode;
2781  rlUInt16_t reserved;
2787 typedef struct rlDigLatentFaultReportData
2788 {
2820  rlUInt32_t digMonLatentFault;
2822 
2827 typedef struct rlMonReportHdrData
2828 {
2832  rlUInt32_t fttiCount;
2837  rlUInt16_t avgTemp;
2841  rlUInt16_t reserved0;
2845  rlUInt32_t reserved1;
2847 
2852 typedef struct rlDigPeriodicReportData
2853 {
2863  rlUInt32_t digMonPeriodicStatus;
2869  rlUInt32_t timeStamp;
2871 
2878 typedef struct rlMonTempReportData
2879 {
2892  rlUInt16_t statusFlags;
2896  rlUInt16_t errorCode;
2914  rlInt16_t tempValues[10U];
2918  rlUInt32_t reserved;
2924  rlUInt32_t timeStamp;
2926 
2934 typedef struct rlMonRxGainPhRep
2935 {
2947  rlUInt16_t statusFlags;
2951  rlUInt16_t errorCode;
2952 #ifndef MMWL_BIG_ENDIAN
2953 
2956  rlUInt8_t profIndex;
2967  rlUInt8_t loopbackPowerRF1;
2979  rlUInt8_t loopbackPowerRF2;
2990  rlUInt8_t loopbackPowerRF3;
2991 #else
2992 
3002  rlUInt8_t loopbackPowerRF1;
3006  rlUInt8_t profIndex;
3017  rlUInt8_t loopbackPowerRF3;
3028  rlUInt8_t loopbackPowerRF2;
3029 #endif
3030 
3056  rlUInt16_t rxGainVal[12U];
3071  rlUInt16_t rxPhaseVal[12U];
3094  rlUInt32_t rxNoisePower1;
3117  rlUInt32_t rxNoisePower2;
3123  rlUInt32_t timeStamp;
3125 
3133 typedef struct rlMonRxNoiseFigRep
3134 {
3143  rlUInt16_t statusFlags;
3147  rlUInt16_t errorCode;
3148 #ifndef MMWL_BIG_ENDIAN
3149 
3152  rlUInt8_t profIndex;
3156  rlUInt8_t reserved0;
3157 #else
3158 
3161  rlUInt8_t reserved0;
3165  rlUInt8_t profIndex;
3166 #endif
3167 
3170  rlUInt16_t reserved1;
3184  rlUInt16_t rxNoiseFigVal[12U];
3188  rlUInt32_t reserved2;
3192  rlUInt32_t reserved3;
3196  rlUInt32_t reserved4;
3202  rlUInt32_t timeStamp;
3204 
3211 typedef struct rlMonRxIfStageRep
3212 {
3223  rlUInt16_t statusFlags;
3227  rlUInt16_t errorCode;
3228 #ifndef MMWL_BIG_ENDIAN
3229 
3232  rlUInt8_t profIndex;
3236  rlUInt8_t reserved0;
3237 #else
3238 
3241  rlUInt8_t reserved0;
3245  rlUInt8_t profIndex;
3246 #endif
3247 
3257  rlInt16_t lpfCutOffBandEdgeDroopValRx0;
3258 #ifndef MMWL_BIG_ENDIAN
3259 
3275  rlInt8_t hpfCutOffFreqEr[8U];
3289  rlInt8_t lpfCutOffStopBandAtten[8U];
3303  rlInt8_t rxIfaGainErVal[8U];
3308  rlInt8_t ifGainExp;
3312  rlUInt8_t reserved2;
3325  rlInt8_t lpfCutOffBandEdgeDroopValRx[6U];
3326 #else
3327 
3343  rlInt8_t hpfCutOffFreqEr[8U];
3357  rlInt8_t lpfCutOffStopBandAtten[8U];
3371  rlInt8_t rxIfaGainErVal[8U];
3375  rlUInt8_t reserved2;
3380  rlInt8_t ifGainExp;
3393  rlInt8_t lpfCutOffBandEdgeDroopValRx[6U];
3394 #endif
3395 
3399  rlUInt32_t timeStamp;
3401 
3409 typedef struct rlMonTxPowRep
3410 {
3420  rlUInt16_t statusFlags;
3424  rlUInt16_t errorCode;
3425 #ifndef MMWL_BIG_ENDIAN
3426 
3429  rlUInt8_t profIndex;
3433  rlUInt8_t reserved0;
3434 #else
3435 
3438  rlUInt8_t reserved0;
3442  rlUInt8_t profIndex;
3443 #endif
3444 
3447  rlUInt16_t reserved1;
3459  rlInt16_t txPowVal[3U];
3463  rlUInt16_t reserved2;
3469  rlUInt32_t timeStamp;
3471 
3480 typedef struct rlMonTxBallBreakRep
3481 {
3490  rlUInt16_t statusFlags;
3494  rlUInt16_t errorCode;
3499  rlInt16_t txReflCoefVal;
3503  rlUInt16_t reserved0;
3507  rlUInt32_t reserved1;
3513  rlUInt32_t timeStamp;
3515 
3522 typedef struct rlMonTxGainPhaMisRep
3523 {
3533  rlUInt16_t statusFlags;
3537  rlUInt16_t errorCode;
3538 #ifndef MMWL_BIG_ENDIAN
3539 
3542  rlUInt8_t profIndex;
3546  rlUInt8_t noisePower00;
3550  rlUInt8_t noisePower01;
3554  rlUInt8_t noisePower02;
3555 #else
3556 
3559  rlUInt8_t noisePower00;
3563  rlUInt8_t profIndex;
3567  rlUInt8_t noisePower02;
3571  rlUInt8_t noisePower01;
3572 #endif
3573 
3585  rlInt16_t txGainVal[9U];
3599  rlUInt16_t txPhaVal[9U];
3600 #ifndef MMWL_BIG_ENDIAN
3601 
3604  rlUInt8_t noisePower10;
3608  rlUInt8_t noisePower11;
3612  rlUInt8_t noisePower12;
3616  rlUInt8_t noisePower20;
3620  rlUInt8_t noisePower21;
3624  rlUInt8_t noisePower22;
3628  rlUInt8_t reserved0;
3632  rlUInt8_t reserved1;
3633 #else
3634 
3637  rlUInt8_t noisePower11;
3641  rlUInt8_t noisePower10;
3645  rlUInt8_t noisePower20;
3649  rlUInt8_t noisePower12;
3653  rlUInt8_t noisePower22;
3657  rlUInt8_t noisePower21;
3661  rlUInt8_t reserved1;
3665  rlUInt8_t reserved0;
3666 #endif
3667 
3671  rlUInt32_t timeStamp;
3673 
3681 typedef struct rlMonTxPhShiftRep
3682 {
3692  rlUInt16_t statusFlags;
3696  rlUInt16_t errorCode;
3697 #ifndef MMWL_BIG_ENDIAN
3698 
3701  rlUInt8_t profIndex;
3705  rlUInt8_t reserved0;
3706 #else
3707 
3710  rlUInt8_t reserved0;
3714  rlUInt8_t profIndex;
3715 #endif
3716 
3719  rlUInt16_t reserved1;
3725  rlUInt16_t phaseShifterMonVal1;
3731  rlUInt16_t phaseShifterMonVal2;
3737  rlUInt16_t phaseShifterMonVal3;
3743  rlUInt16_t phaseShifterMonVal4;
3749  rlInt16_t txPsAmplitudeVal1;
3755  rlInt16_t txPsAmplitudeVal2;
3761  rlInt16_t txPsAmplitudeVal3;
3767  rlInt16_t txPsAmplitudeVal4;
3768 #ifndef MMWL_BIG_ENDIAN
3769 
3774  rlInt8_t txPsNoiseVal1;
3780  rlInt8_t txPsNoiseVal2;
3786  rlInt8_t txPsNoiseVal3;
3792  rlInt8_t txPsNoiseVal4;
3793 #else
3794 
3799  rlInt8_t txPsNoiseVal2;
3805  rlInt8_t txPsNoiseVal1;
3811  rlInt8_t txPsNoiseVal4;
3817  rlInt8_t txPsNoiseVal3;
3818 #endif
3819 
3824  rlUInt32_t timeStamp;
3828  rlUInt32_t reserved2;
3832  rlUInt32_t reserved3;
3834 
3841 typedef struct rlMonSynthFreqRep
3842 {
3851  rlUInt16_t statusFlags;
3855  rlUInt16_t errorCode;
3856 #ifndef MMWL_BIG_ENDIAN
3857 
3860  rlUInt8_t profIndex;
3864  rlUInt8_t reserved0;
3865 #else
3866 
3869  rlUInt8_t reserved0;
3873  rlUInt8_t profIndex;
3874 #endif
3875 
3878  rlUInt16_t reserved1;
3886  rlInt32_t maxFreqErVal;
3896  rlUInt32_t freqFailCnt;
3900  rlUInt32_t reserved2;
3904  rlUInt32_t reserved3;
3910  rlUInt32_t timeStamp;
3912 
3919 typedef struct rlMonExtAnaSigRep
3920 {
3934  rlUInt16_t statusFlags;
3938  rlUInt16_t errorCode;
3950  rlInt16_t extAnaSigVal[6U];
3954  rlUInt32_t reserved;
3960  rlUInt32_t timeStamp;
3962 
3969 typedef struct rlMonTxIntAnaSigRep
3970 {
3980  rlUInt16_t statusFlags;
3984  rlUInt16_t errorCode;
3985 #ifndef MMWL_BIG_ENDIAN
3986 
3989  rlUInt8_t profIndex;
3993  rlUInt8_t reserved0;
3998  rlUInt8_t phShiftDacIdeltaMin;
4003  rlUInt8_t phShiftDacQdeltaMin;
4004 #else
4005 
4008  rlUInt8_t reserved0;
4012  rlUInt8_t profIndex;
4017  rlUInt8_t phShiftDacQdeltaMin;
4022  rlUInt8_t phShiftDacIdeltaMin;
4023 #endif
4024 
4029  rlUInt32_t timeStamp;
4031 
4038 typedef struct rlMonRxIntAnaSigRep
4039 {
4055  rlUInt16_t statusFlags;
4059  rlUInt16_t errorCode;
4060 #ifndef MMWL_BIG_ENDIAN
4061 
4064  rlUInt8_t profIndex;
4068  rlUInt8_t reserved0;
4069 #else
4070 
4073  rlUInt8_t reserved0;
4077  rlUInt8_t profIndex;
4078 #endif
4079 
4082  rlUInt16_t reserved1;
4088  rlUInt32_t timeStamp;
4090 
4097 typedef struct rlMonPmclkloIntAnaSigRep
4098 {
4111  rlUInt16_t statusFlags;
4115  rlUInt16_t errorCode;
4116 #ifndef MMWL_BIG_ENDIAN
4117 
4120  rlUInt8_t profIndex;
4126  rlInt8_t sync20GPower;
4127 #else
4128 
4133  rlInt8_t sync20GPower;
4137  rlUInt8_t profIndex;
4138 #endif
4139 
4142  rlUInt16_t reserved;
4148  rlUInt32_t timeStamp;
4150 
4158 typedef struct rlMonGpadcIntAnaSigRep
4159 {
4169  rlUInt16_t statusFlags;
4173  rlUInt16_t errorCode;
4179  rlInt16_t gpadcRef1Val;
4185  rlUInt16_t gpadcRef2Val;
4189  rlUInt32_t reserved;
4195  rlUInt32_t timeStamp;
4197 
4204 typedef struct rlMonPllConVoltRep
4205 {
4220  rlUInt16_t statusFlags;
4224  rlUInt16_t errorCode;
4245  rlInt16_t pllContVoltVal[8U];
4249  rlUInt32_t reserved;
4255  rlUInt32_t timeStamp;
4257 
4264 typedef struct rlMonDccClkFreqRep
4265 {
4278  rlUInt16_t statusFlags;
4282  rlUInt16_t errorCode;
4296  rlUInt16_t freqMeasVal[8U];
4300  rlUInt32_t reserved;
4306  rlUInt32_t timeStamp;
4308 
4316 typedef struct rlMonRxMixrInPwrRep
4317 {
4329  rlUInt16_t statusFlags;
4333  rlUInt16_t errorCode;
4334 
4335 #ifndef MMWL_BIG_ENDIAN
4339  rlUInt8_t profIndex;
4343  rlUInt8_t reserved0;
4344 #else
4345 
4348  rlUInt8_t reserved0;
4352  rlUInt8_t profIndex;
4353 #endif
4354 
4357  rlUInt16_t reserved1;
4370  rlUInt32_t rxMixInVolt;
4374  rlUInt32_t reserved2;
4379  rlUInt32_t timeStamp;
4381 
4389 typedef struct rlMonSynthFreqNonLiveRep
4390 {
4400  rlUInt16_t statusFlags;
4404  rlUInt16_t errorCode;
4405 
4406 #ifndef MMWL_BIG_ENDIAN
4410  rlUInt8_t profIndex0;
4414  rlUInt8_t reserved0;
4415 #else
4416 
4419  rlUInt8_t reserved0;
4423  rlUInt8_t profIndex0;
4424 #endif
4425 
4428  rlUInt16_t reserved1;
4436  rlInt32_t maxFreqErVal0;
4446  rlUInt32_t freqFailCnt0;
4452  rlUInt32_t maxFreqFailTime0;
4456  rlUInt32_t reserved2;
4457 
4458 #ifndef MMWL_BIG_ENDIAN
4462  rlUInt8_t profIndex1;
4466  rlUInt8_t reserved3;
4467 #else
4468 
4471  rlUInt8_t reserved3;
4475  rlUInt8_t profIndex1;
4476 #endif
4477 
4480  rlUInt16_t reserved4;
4488  rlInt32_t maxFreqErVal1;
4498  rlUInt32_t freqFailCnt1;
4504  rlUInt32_t maxFreqFailTime1;
4508  rlUInt32_t reserved5;
4509 
4514  rlUInt32_t timeStamp;
4516 
4526 typedef struct rlMmwlErrorStatus
4527 {
4528  rlInt32_t errorVal;
4530 
4531 #include <ti/control/mmwavelink/include/rl_device.h>
4532 #include <ti/control/mmwavelink/include/rl_sensor.h>
4533 #include <ti/control/mmwavelink/include/rl_monitoring.h>
4534 #include <ti/control/mmwavelink/include/rl_protocol.h>
4535 #include <ti/control/mmwavelink/include/rl_messages.h>
4536 
4537 
4538 /******************************************************************************
4539  * FUNCTION PROTOTYPES
4540  ******************************************************************************
4541  */
4542 
4543 #ifdef __cplusplus
4544 }
4545 #endif
4546 
4547 #endif
4548 /*
4549  * END OF MMWAVELINK_H
4550  */
4551 
This is the Monitoring report which RadarSS sends to the host, containing information about the relat...
Definition: mmwavelink.h:4267
mmWaveLink RF Run time calibration report for event RL_RF_AE_RUN_TIME_CALIB_REPORT_SB
Definition: mmwavelink.h:2136
This async event is sent periodically to indicate the status of periodic digital monitoring tests....
Definition: mmwavelink.h:2855
mmWaveLink client callback structure
Definition: mmwavelink.h:1473
This is the Monitoring report which RadarSS sends to the host, containing the measured RX noise figur...
Definition: mmwavelink.h:3136
mmWaveLink RF Init Complete data structure for event RL_RF_AE_INITCALIBSTATUS_SB
Definition: mmwavelink.h:2083
Sensors GPADC measurement data for event RL_RF_AE_GPADC_MEAS_DATA_SB.
Definition: mmwavelink.h:2697
Structure to hold the BSS ESM Fault data strucutre for event RL_RF_AE_ESMFAULT_SB.
Definition: mmwavelink.h:2012
mmWaveLink firmware version structure
Definition: mmwavelink.h:2443
Structure to hold the test status report of the latent fault tests data strucutre for event RL_DEV_AE...
Definition: mmwavelink.h:1904
mmWaveLink Report for event RL_RF_AE_MONITOR_TYPE_TRIGGER_DONE_SB. The triggered monitor types are do...
Definition: mmwavelink.h:2195
Communication interface(SPI, MailBox, UART etc) callback functions.
Definition: mmwavelink.h:1024
mmWaveLink CRC callback function
Definition: mmwavelink.h:1309
Calibration monitoring timing error data for event RL_RF_AE_MON_TIMING_FAIL_REPORT_SB.
Definition: mmwavelink.h:2769
This is the Monitoring report which RadarSS sends to the host, containing the measured temperature ne...
Definition: mmwavelink.h:2881
mmWaveLink Init Complete data structure for event RL_DEV_AE_MSSPOWERUPDONE_SB
Definition: mmwavelink.h:1536
This is the Monitoring report which RadarSS sends to the host, containing information about Internal ...
Definition: mmwavelink.h:4100
This API is a Monitoring report which RadarSS sends to the host, containing the measured RX gain and ...
Definition: mmwavelink.h:2937
This is an error status report internally generated from mmWaveLink when it finds any issue with the ...
Definition: mmwavelink.h:4529
This is the Monitoring report which RadarSS sends to the host, containing the measured TX reflection ...
Definition: mmwavelink.h:3483
This is the Monitoring report which RadarSS sends to the host, containing information about the measu...
Definition: mmwavelink.h:4161
This is the Monitoring report which the AWR device sends to the host, containing the measured TX phas...
Definition: mmwavelink.h:3684
OS semaphore callback functions.
Definition: mmwavelink.h:1160
mmWaveLink Device Control, Interrupt callback functions
Definition: mmwavelink.h:1334
This is the Monitoring report which RadarSS sends to the host, containing information related to meas...
Definition: mmwavelink.h:3844
mmWaveLink Timer callback functions
Definition: mmwavelink.h:1289
mmWaveLink debug callback structure
Definition: mmwavelink.h:1448
Analog fault strucure for event RL_RF_AE_ANALOG_FAULT_SB.
Definition: mmwavelink.h:2716
This is the Monitoring report which RadarSS sends to the host, containing the measured Tx gain and ph...
Definition: mmwavelink.h:3525
API APLL closed loop cal Status Get Sub block structure.
Definition: mmwavelink.h:2244
This is the Monitoring report which RadarSS sends to the host, containing information about Internal ...
Definition: mmwavelink.h:3972
This is the Monitoring report which RadarSS sends to the host, containing information about Internal ...
Definition: mmwavelink.h:4041
Structure to hold data strucutre for RF-error status send by MSS for event RL_DEV_AE_MSS_RF_ERROR_STA...
Definition: mmwavelink.h:1986
Latent fault digital monitoring status data for event RL_RF_AE_DIG_LATENTFAULT_REPORT_AE_SB.
Definition: mmwavelink.h:2790
This is the Monitoring report which RadarSS sends to the host, containing the measured PLL control vo...
Definition: mmwavelink.h:4207
GPADC measurement data for sensors.
Definition: mmwavelink.h:2678
This is a Non live Monitoring report which device sends to the host, containing information related t...
Definition: mmwavelink.h:4392
This is the Monitoring report which the xWR device sends to the host, containing the measured RX mixe...
Definition: mmwavelink.h:4319
Structure to hold the MSS Boot error status data strucutre when booted over SPI for event RL_DEV_AE_M...
Definition: mmwavelink.h:1793
Structure to hold the MSS ESM Fault data structure for event RL_DEV_AE_MSS_ESMFAULT_SB.
Definition: mmwavelink.h:1703
The report header includes common information across all enabled monitors like current FTTI number an...
Definition: mmwavelink.h:2830
mmwavelink software version structure
Definition: mmwavelink.h:2585
mmWaveLink callback functions for Command parser
Definition: mmwavelink.h:1297
OS mutex callback functions.
Definition: mmwavelink.h:1087
This is the Monitoring report which RadarSS sends to the host, containing the external signal voltage...
Definition: mmwavelink.h:3922
Structure to hold the MSS/radarSS CPU Fault data strucutre for event RL_DEV_AE_MSS_CPUFAULT_SB and RL...
Definition: mmwavelink.h:2273
mmwavelink version structure
Definition: mmwavelink.h:2659
Structure to hold data strucutre for test status of the periodic tests for event RL_DEV_AE_MSS_PERIOD...
Definition: mmwavelink.h:1965
mmWaveLink RF Start Complete data structure for event RL_DEV_AE_RFPOWERUPDONE_SB
Definition: mmwavelink.h:1647
mmWaveLink Asynchronous event callback function
Definition: mmwavelink.h:1265
This is the Monitoring report which RadarSS sends to the host, containing the measured RX IF filter a...
Definition: mmwavelink.h:3214
OS message queue/Spawn callback functions.
Definition: mmwavelink.h:1220
This is the Monitoring report which RadarSS sends to the host, containing the measured TX power value...
Definition: mmwavelink.h:3412
OS services callback functions.
Definition: mmwavelink.h:1246

Copyright 2020, Texas Instruments Incorporated