3.2. PRU ICSS EthernetIP Release Notes

3.2.1. Overview

The PRU-ICSS Ethernet/IP package provides the foundation that facilitate application software development for Ethernet/IP Adapter on TI Sitara Embedded Processors with PRU-ICSS HW IP.

3.2.2. Standard Compliance

Compliant to ODVA EtherNet IP Comformance Tests 15

3.2.3. Documentation

  • EtherNet IP Datasheet: Data sheet contains information about the capabilities of the solution, certification information (if applicable), memory and pin mux information. It can be found in the ‘docs’ folder in the installation directory. The directory structure is shown in the user guide here
  • EVM Quick Start Guide: Provides information on hardware setup and running the demonstration application that is loaded on flash. This document is provided as part of the EVM kit.

3.2.3.1. Release 01.00.04

Released January 2021

PRU-ICSS Ethernet/IP package download link : https://www.ti.com/tool/PRU-ICSS-INDUSTRIAL-SW

3.2.3.1.1. What’s New

  • Multicast filtering for host traffic
  • Compliance to Conformance Test Suite v15
  • Bug Fixes

3.2.3.1.2. Features supported

  • Ethernet/IP Capabilities
    • Explicit Messaging and Implicit Messaging
    • UCMM
    • Class 1 and Class 3 Connection
  • Object classes supported
    • Identity Object
    • Message Router Object
    • Assembly Object
    • Connection Manager Object
    • Ethernet Link Object
    • TCP/IP Interface Object
    • QOS Object
    • Device Level Ring Object
  • Supported Connections
    • Exclusive Owner Connection
    • Input Only Connection
    • Listen Only Connection
  • Total CIP connections : 9
    • IO Messaging : 6
    • Explicit Messaging : 3
  • PHY Configuration
    • Duplex : Half/Full/Auto
    • Speed : 10/100/Auto
  • Device Configuration : EDS File
  • QoS scheme : 3-bit VLAN PCP
    • No of levels supported : 8
    • Number of queues : 4. 2 QoS levels per queue
  • Statistics
    • Media counters supported per port
    • Interface counters supported per port
  • Conformance : CT 15 compliant
  • Min RPI supported : 1ms
  • Device Level Ring
    • Beacon Based
    • Min. beacon interval : 200 us
    • Min. beacon timeout : 400 us
    • Self configuring
  • PTP/1588
    • Supports Drives Profile : E2E clock.
    • PTP over UDP
    • Transparent Clock supported
    • Ordinary Clock supported
    • Single and Two step clock supported
  • Learning/FDB : Yes
    • 1024 entries per port
    • Learning table on DDR
  • Storm Prevention : Yes. Configurable per port
  • Support for Multicast Filtering
    • Supported on all SoCs
    • Hash Table for faster lookup
    • O(1) complexity

3.2.3.1.3. What is not supported

  • CIP Sync support in stack
  • IEEE 1588 Master support

3.2.3.1.4. PRU-ICSS Firmware Revision

Platform Build Firmware Header Location
AM64x 5.2.7 protocols\ethernetip_adapter\firmware\g_v1.0

3.2.3.1.5. Fixed Issues

None

3.2.3.1.6. Known Issues

This section contains the list of known Issues at the time of making the release.

None

3.2.3.2. Additional Notes

None


3.2.3.3. Archives

None


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