4.2. PRU ICSS Industrial Drives Release Notes¶
Updated : January 2021
4.2.1. Overview¶
PRU-ICSS Industrial Drives package is designed for the Sitara processor AM64x (with PRU-ICSS IP) to enable customers leverage Industrial Drives (position, current sense & control algorithm) capabilities
4.2.2. Licensing¶
Please refer to the software manifest, which outlines the licensing status for all packages included in this release. The manifest can be found on the SDK download page, installed directory.
4.2.3. Specification Compliance¶
- EnDat2.2 Master
- EnDAT 2.2 Specification 297403_04_A_02
- Hiperface DSL master
- DSL Protocol Specification v3.20
4.2.4. Documentation¶
- Software Developer Guide: Provides information on features, functions, delivery package and, compile tools for the release. This also provides detailed information regarding software elements and software infrastructure to allow developers to start creating applications.
- Getting Started Guide: provides information on getting the software and running basic examples/demonstrations bundled in the package.
- User Guide: Provides basic information on the applications
- Software Manifest: Provides license information on software included in the package. This document is in the release at the root directory of the package
- EVM Quick Start Guide: Provides information on hardware setup and running the demonstration application that is loaded on flash. This document is provided as part of the EVM kit.
4.2.5. Release 02.00.00¶
Released January 2021
4.2.5.1. System Requirements¶
4.2.5.2. Device Support¶
- SOC
- AM64x
- Hardware Platform
- AM64x GPEVM
4.2.5.3. What’s New¶
- External pulse synchronization support added to HDSL.
4.2.5.4. Features Supported¶
- Hiperface DSL master
- PRU Firmware source
- External pulse synchronization
- Safe position
- Supports upto 100m cable
- Communication status
- Register interface to be compatible with SICK HDSL FPGA IP Core (except registers that have different functionality for read & write)
- Parameter channel communication (short message write)
- EnDat2.2 Master
- PRU Firmware source
- EnDat 2.2 command set
- EnDat 2.1 command set
- Interrupted and continuous clock mode
- Clock configuration up to 16MHz
- Cable length up to 100m @8MHz
- Propagation delay compensation (capable of handling different propagation delay of different channels in concurrent multi channel configuration)
- Automatic estimation of propagation delay
- Receive on-the-fly CRC verification of position, parameters and additional information
- Two modes of operation - host trigger and periodic trigger
- Channel select
- Concurrent multi channel support (up-to 3 encoders with identical part number @ 8MHz maximum)
4.2.5.5. What is not supported¶
In general, peripherals or features not mentioned as part of “Features Supported” section are not supported in this release.
Motor Control
Tamagawa Receiver
EnDat2.2 Master
- Safety
Hiperface DSL master
- Fast position, speed
- Pipeline channel
- Short message read
- Safety
4.2.5.7. Known Issues¶
This section contains the list of Known Issues at the time of making the release.
| Record ID | Platform | Details | Workaround |
|---|---|---|---|
| SITSW-372 | Sitara | Continuous mode does not work for EnDAT encoder. | Use non continuous mode |
