2.2. PRU ICSS EtherCAT Release Notes¶
2.2.1. Overview¶
The PRU-ICSS EtherCAT package provides the foundation that facilitate application software development for EtherCAT Slave on TI Sitara Embedded Processors with PRU-ICSS HW IP
2.2.2. Standard Compliance¶
Compliant to ETG.1000 V1.0.2 Spec
2.2.3. Documentation¶
- Software Developer Guide: Provides information on features, functions, delivery package and, compile tools for the release. This also provides detailed information regarding software elements and software infrastructure to allow developers to start creating applications.
- Getting Started Guide: provides information on getting the software and running basic examples/demonstrations bundled in the package.
- User Guide: Provides basic information on the applications
- EVM Quick Start Guide: Provides information on hardware setup and running the demonstration application that is loaded on flash. This document is provided as part of the EVM kit.
2.2.4. Release 01.00.09¶
Released January 2021
2.2.4.1. System Requirements¶
2.2.4.3. Features Supported¶
- EtherCAT Slave Controller
- All EtherCAT Commands (NOP, APRD, APWR, APRW, FPRD, FPWR, FPRW, BRD, BWR, BRW, LRD, LWR, LRW, ARMW and FRMW)
- 8 FMMU support
- 8 SM support
- 60KB (AM64x) of Process Data RAM
- Distributed clocks
- 64-bit DC
- SYNC0 out generation single shot and cyclic mode support
- SYNC1 out generation - SYNC1 cycle time multiple of SYNC0 cycle time
- Latch0 and Latch1 inputs
- System Time PDI control
- DL Loop Control
- Using MII_RX_LINK (fast - depending on PHY link loss detection latency) – mandatory for cable redundancy support
- Using PRU-ICSS MDIO state machine – not recommended for cable redundancy support
- Interrupts – AL/ECAT events
- SYNC0, SYNC1 and PDI interrupt events on external SOC pins
- Watchdog – PDI and SM
- Error Counters
- RX Invalid Frame Counter Port 0/1
- RX ERR Counter Port 0/1
- Forwarded Error Counter Port 0/1
- ECAT Processing Unit Error Counter
- LED – Run, Error and Port0/1 activity based on firmware feedback
- Controlled via GPIO from Host CPU or PHY directly
- EEPROM Emulation
- QSPI flash non-volatile storage support
- Management Interface for PHY over EtherCAT
- PHY address configuration and host side PRU-ICSS MDIO API for PHY programming
- Cable redundancy support
- Beckhoff EtherCAT Slave Stack Code (SSC) Version 5.12 based evaluation library and example
2.2.4.4. What is not supported¶
- In general, peripherals or features not mentioned as part of “Features Supported” section are not supported in this release.
- EtherCAT Slave Controller
- ECAT side register protection when using LRD command
- APRW/FPRW/BRW for SM mapped area
- EtherCAT G
2.2.4.5. PRU-ICSS Firmware Revision¶
| Platform | Build | Firmware Header location |
|---|---|---|
| AM64x | 5.4.242 | protocols\ethercat_slave\firmware\g_v1.0 |
2.2.4.7. Known Issues¶
This section contains the list of Known Issues at the time of making the release.
| Record ID | Platform | Details | Workaround |
|---|---|---|---|
| PINDSW-47 | Sitara | Multiple FMMU access in a single datagram to a slave for process data using LRD/LWR commands | Use LRW instead of LRD/LWR |
| PINDSW-72 | Sitara | PDI/PD watchdog counter incremented by 1 whenever PDI/PD watchdog is disabled | None |
| PINDSW-74 | Sitara | LRD access on unused registers increment WKC - no register protection while using LRD | None |
| PINDSW-141 | Sitara | LRW access to non-interleaved input and output process data of multiple slaves does not work. SOEM accesses slaves in LRW mode this way | Use LRD/LWR for process data access or use more optimal interleaved access for process data access from Master (TwinCAT way) |
| PINDSW-2204 | Sitara | Frames with no SFD not counted as errors if received on reverse path | None |
| PINDSW-2360 | Sitara | System time of next Sync0 pulse register (0x990:0x993) is not instantaneous, resulting in read of incorrect value if read immediately after sync pulse | None |
| PINDSW-3120 | Sitara | Lost Link Counter register (0x310) increments with “2” on every link down instead of “1” | Revert back the MDIO Link interrupt to Edge in tiesc_pruss_intc_mapping.h file. Customers need to make sure that above mentioned link stability issue is not seen in their setup before making this change. |
| PINDSW-4298 | AM65x | IDK does not detected by TwinCAT when NIC’s Link Speed Duplex is in 100Mbps Full Duplex Mode | None |
| PINDSW-4310 | Sitara | EtherCAT Slave in DC slave mode takes longer to recover from reference clock shifts | None |
