2.4. Release Notes - 07_01_00¶

2.4.3.1. MCUSW¶

This release do not include MCUSW component, please contact local FAE for further information.

2.4.3.2. Build and Packaging¶

• The PDK package is now a separate package each platform, i.e. this package contains drivers required for AM65xx platform only.

• Only the files applicable to a particular platform is packaged. This is to done to reduce the overall package size, remove unwanted files for users for better file/folder navigation and also to ensure that a file which is not applicable for a platform is not included by application un-intentionally

  • Due to this some of the application interface files may be missing from the package compared to last release. Users are advised to remove the inclusion of these files in their application for the respective platform builds

2.4.3.3. Memory Map and Linker Command¶

System Firmware architecture has been updated for J7200 and J721E devices to run Device Management services on the MCU1_0 R5F. For details, see Sciclient upgrade and compatibility information.

In order to support this new architecture, additional memory sections are reserved in MCU MSRAM for the boot and initialization sequence, and new data sections are introduced by the supporting libraries.

SoC-wide

A portion of the MCU SRAM is reserved for exchange of data between SBL and the Device Manager, summarized in the below table:

For more information on the purpose and implementation of these reserved regions, refer to Board configuration passing between SPL/SBL and MCU1_0 applications. Also, PDK common linker command file could be used as reference PDK_INSTALL_DIR/packages/ti/build/am65xx/linker_r5.lds

MCU1_0 Applications

Linker configuration files for MCU1_0 applications must be updated to comprehend placement of additional sections introduced by the Device Manager implementation

• Passing of the board configuration between SBL and the MCU1_0 application may optionally be replaced by referencing a local copy of the board configuration data structures within the Sciclient library. Regardless of which method for sending board configuration data, the .boardcfg_data section is defined by default for the placement of these structures in the application memory map.

• MCU1_0 R5F applications are expected to co-host Device Management services which are implemented via the RM/PM HAL library. This library introduces additional data sections, which are free to be placed anywhere as required by the integrating application:
  • .const.devgroup.MAIN
  • .const.devgroup.MCU_WAKEUP
  • .const.devgroup.DMSC_INTERNAL
  • .bss.devgroup.MAIN
  • .bss.devgroup.MCU_WAKEUP
  • .bss.devgroup.DMSC_INTERNAL

2.4.3.4. OSPI Flash Memory Map¶

The default flash memory layout used by the SBL to load multicore application images has been updated in this release. It now uses the following flash address offsets:

2.4.3.5. Sciclient¶

No specific changes for AM65xx

2.4.3.6. MCU R5F ATCM¶

As part of SBL starting MCU R5F (MCU 10) with application provided for MCU 10, the MCU R5F would be reset. When the MCU R5F is reset, the TCMs would also be reset / contents lost. When the application is based on sysbios / TI RTOS, the vectors should be placed in ATCM, as detailed in FAQ Copy Vecs to ATCM

Loss of vectors placed in TCMs

• Results in MCU 10 applications not starting

• PDK provides an utility (utilsCopyVecs2ATcm) to place the vectors into ATCM as part of application start up

• The default sysbios configuration file PDK_INSTALL_DIR/packages/ti/build/am65xx/sysbios_r5f.cfg , employes this utility

• Care should be take to place this utility in memory segements that’s accessible before application initialization,

  • The default linker command file PDK_INSTALL_DIR/packages/ti/build/am65xx/linker_r5_sysbios.lds, places this in OCMRAM

Loss of .text or .data placed in TCMs

• Using TCMs to hold .text, .data and others would be affected
• PDK provides and example that demonstrate the steps required to place sections in TCM’s, refer How to move sections at runtime

2.4.3.7. Execution of apps with CCS¶

The steps to run applications with CCS has been updated. Refer Link for detailed steps.

2.4.3.8. SBL¶

• The SBL provides support on J721E and J7200 for the new split architecture for System Firmware, with TI Foundational Security (TIFS) running on the DMSC and the Device Management (DM) functions running on the MCU R5F. Sciclient API requests for security related operations will continue to be sent to the DMSC, while other Sciclient API requests for the non-secure Resource Managment (RM) and Power Management (PM) operations will be handled directly on the MCU R5F.
• The OSPI PHY on the SoC requires a PHY tuning procedure to be performed to ensure good stability and performance is achieved for the high-speed transfers performed when the PHY is enabled. The BOARD library linked in with the SBL handles this procedure as part of the SBL boot sequence. However, a PHY tuning data binary must be flashed to the start address of the last flash sector of the OSPI/xSPI device on the board. This data is used by the OSPI driver during the boot sequence for tuning the PHY.
• HLOS + RTOS boot is now supported by the SBL, with new SBL build targets for support of HLOS (or U-boot) boot on the Cortex-A cores in the MAIN domain. MMC/SD boot and OSPI/xSPI flash boot options are supported.
• Tooling is provided to created a “combined” .appimage file with the desired HLOS & RTOS images that the SBL can load, parse, and subsequently load & start on each of the remote cores that have been targeted to boot.

2.4.3.9. SYSBIOS Configuration¶

• Main Domain R5F Timer

  • Updated to use DM Timers instance 6 & 7 of main domain for Main Domain R5F. By default SYSBIOS uses instance 12 & 13
  • DM Timers instances 9 to 20 are not powered on by default, requires to be explicitly powered on
  • Without this configuration, sysbios application would not be functional

• The sysbios reserved interrupt number “0”

  • MCAN instance 0 in MCU and interrupt line 0 cannot used with default sysbios configuration
  • Recommend to re-configure sysbios to use a different interrupt number

2.4.3.10. UDMA¶

• Update in Udma_RmInitPrms->startIrIntr and Udma_RmInitPrms->numIrIntr

  • Earlier this parameters referred to the core interrupt range.
  • Its updated to refer to IR Interrupt range for alligning with Sciclient BoardCfg RM.

• Udma_eventUnregister for UDMA_EVENT_TYPE_RING / UDMA_EVENT_TYPE_DMA_COMPLETION will return failure when Ring Occupancy is non-zero.

  • This is to make sure that there is no resource leak, because unregistering these events will reset the ring.
  • All the unprocessed descriptors in the ring / processed descriptors returned to the ring, should be dequeued using Udma_ringFlushRaw / Udma_ringDequeueRaw before unregistering these events.

2.4.3.11. ENET¶

Migration to Enet LLD from the Emac LLD descoped for this release. Emac LLD would continue to support CPSW and ICSSG. Enet LLD code in PDK repo is for reference only and should not be used in development.

2.4.3.12. PMIC¶

Not supported and no impact