47 #ifndef CSL_DSSVIDEOPORT_H_ 48 #define CSL_DSSVIDEOPORT_H_ 79 #define CSL_DSS_VP_CSC_POS_AFTER_GAMMA \ 80 ((uint32_t) CSL_DSS_VP1_CONFIG_COLORCONVPOS_VAL_AFTERGAMMA) 82 #define CSL_DSS_VP_CSC_POS_BEFORE_GAMMA \ 83 ((uint32_t) CSL_DSS_VP1_CONFIG_COLORCONVPOS_VAL_BEFOREGAMMA) 94 #define CSL_DSS_VP_TDM_UNUSED_BITS_LEVEL_LOW \ 95 ((uint32_t) CSL_DSS_VP1_CONTROL_TDMUNUSEDBITS_VAL_LOWLEVEL) 97 #define CSL_DSS_VP_TDM_UNUSED_BITS_LEVEL_HIGH \ 98 ((uint32_t) CSL_DSS_VP1_CONTROL_TDMUNUSEDBITS_VAL_HIGHLEVEL) 100 #define CSL_DSS_VP_TDM_UNUSED_BITS_LEVEL_UNCHANGED \ 101 ((uint32_t) CSL_DSS_VP1_CONTROL_TDMUNUSEDBITS_VAL_UNCHANGED) 111 #define CSL_DSS_VP_TDM_CYCLE_1PERPIXEL \ 112 ((uint32_t) CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_VAL_1CYCPERPIX) 114 #define CSL_DSS_VP_TDM_CYCLE_2PERPIXEL \ 115 ((uint32_t) CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_VAL_2CYCPERPIX) 117 #define CSL_DSS_VP_TDM_CYCLE_3PERPIXEL \ 118 ((uint32_t) CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_VAL_3CYCPERPIX) 120 #define CSL_DSS_VP_TDM_CYCLE_3PER2PIXEL \ 121 ((uint32_t) CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_VAL_3CYCPER2PIX) 131 #define CSL_DSS_VP_TDM_PARALLEL_OUTPUT_8BIT \ 132 ((uint32_t) CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_VAL_8BPARAINT) 134 #define CSL_DSS_VP_TDM_PARALLEL_OUTPUT_9BIT \ 135 ((uint32_t) CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_VAL_9BPARAINT) 137 #define CSL_DSS_VP_TDM_PARALLEL_OUTPUT_12BIT \ 138 ((uint32_t) CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_VAL_12BPARAINT) 140 #define CSL_DSS_VP_TDM_PARALLEL_OUTPUT_16BIT \ 141 ((uint32_t) CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_VAL_16BPARAINT) 151 #define CSL_DSS_VP_HVSYNC_NOT_ALIGNED \ 152 ((uint32_t) CSL_DSS_VP1_POL_FREQ_ALIGN_VAL_NOTALIGNED) 154 #define CSL_DSS_VP_HVSYNC_ALIGNED \ 155 ((uint32_t) CSL_DSS_VP1_POL_FREQ_ALIGN_VAL_ALIGNED) 166 #define CSL_DSS_VP_HVCLK_CONTROL_OFF \ 167 ((uint32_t) CSL_DSS_VP1_POL_FREQ_ONOFF_VAL_DOPEDPCK) 169 #define CSL_DSS_VP_HVCLK_CONTROL_ON \ 170 ((uint32_t) CSL_DSS_VP1_POL_FREQ_ONOFF_VAL_DBIT16) 181 #define CSL_DSS_VP_LPP_DELTA_ZERO \ 182 ((uint32_t) CSL_DSS_VP1_SIZE_SCREEN_DELTA_LPP_VAL_SAME) 184 #define CSL_DSS_VP_LPP_DELTA_PLUSONE \ 185 ((uint32_t) CSL_DSS_VP1_SIZE_SCREEN_DELTA_LPP_VAL_PLUSONE) 187 #define CSL_DSS_VP_LPP_DELTA_MINUSONE \ 188 ((uint32_t) CSL_DSS_VP1_SIZE_SCREEN_DELTA_LPP_VAL_MINUSONE) 199 #define CSL_DSS_VP_FID_FIRST_EVEN \ 200 ((uint32_t) CSL_DSS_VP1_CONFIG_FIDFIRST_VAL_EVEN) 202 #define CSL_DSS_VP_FID_FIRST_ODD \ 203 ((uint32_t) CSL_DSS_VP1_CONFIG_FIDFIRST_VAL_ODD) 213 #define CSL_DSS_VP_SAFETY_REGION_0 ((uint32_t) 0x0U) 215 #define CSL_DSS_VP_SAFETY_REGION_1 ((uint32_t) 0x1U) 217 #define CSL_DSS_VP_SAFETY_REGION_2 ((uint32_t) 0x2U) 219 #define CSL_DSS_VP_SAFETY_REGION_3 ((uint32_t) 0x3U) 221 #define CSL_DSS_VP_SAFETY_REGION_MAX ((uint32_t) 0x4U) 223 #define CSL_DSS_VP_SAFETY_REGION_INVALID ((uint32_t) 0xFFU) 234 #define CSL_DSS_VP_OLDI_MAP_TYPE_A \ 235 ((uint32_t) CSL_DSS_VP1_DSS_OLDI_CFG_MAP_VAL_TYPE_A) 237 #define CSL_DSS_VP_OLDI_MAP_TYPE_B \ 238 ((uint32_t) CSL_DSS_VP1_DSS_OLDI_CFG_MAP_VAL_TYPE_B) 240 #define CSL_DSS_VP_OLDI_MAP_TYPE_C \ 241 ((uint32_t) CSL_DSS_VP1_DSS_OLDI_CFG_MAP_VAL_TYPE_C) 255 #define CSL_DSS_VP_OLDI_BIT_DEPTH_18_BITS \ 256 ((uint32_t) CSL_DSS_VP1_DSS_OLDI_CFG_MSB_VAL_18B) 258 #define CSL_DSS_VP_OLDI_BIT_DEPTH_24_BITS \ 259 ((uint32_t) CSL_DSS_VP1_DSS_OLDI_CFG_MSB_VAL_24B) 641 uint32_t isCustomTiming);
714 uint32_t signSeedVal);
728 uint32_t referenceSign,
913 if(
NULL != polarityCfg)
925 if(
NULL != advSignalCfg)
930 advSignalCfg->
acBI = 0x0U;
931 advSignalCfg->
acB = 0x0U;
uint32_t acB
Definition: csl_dssVideoPort.h:373
Advance Signal Configuration for the LCD.
Definition: csl_dssVideoPort.h:358
uint32_t hFrontPorch
Definition: csl_dssVideoPort.h:501
uint32_t tdmCycleFormat
Definition: csl_dssVideoPort.h:291
FVID2 Mode information structure.
Definition: csl_fvid2_dataTypes.h:1266
void CSL_dssVpEnableTvGamma(CSL_dss_vpRegs *vpRegs, const CSL_DssVpGammaCfg *gammaCfg)
Enable/Bypass TV Gamma Table.
static void CSL_dssVpLcdOpTimingCfgInit(CSL_DssVpLcdOpTimingCfg *lcdCfg)
CSL_DssVpLcdOpTimingCfg structure init function.
Definition: csl_dssVideoPort.h:940
uint32_t numBitsPixel2Cycle1
Definition: csl_dssVideoPort.h:318
Blanking Timing parameters for the LCD.
Definition: csl_dssVideoPort.h:499
#define CSL_DSS_VP_HVCLK_CONTROL_OFF
HSYNC and VSYNC are driven on opposite edges of the pixel clock than pixel data.
Definition: csl_dssVideoPort.h:166
void CSL_dssVpSetSafetyChkConfig(CSL_dss_vpRegs *vpRegs, const CSL_DssSafetyChkCfg *safetyCfg, uint32_t regionId)
Configure the Safety Check parameters.
uint32_t pixelClkPolarity
Definition: csl_dssVideoPort.h:344
#define FALSE
Definition: csl_types.h:55
uint32_t hVClkControl
Definition: csl_dssVideoPort.h:363
void CSL_dssVpSetLcdTdmConfig(CSL_dss_vpRegs *vpRegs, const CSL_DssVpLcdTdmCfg *lcdTdmCfg)
Configure the LCD TDM(Time division multiplexing) parameters.
#define FVID2_POL_HIGH
High Polarity.
Definition: csl_fvid2_dataTypes.h:772
Timing configuration for the LCD output.
Definition: csl_dssVideoPort.h:405
uint32_t tdmEnable
Definition: csl_dssVideoPort.h:284
uint32_t hSyncGated
Definition: csl_dssVideoPort.h:383
Polarity of Active Video, Pixel Clock, HSync and VSync signals for the LCD.
Definition: csl_dssVideoPort.h:339
#define FVID2_EDGE_POL_FALLING
Falling Edge.
Definition: csl_fvid2_dataTypes.h:787
static void Fvid2ModeInfo_init(Fvid2_ModeInfo *modeInfo)
Fvid2_ModeInfo structure init function. This defaults to 1080p60.
Definition: csl_fvid2_dataTypes.h:2233
static void CSL_dssVpLcdTdmCfgInit(CSL_DssVpLcdTdmCfg *tdmCfg)
CSL_DssVpLcdTdmCfg structure init function.
Definition: csl_dssVideoPort.h:886
#define CSL_DSS_VP_FID_FIRST_EVEN
First field is even.
Definition: csl_dssVideoPort.h:199
#define CSL_DSS_VP_OLDI_BIT_DEPTH_24_BITS
Input RGB data's bit depth is 24.
Definition: csl_dssVideoPort.h:258
uint32_t fidFirst
Definition: csl_dssVideoPort.h:490
Gamma Correction configuration for DSS Video Port Output.
Definition: csl_dssVideoPort.h:269
void CSL_dssVpSetCSCCoeff(CSL_dss_vpRegs *vpRegs, const CSL_DssCscCoeff *cscCoeff, uint32_t cscPos, uint32_t cscEnable)
Configure the coefficients for Color Space Conversion.
uint32_t gammaEnable
Definition: csl_dssVideoPort.h:271
uint32_t dssBitDepth
Definition: csl_dssVideoPort.h:550
uint32_t hVClkRiseFall
Definition: csl_dssVideoPort.h:366
void CSL_dssVpSetOldiConfig(CSL_dss_vpRegs *vpRegs, const CSL_DssVpOldiCfg *oldiCfg)
Set the OLDI configuration.
uint32_t pixelGated
Definition: csl_dssVideoPort.h:395
uint32_t numBitsPixel1Cycle2
Definition: csl_dssVideoPort.h:303
uint32_t vsPolarity
Definition: csl_dssVideoPort.h:350
#define CSL_DSS_VP_TDM_CYCLE_1PERPIXEL
1 cycle per pixel
Definition: csl_dssVideoPort.h:111
#define CSL_DSS_VP_OLDI_MAP_TYPE_C
Map Type C is Single Link 24 bit VESA.
Definition: csl_dssVideoPort.h:240
uint32_t bitAlignPixel1Cycle0
Definition: csl_dssVideoPort.h:306
uint32_t pixelClockGated
Definition: csl_dssVideoPort.h:387
uint32_t bitAlignPixel1Cycle2
Definition: csl_dssVideoPort.h:312
uint32_t actVidPolarity
Definition: csl_dssVideoPort.h:341
uint32_t tdmParallelMode
Definition: csl_dssVideoPort.h:294
uint32_t dataEnablePolarity
Definition: csl_dssVideoPort.h:547
uint32_t videoIfWidth
Definition: csl_dssVideoPort.h:478
uint32_t vBackPorch
Definition: csl_dssVideoPort.h:524
int32_t CSL_dssVpSetLcdBlankTiming(CSL_dss_vpRegs *vpRegs, const CSL_DssVpLcdBlankTimingCfg *blankCfg, uint32_t dvoFormat, uint32_t scanFormat, uint32_t isCustomTiming)
Configure the LCD Blank Timing parameters.
uint32_t oldiMapType
Definition: csl_dssVideoPort.h:545
uint32_t hVAlign
Definition: csl_dssVideoPort.h:360
#define CSL_DSS_VP_TDM_PARALLEL_OUTPUT_8BIT
8-bit parallel output interface selected
Definition: csl_dssVideoPort.h:131
static void CSL_dssVpOldiCfgInit(CSL_DssVpOldiCfg *oldiCfg)
CSL_DssVpOldiCfg structure init function.
Definition: csl_dssVideoPort.h:968
uint32_t tdmUnusedBitsLevel
Definition: csl_dssVideoPort.h:288
#define NULL
Define NULL if not defined.
Definition: csl_types.h:107
#define CSL_DSS_VP_LPP_DELTA_ZERO
Odd field has same size as even.
Definition: csl_dssVideoPort.h:181
void CSL_dssVpSetSafetyReferenceSign(CSL_dss_vpRegs *vpRegs, uint32_t referenceSign, uint32_t regionId)
Set the reference safety signature for data correctness check.
uint32_t bitAlignPixel1Cycle1
Definition: csl_dssVideoPort.h:309
uint32_t numBitsPixel2Cycle2
Definition: csl_dssVideoPort.h:321
uint32_t numBitsPixel2Cycle0
Definition: csl_dssVideoPort.h:315
OLDI Configuration.
Definition: csl_dssVideoPort.h:543
static void CSL_dssVpLcdAdvSignalCfgInit(CSL_DssVpLcdAdvSignalCfg *advSignalCfg)
CSL_DssVpLcdAdvSignalCfg structure init function.
Definition: csl_dssVideoPort.h:922
Structure containing coefficients for Color Space Conversion.
Definition: csl_dssTop.h:230
uint32_t pixelDataGated
Definition: csl_dssVideoPort.h:391
void CSL_dssVpSetLcdSignalPolarityConfig(CSL_dss_vpRegs *vpRegs, const CSL_DssVpLcdSignalPolarityCfg *polarityCfg)
Configure the Polarity of LCD signals(HSYNC, VSYNC, PCLK, Data)
void CSL_dssVpSetSafetySignSeedVal(CSL_dss_vpRegs *vpRegs, uint32_t signSeedVal)
Set the seed value for the signature calculation.
#define CSL_DSS_NUM_LUT_ENTRIES
Number of entries for CLUT/Gamma Correction.
Definition: csl_dssTop.h:218
#define CSL_DSS_VP_HVSYNC_NOT_ALIGNED
HSYNC and VSYNC are not aligned.
Definition: csl_dssVideoPort.h:151
uint32_t acBI
Definition: csl_dssVideoPort.h:369
uint32_t cscRange
Definition: csl_dssVideoPort.h:476
uint32_t bitAlignPixel2Cycle2
Definition: csl_dssVideoPort.h:330
CSL_dss_vp1Regs CSL_dss_vpRegs
DSS Video Port Registers.
Definition: csl_dssVideoPort.h:69
#define FVID2_VIFW_12BIT
12-bit interface.
Definition: csl_fvid2_dataTypes.h:909
Fvid2_ModeInfo mInfo
Definition: csl_dssVideoPort.h:407
void CSL_dssVpEnable(CSL_dss_vpRegs *vpRegs, uint32_t enable)
Enable the DSS Video Port.
uint32_t hSyncLen
Definition: csl_dssVideoPort.h:513
uint32_t vSyncLen
Definition: csl_dssVideoPort.h:531
uint32_t vFrontPorch
Definition: csl_dssVideoPort.h:518
#define CSL_DSS_CSC_RANGE_FULL
Full range selected.
Definition: csl_dssTop.h:181
uint32_t numBitsPixel1Cycle0
Definition: csl_dssVideoPort.h:297
uint32_t dvoFormat
Definition: csl_dssVideoPort.h:474
uint32_t numBitsPixel1Cycle1
Definition: csl_dssVideoPort.h:300
uint32_t vSyncGated
Definition: csl_dssVideoPort.h:379
LCD Configuration for Time Division Multiplexing.
Definition: csl_dssVideoPort.h:282
void CSL_dssVpSetLcdAdvSignalConfig(CSL_dss_vpRegs *vpRegs, const CSL_DssVpLcdAdvSignalCfg *advSignalCfg)
Configure the advance LCD Signal parameters.
#define FVID2_EDGE_POL_RISING
Rising Edge.
Definition: csl_fvid2_dataTypes.h:785
int32_t CSL_dssVpSetLcdOpTimingConfig(CSL_dss_vpRegs *vpRegs, const CSL_DssVpLcdOpTimingCfg *lcdCfg)
Configure the LCD Timing parameters.
uint32_t bitAlignPixel2Cycle0
Definition: csl_dssVideoPort.h:324
Configuration for doing safety checks.
Definition: csl_dssTop.h:270
uint32_t deltaLinesPerPanel
Definition: csl_dssVideoPort.h:487
#define FVID2_DV_GENERIC_DISCSYNC
Video format is for any discrete sync.
Definition: csl_fvid2_dataTypes.h:221
void CSL_dssVpSetLcdLineNum(CSL_dss_vpRegs *vpRegs, uint32_t lineNum)
Set the Line Number at which the interrupt should be generated.
void CSL_dssVpOldiReset(const CSL_dss_vpRegs *vpRegs)
Reset the OLDI Module.
uint32_t hsPolarity
Definition: csl_dssVideoPort.h:347
uint32_t hBackPorch
Definition: csl_dssVideoPort.h:507
static void CSL_dssVpLcdBlankTimingCfgInit(CSL_DssVpLcdBlankTimingCfg *blankCfg)
CSL_DssVpLcdBlankTimingCfg structure init function.
Definition: csl_dssVideoPort.h:954
static void CSL_dssVpGammaCfgInit(CSL_DssVpGammaCfg *gammaCfg)
CSL_DssVpGammaCfg structure init function.
Definition: csl_dssVideoPort.h:872
static void CSL_dssVpLcdSignalPolarityCfgInit(CSL_DssVpLcdSignalPolarityCfg *polarityCfg)
CSL_DssVpLcdSignalPolarityCfg structure init function.
Definition: csl_dssVideoPort.h:910
uint32_t CSL_dssVpGetSafetySign(const CSL_dss_vpRegs *vpRegs, uint32_t regionId)
Get the Safety Signature of the sub region.
void CSL_dssVpOldiEnable(CSL_dss_vpRegs *vpRegs, uint32_t enable)
Enable/disable the OLDI Module.
#define CSL_DSS_VP_TDM_UNUSED_BITS_LEVEL_LOW
Low level.
Definition: csl_dssVideoPort.h:94
void CSL_dssVpSetGoBit(CSL_dss_vpRegs *vpRegs)
GO Command for the VP output. It is used to synchronize the pipelines associated with the VP output.
uint32_t gammaData[CSL_DSS_NUM_LUT_ENTRIES]
Definition: csl_dssVideoPort.h:275
uint32_t bitAlignPixel2Cycle1
Definition: csl_dssVideoPort.h:327