1    /*
     2     * Copyright (c) 2013-2020, Texas Instruments Incorporated
     3     * All rights reserved.
     4     *
     5     * Redistribution and use in source and binary forms, with or without
     6     * modification, are permitted provided that the following conditions
     7     * are met:
     8     *
     9     * *  Redistributions of source code must retain the above copyright
    10     *    notice, this list of conditions and the following disclaimer.
    11     *
    12     * *  Redistributions in binary form must reproduce the above copyright
    13     *    notice, this list of conditions and the following disclaimer in the
    14     *    documentation and/or other materials provided with the distribution.
    15     *
    16     * *  Neither the name of Texas Instruments Incorporated nor the names of
    17     *    its contributors may be used to endorse or promote products derived
    18     *    from this software without specific prior written permission.
    19     *
    20     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    21     * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
    22     * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
    23     * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
    24     * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
    25     * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
    26     * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
    27     * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
    28     * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
    29     * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
    30     * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    31     */
    32    /*
    33     *  ======== ICache.xdc ========
    34     *
    35     *
    36     */
    37    
    38    /*!
    39     *  ======== ICache ========
    40     *  Cache Interface
    41     */
    42    
    43    @DirectCall
    44    interface ICache
    45    {
    46        /*! Lists of bitmask cache types */
    47        enum Type {
    48            Type_L1P = 0x1,         /*! Level 1 Program cache */
    49            Type_L1D = 0x2,         /*! Level 1 Data cache */
    50            Type_L1  = 0x3,         /*! Level 1 caches */
    51            Type_L2P = 0x4,         /*! Level 2 Program cache */
    52            Type_L2D = 0x8,         /*! Level 2 Data cache */
    53            Type_L2  = 0xC,         /*! Level 2 caches */
    54            Type_ALLP = 0x5,        /*! All Program caches */
    55            Type_ALLD = 0xA,        /*! All Data caches */
    56            Type_ALL = 0x7fff       /*! All caches */
    57        };
    58    
    59        /*!
    60         *  ======== enableCache ========
    61         *  Enable supported caches during startup
    62         *
    63         *  Not implemented by all architectures.  Refer to specific
    64         *  architecture Cache module for details.
    65         */
    66        config Bool enableCache = true;
    67    
    68        /*!
    69         *  ======== enable ========
    70         *  Enables all cache(s)
    71         *
    72         *  @param(type)    bit mask of Cache type
    73         */
    74        /* REQ_TAG(SYSBIOS-1235) */
    75        Void enable(Bits16 type);
    76    
    77        /*!
    78         *  ======== disable ========
    79         *  Disables the 'type' cache(s)
    80         *
    81         *  @param(type)    bit mask of Cache type
    82         */
    83        /* REQ_TAG(SYSBIOS-1236) */
    84        Void disable(Bits16 type);
    85    
    86        /*!
    87         *  ======== inv ========
    88         *  Invalidate the range of memory within the specified starting
    89         *  address and byte count.  The range of addresses operated on
    90         *  gets quantized to whole cache lines in each cache.  All lines
    91         *  in range are invalidated for all the 'type' caches.
    92         *
    93         *  @param(blockPtr) start address of range to be invalidated
    94         *  @param(byteCnt)  number of bytes to be invalidated
    95         *  @param(type)     bit mask of Cache type
    96         *  @param(wait)     wait until the operation is completed
    97         */
    98        /* REQ_TAG(SYSBIOS-1237) */
    99        Void inv(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
   100    
   101        /*!
   102         *  ======== wb ========
   103         *  Writes back a range of memory from all cache(s)
   104         *
   105         *  Writes back the range of memory within the specified starting
   106         *  address and byte count.  The range of addresses operated on
   107         *  gets quantized to whole cache lines in each cache.  All lines
   108         *  within the range are left valid in the 'type' caches and the data
   109         *  within the range will be written back to the source memory.
   110         *
   111         *  @param(blockPtr) start address of range to be invalidated
   112         *  @param(byteCnt)  number of bytes to be invalidated
   113         *  @param(type)     bit mask of Cache type
   114         *  @param(wait)     wait until the operation is completed
   115         */
   116        /* REQ_TAG(SYSBIOS-1238) */
   117        Void wb(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
   118    
   119        /*!
   120         *  ======== wbInv ========
   121         *  Writes back and invalidates the range of memory within the
   122         *  specified starting address and byte count.  The range of
   123         *  addresses operated on gets quantized to whole cache lines in
   124         *  each cache.  All lines within the range are written back to the
   125         *  source memory and then invalidated for all 'type' caches.
   126         *
   127         *  @param(blockPtr) start address of range to be invalidated
   128         *  @param(byteCnt)  number of bytes to be invalidated
   129         *  @param(type)     bit mask of Cache type
   130         *  @param(wait)     wait until the operation is completed
   131         */
   132        /* REQ_TAG(SYSBIOS-1239) */
   133        Void wbInv(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
   134    
   135        /*!
   136         *  ======== wbAll ========
   137         *  Write back all caches
   138         *
   139         *  Perform a global write back.  There is no effect on program cache.
   140         *  All data cache lines are left valid.
   141         */
   142        /* REQ_TAG(SYSBIOS-1240) */
   143        Void wbAll();
   144    
   145        /*!
   146         *  ======== wbInvAll ========
   147         *  Write back invalidate all caches
   148         *
   149         *  Performs a global write back and invalidate.  All cache lines
   150         *  are written out to physical memory and then invalidated.  
   151         */
   152        /* REQ_TAG(SYSBIOS-1241) */
   153        Void wbInvAll();
   154    
   155        /*!
   156         *  ======== wait ========
   157         *  Wait for a previous cache operation to complete
   158         *
   159         *  Wait for the cache wb/wbInv/inv operation to complete.  A cache
   160         *  operation is not truly complete until it has worked its way
   161         *  through all buffering and all memory writes have landed in the
   162         *  source memory.
   163         */
   164        /* REQ_TAG(SYSBIOS-1242) */
   165        Void wait();
   166    
   167    }
   168