PDK API Guide for AM65xx
IPC SoC Config

Introduction

This is IPC documentation specific to AM65xx SoC

Files

file  ipc_soc.h
 IPC Low Level Driver AM65XX SOC specific file.
 

Macros

#define IPC_VRING_BUFFER_SIZE   (0x200000)
 VRing Buffer Size required for all core combinations. More...
 
#define IPC_MPU1_0   (0)
 Core definitions. More...
 
#define IPC_MCU1_0   (1)
 
#define IPC_MCU1_1   (2)
 
#define IPC_MAX_PROCS   (3)
 
#define IPC_MAILBOX_CLUSTER_CNT   (12U)
 
#define IPC_MAILBOX_USER_CNT   (4U)
 
#define MAIN_NAVSS_MAILBOX_INPUTINTR_MAX   (440U)
 
#define MAIN_NAVSS_MAILBOX_OUTPUTINTR_MAX   (512U)
 
#define IPC_MCU_NAVSS0_INTR0_CFG_BASE   (CSL_NAVSS0_INTR0_INTR_ROUTER_CFG_BASE)
 
#define NAVSS512_MPU1_0_OUTPUT_OFFSET   (112)
 
#define NAVSS512_MCU1R5F0_OUTPUT_OFFSET   (120)
 
#define NAVSS512_MCU1R5F1_OUTPUT_OFFSET   (121)
 
#define MAIN2MCU0_INTR_ROUTER_INPUT_BASE   (184)
 
#define MAIN2MCU1_INTR_ROUTER_INPUT_BASE   (186)
 
#define MAIN2MCU0_INTR_ROUTER_OUTPUT_BASE   (0)
 
#define MAIN2MCU1_INTR_ROUTER_OUTPUT_BASE   (1)
 

Macro Definition Documentation

◆ IPC_VRING_BUFFER_SIZE

#define IPC_VRING_BUFFER_SIZE   (0x200000)

VRing Buffer Size required for all core combinations.

◆ IPC_MPU1_0

#define IPC_MPU1_0   (0)

Core definitions.

ARM A53 - VM0

◆ IPC_MCU1_0

#define IPC_MCU1_0   (1)

ARM MCU R5F - core0

◆ IPC_MCU1_1

#define IPC_MCU1_1   (2)

ARM MCU R5F - core1

◆ IPC_MAX_PROCS

#define IPC_MAX_PROCS   (3)

Maximum Processors

◆ IPC_MAILBOX_CLUSTER_CNT

#define IPC_MAILBOX_CLUSTER_CNT   (12U)

◆ IPC_MAILBOX_USER_CNT

#define IPC_MAILBOX_USER_CNT   (4U)

◆ MAIN_NAVSS_MAILBOX_INPUTINTR_MAX

#define MAIN_NAVSS_MAILBOX_INPUTINTR_MAX   (440U)

◆ MAIN_NAVSS_MAILBOX_OUTPUTINTR_MAX

#define MAIN_NAVSS_MAILBOX_OUTPUTINTR_MAX   (512U)

◆ IPC_MCU_NAVSS0_INTR0_CFG_BASE

#define IPC_MCU_NAVSS0_INTR0_CFG_BASE   (CSL_NAVSS0_INTR0_INTR_ROUTER_CFG_BASE)

◆ NAVSS512_MPU1_0_OUTPUT_OFFSET

#define NAVSS512_MPU1_0_OUTPUT_OFFSET   (112)

◆ NAVSS512_MCU1R5F0_OUTPUT_OFFSET

#define NAVSS512_MCU1R5F0_OUTPUT_OFFSET   (120)

◆ NAVSS512_MCU1R5F1_OUTPUT_OFFSET

#define NAVSS512_MCU1R5F1_OUTPUT_OFFSET   (121)

◆ MAIN2MCU0_INTR_ROUTER_INPUT_BASE

#define MAIN2MCU0_INTR_ROUTER_INPUT_BASE   (184)

◆ MAIN2MCU1_INTR_ROUTER_INPUT_BASE

#define MAIN2MCU1_INTR_ROUTER_INPUT_BASE   (186)

◆ MAIN2MCU0_INTR_ROUTER_OUTPUT_BASE

#define MAIN2MCU0_INTR_ROUTER_OUTPUT_BASE   (0)

◆ MAIN2MCU1_INTR_ROUTER_OUTPUT_BASE

#define MAIN2MCU1_INTR_ROUTER_OUTPUT_BASE   (1)