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35
36 package ti.sysbios.family.arm.v8a.smp;
37
38 import xdc.runtime.Error;
39 import ti.sysbios.family.arm.v8a.smp.GateSmp;
40
41 /*!
42 * ======== Core ========
43 * Core Identification Module.
44 *
45 * This Core module supports 2-core SMP mode on cluster 0
46 * and 4-core SMP mode with Core 0 being core 0 on cluster 0.
47 *
48 * 2-core SMP mode on Cluster 1 is explicitly NOT SUPPORTED.
49 */
50
51 @ModuleStartup
52 @CustomHeader
53
54 module Core inherits ti.sysbios.interfaces.ICore
55 {
56 /*!
57 * @_nodoc
58 * ======== CPUMASK ========
59 */
60 config UInt CPUMASK;
61
62 /*!
63 * ======== setL2DataRamLatency ========
64 * Value to set in L2CTRL[2:0] for Data RAM latency
65 *
66 * Faster CPUs need higher cycle latency for Data RAM accesses.
67 * For A72 CPUs running at 2 GHz, a value of 0x2 (3 cycles) is needed.
68 * If the A72 CPU is running slower than 2 GHz, you can set a lower
69 * value for fewer cycles of latency, but take care to ensure that this
70 * lower latency is sufficient for stable Data RAM values.
71 *
72 * This can be set to -1 to prevent any programming of L2CTRL[2:0] at all.
73 */
74 metaonly config Int setL2DataRamLatency = 0x2;
75
76 /*!
77 * @_nodoc
78 * ======== baseClusterId ========
79 */
80 config UInt baseClusterId = 0;
81
82 /*!
83 * @_nodoc
84 * ======== IpcFuncPtr ========
85 * IPC Callback function type definition.
86 */
87 typedef Void (*IpcFuncPtr)(UArg);
88
89 @Macro
90 override UInt hwiDisable();
91
92 @Macro
93 override UInt hwiEnable();
94
95 @Macro
96 override Void hwiRestore(UInt key);
97
98 /*!
99 * @_nodoc
100 * ======== getRevisionNumber ========
101 * Returns the major and minor revision number for the Cortex-A
102 * processor as a 2-nibble quantity [Major revision: Minor revision]
103 *
104 * This API is used internally by different modules to check
105 * the ARM IP revision number and determine whether or not an
106 * errata applies and requires a workaround.
107 */
108 UInt8 getRevisionNumber();
109
110 /*!
111 * @_nodoc
112 * ======== notifySpinLock ========
113 */
114 UInt notifySpinLock();
115
116 /*!
117 * @_nodoc
118 * ======== notifySpinUnlock ========
119 */
120 Void notifySpinUnlock(UInt key);
121
122 /*!
123 * @_nodoc
124 * ======== notify ========
125 * notify all cores specified by 'cpuMask' to execute callback function
126 * and wait for other cores to complete operation.
127 *
128 * @param(func) The callback function that is called by each
129 * interrupted core. If function pointer is NULL,
130 * the IPC handler simply returns.
131 * @param(arg) Argument to be passed to the callback function.
132 * @param(cpuMask) Bit mask of all CPUs that should be interrupted.
133 * If the MPCore sub-system has 4 CPUs and all need
134 * to be interrupted, a bit mask of 0b1111 or 0xF
135 * needs to be passed to Core_notify().
136 *
137 * @a(NOTE)
138 * SGI numbers 0, 1, 2 ..., N, where N is the number of cores in MPCore
139 * sub-system, are reserved for the internal use of the kernel.
140 *
141 * @a(NOTE)
142 * The call to this function should be protected with a
143 * Core_notifySpinLock()/Core_notifySpinUnlock(). This function should
144 * not be called with the inter-core lock already taken or it will spin
145 * forever as the other cores will not be able to service the notify
146 * interrupts.
147 */
148 Void notify(IpcFuncPtr func, UArg arg, UInt cpuMask);
149
150 internal:
151
152 153 154 155
156 struct IpcMsg {
157 IpcFuncPtr func;
158 UArg arg;
159 };
160
161 config GateSmp.Handle gate;
162
163 config Bool initStackFlag = true;
164
165 166 167
168 Void startCoreX();
169
170 171 172
173 Void exit(UArg arg);
174
175 176 177 178 179
180 Void hwiFunc(UArg arg);
181
182 183 184 185
186 Void startup();
187
188 /*!
189 * ======== atexit ========
190 * atexit() func used to signal the other core to halt
191 */
192 Void atexit(Int arg);
193
194 struct Module_State {
195 Bool startupCalled;
196 Bool gateEntered[];
197 UInt schedulerInts[];
198 UInt interrupts[][];
199 volatile Bool syncCores[][];
200 volatile IpcMsg ipcMsg[];
201 volatile Bool notifyLock;
202 };
203 }