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32
33 34 35 36
37 package ti.sysbios.family.arm.m3;
38
39 import xdc.rov.ViewInfo;
40 import xdc.runtime.Diags;
41 import xdc.runtime.Log;
42 import xdc.runtime.Assert;
43 import xdc.runtime.Error;
44 import xdc.runtime.Types;
45
46 import ti.sysbios.BIOS;
47 import ti.sysbios.interfaces.IHwi;
48
49 /*!
50 * ======== Hwi ========
51 * Cortex M3/M4 Hardware Interrupt Manager
52 *
53 * The Cortex-M devices' Nested Vectored Interrupt Controller (NVIC)
54 * supports up to 256 interrupts/exceptions. In practice, most
55 * devices support much fewer (ie the SimpleLink CC13XX/CC26XX
56 * family of devices have only 50 total interrupts defined).
57 *
58 * SYS/BIOS Interrupt IDs or interrupt numbers correspond
59 * to an interrupt's position in the interrupt vector table.
60 *
61 * ID 0 corresponds to vector 0 which is used by the NVIC
62 * to hold the initial (reset) stack pointer value.
63 *
64 * ID 1 corresponds to vector 1 which is the reset vector which is
65 * usually initialized to point to an application's entry point
66 * (ie for the TI compiler tool chain, the entry point is "_c_int00")
67 *
68 * IDs 2-13 are, by default, hard wired to the internal exception handler
69 * which will save important context information that can be viewed
70 * using the ROV tool within either the Code Composer Studio debugger
71 * or the IAR Workbench debugger.
72 *
73 * ID 14 is the "pendSV" handler which is used exclusively by the shared
74 * interrupt dispatcher to orchestrate the execution of
75 * {@link ti.sysbios.knl.Swi Swis} posted
76 * from within interrupts, as well as to manage asynchronous
77 * task pre-emption upon returning from interrupts which have
78 * readied a task of higher priority than the task that
79 * was interrupted.
80 *
81 * ID 15 is the SysTick timer interrupt.
82 *
83 * ID's 16-255 are mapped to the NVIC's "User" interrupts 0-239
84 * which are tied to platform specific interrupt sources.
85 *
86 * @a(Zero Latency Interrupts)
87 * The M3/M4 Hwi module supports "zero latency" interrupts.
88 * Interrupts configured with priority greater (in actual
89 * hardware priority, but lower in number) than the configured
90 * {@link #disablePriority Hwi.disablePriority} are NOT
91 * disabled by {@link #disable Hwi_disable()}, and they are not managed by
92 * the internal interrupt dispatcher.
93 *
94 * Zero Latency interrupts fall into the commonly used category
95 * of "Unmanaged Interrupts". However they are somewhat distinct from
96 * that definition in that in addition to being unmanaged, they are
97 * also almost never disabled by SYS/BIOS code, thus gaining the
98 * "Zero Latency" title.
99 *
100 * Zero latency interrupts are distinguished from regular dispatched
101 * interrupts at create time solely by their interrupt priority being
102 * set greater than the configured Hwi.disablePriority.
103 *
104 * Note that since zero latency interrupts don't use the dispatcher,
105 * the {@link ti.sysbios.interfaces.IHwi#arg arg} parameter is not
106 * functional. Also note that due to the Cortex-M's native automatic
107 * stacking of saved-by-caller C context on the way to an ISR, zero
108 * latency interrupt handlers are implemented using regular C functions
109 * (ie no 'interrupt' keyword is required).
110 *
111 * @a(WARNING)
112 * Zero latency interrupts are NOT HANDLED by the SYS/BIOS
113 * interrupt dispatcher! Instead, they are vectored to directly.
114 * As such, and because they are NOT DISABLED BY Hwi_disable(),
115 * these interrupt handlers are SEVERELY RESTRICTED in terms of the
116 * SYS/BIOS APIs they can invoke and THREAD SAFETY MUST BE CAREFULLY
117 * CONSIDERED! See the descriptions of {@link #disable Hwi_disable()} and
118 * and {@link #disablePriority Hwi.disablePriority} for more details.
119 *
120 * @a(Interrupt Masking Options)
121 *
122 * The NVIC interrupt controller is designed for priority based
123 * interrupts.
124 *
125 * In this Hwi module, the {@link #maskSetting} instance configuration
126 * parameter is ignored.
127 * Effectively, only the {@link #MaskingOption_LOWER} is supported.
128 *
129 * @a(Interrupt Priorities)
130 *
131 * In general, the NVIC supports priority values of 0 thru 255.
132 *
133 * In practice, the number of priorities and their values are device
134 * dependent, and their nesting behaviors depend on the
135 * {@link #priGroup Hwi.priGroup} setting.
136 *
137 * For most TI MCU devices, 8 priorities are supported. A peculiarity
138 * of ARM's NVIC is that, although the priority field is an 8 bit value,
139 * the range of supported priority values are left-justified within this
140 * 8 bit field. Consequently, the 8 priority values are not 0 thru 7 as
141 * one might expect, but rather:
142 *
143 * @p(code)
144 * 0x00 // highest priority, non dispatched, Zero Latency priority
145 * 0x20 // highest dispatched interrupt priority
146 * 0x40
147 * 0x60
148 * 0x80
149 * 0xa0
150 * 0xc0
151 * 0xe0 // lowest dispatched interrupt priority, (default)
152 * @p
153 *
154 * Priority 0 is the highest priority and by default is
155 * reserved for zero latency interrupts
156 * (see {@link #disablePriority Hwi.disablePriority}).
157 *
158 * See the {@link http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/CIHIGCIF.html Cortex M4 Devices Generic User Guide}
159 * for details on the behavior of interrupt priorities and their relationship
160 * to the {@link #priGroup Hwi.priGroup} setting.
161 *
162 * @a(Interrupt Vector Tables)
163 * SimpleLink CC13XX/CC26XX devices:
164 *
165 * By default, two vector tables are created for SimpleLink devices:
166 *
167 * A 15 entry boot vector table is placed at address 0x00000000 in
168 * FLASH.
169 *
170 * A 50 entry vector table is placed at address 0x20000000 in RAM.
171 *
172 * The FLASH boot vector table contains the reset vector and exception
173 * handler vectors used until the RAM based vector table is initialized.
174 *
175 * The RAM vector table contains those same first 15 vectors as well as
176 * the SysTick vector and the remainder of the user interrupt vectors.
177 *
178 * During system startup, the NVIC Vector Table Offset Registor is
179 * intialized to point to the RAM vector table after it has been
180 * initialized.
181 *
182 * @a( )
183 * Dual M3/M4 Core ('Ducati'/'Benelli') devices:
184 *
185 * By default, Ducati/Benelli core 0 places its runtime vector table at
186 * address 0x00000400 and core 1 places its runtime vector table at
187 * address 0x00000800.
188 *
189 * Additionally, a boot vector table is placed at address
190 * 0x00000000 which is shared by both cores.
191 *
192 * The boot reset vector function determines which core it is being
193 * executed on and jumps to the reset vector contained in its corresponding
194 * runtime vector table.
195 *
196 * The generation and placement of these vector tables is made
197 * automatically when the
198 * {@link ti.sysbios.family.arm.ducati.Core} module is used.
199 *
200 * Although STRONGLY discouraged, this default behavior can be overridden
201 * by explicitly setting the
202 * {@link #resetVectorAddress Hwi.resetVectorAddress} and
203 * {@link #vectorTableAddress Hwi.vectorTableAddress} config parameters.
204 *
205 * @a(Restrictions)
206 * When used within a dual M3/M4 core (Ducati/Benelli) arrangement, care
207 * must be taken when initializing this shared resource.
208 * The "Shared Resources" note provided
209 * in the {@link ti.sysbios.family.arm.ducati ducati} package discusses
210 * the management of the various hardware and software resources
211 * shared by the two M3/M4 cores.
212 * @a
213 *
214 * @p(html)
215 * <h3> Calling Context </h3>
216 * <table border="1" cellpadding="3">
217 * <colgroup span="1"></colgroup> <colgroup span="5" align="center"></colgroup>
218 *
219 * <tr><th> Function </th><th> Hwi </th><th> Swi </th><th> Task </th><th> Main </th><th> Startup </th></tr>
220 * <!-- -->
221 * <tr><td> {@link #clearInterrupt} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
222 * <tr><td> {@link #create} </td><td> N </td><td> N </td><td> Y </td><td> Y </td><td> N </td></tr>
223 * <tr><td> {@link #disable} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
224 * <tr><td> {@link #disableInterrupt} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
225 * <tr><td> {@link #enable} </td><td> Y </td><td> Y </td><td> Y </td><td> N </td><td> N </td></tr>
226 * <tr><td> {@link #enableInterrupt} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
227 * <tr><td> {@link #Params_init} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
228 * <tr><td> {@link #restore} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
229 * <tr><td> {@link #restoreInterrupt} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
230 * <tr><td> {@link #construct} </td><td> N </td><td> N </td><td> Y </td><td> Y </td><td> N </td></tr>
231 * <tr><td> {@link #delete} </td><td> N </td><td> N </td><td> Y </td><td> Y </td><td> N </td></tr>
232 * <tr><td> {@link #destruct} </td><td> N </td><td> N </td><td> Y </td><td> Y </td><td> N </td></tr>
233 * <tr><td> {@link #getHookContext} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
234 * <tr><td> {@link #setFunc} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
235 * <tr><td> {@link #setHookContext} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
236 * <tr><td colspan="6"> Definitions: <br />
237 * <ul>
238 * <li> <b>Hwi</b>: API is callable from a Hwi thread. </li>
239 * <li> <b>Swi</b>: API is callable from a Swi thread. </li>
240 * <li> <b>Task</b>: API is callable from a Task thread. </li>
241 * <li> <b>Main</b>: API is callable during any of these phases: </li>
242 * <ul>
243 * <li> In your module startup after this module is started (e.g. Hwi_Module_startupDone() returns TRUE). </li>
244 * <li> During xdc.runtime.Startup.lastFxns. </li>
245 * <li> During main().</li>
246 * <li> During BIOS.startupFxns.</li>
247 * </ul>
248 * <li> <b>Startup</b>: API is callable during any of these phases:</li>
249 * <ul>
250 * <li> During xdc.runtime.Startup.firstFxns.</li>
251 * <li> In your module startup before this module is started (e.g. Hwi_Module_startupDone() returns FALSE).</li>
252 * </ul>
253 * </ul>
254 * </td></tr>
255 *
256 * </table>
257 * @p
258 */
259
260
261 @Template("./Hwi.xdt")
262 @ModuleStartup
263 @InstanceInitStatic
264
265
266 module Hwi inherits ti.sysbios.interfaces.IHwi
267 {
268
269
270 /*!
271 * The Cortex M3/M4 NVIC supports up to 256 interrupts/exceptions.
272 *
273 * The actual number supported is device specific and provided by
274 * the catalog device specification.
275 */
276 config Int NUM_INTERRUPTS;
277
278 /*!
279 * The Cortex M3/M4 NVIC supports up to 256 interrupt priorities.
280 *
281 * The actual number supported is device specific and provided by
282 * the catalog device specification. For all TI SimpleLink devices,
283 * 8 priorities are supported.
284 */
285 config Int NUM_PRIORITIES;
286
287
288
289 /*! Hwi vector function type definition. */
290 typedef Void (*VectorFuncPtr)(void);
291
292 /*! Exception hook function type definition. */
293 typedef Void (*ExceptionHookFuncPtr)(ExcContext *);
294
295 /*! NVIC Configuration Control Register (CCR). */
296 struct CCR {
297 Bits8 STKALIGN; /*! Auto stack alignment in exception */
298 Bits8 BFHFNMIGN; /*! All faults ignore BUS Faults */
299 Bits8 DIV_0_TRP; /*! Trap on divide by zero */
300 Bits8 UNALIGN_TRP; /*! Trap on all unaligned accesses */
301 Bits8 USERSETMPEND; /*! Allow user to trigger interrupts */
302 Bits8 NONEBASETHRDENA; /*! Allow entering thread mode anytime */
303 };
304
305 /*! @_nodoc
306 * Nested Vectored Interrupt Controller.
307 */
308 struct NVIC {
309 UInt32 RES_00; /*! 0xE000E000 reserved */
310 UInt32 ICTR; /*! 0xE000E004 Interrupt Control Type */
311 UInt32 RES_08; /*! 0xE000E008 reserved */
312 UInt32 RES_0C; /*! 0xE000E00C reserved */
313 UInt32 STCSR; /*! 0xE000E010 SysTick Control & Status Register */
314 UInt32 STRVR; /*! 0xE000E014 SysTick Reload Value Register */
315 UInt32 STCVR; /*! 0xE000E018 SysTick Current Value Register */
316 UInt32 STCALIB; /*! 0xE000E01C SysTick Calibration Value Register */
317 UInt32 RES_20 [56]; /*! 0xE000E020-0xE000E0FC reserved */
318 UInt32 ISER [8]; /*! 0xE000E100-0xE000E11C Interrupt Set Enable Registers */
319 UInt32 RES_120 [24]; /*! 0xE000E120-0xE000E17C reserved */
320 UInt32 ICER [8]; /*! 0xE000E180-0xE000E19C Interrupt Clear Enable Registers */
321 UInt32 RES_1A0 [24]; /*! 0xE000E1A0-0xE000E1FC reserved */
322 UInt32 ISPR [8]; /*! 0xE000E200-0xE000E21C Interrupt Set Pending Registers */
323 UInt32 RES_220 [24]; /*! 0xE000E220-0xE000E7C reserved */
324 UInt32 ICPR [8]; /*! 0xE000E280-0xE000E29C Interrupt Clear Pending Registers */
325 UInt32 RES_2A0 [24]; /*! 0xE000E2A0-0xE000E2FC reserved */
326 UInt32 IABR [8]; /*! 0xE000E300-0xE000E31C Interrupt Active Bit Registers */
327 UInt32 RES_320 [56]; /*! 0xE000E320-0xE000E3FC reserved */
328 UInt8 IPR [240]; /*! 0xE000E400-0xE000E4EF Interrupt Priority Registers */
329 UInt32 RES_4F0 [516];/*! 0xE000E4F0-0xE000ECFC reserved */
330 UInt32 CPUIDBR; /*! 0xE000ED00 CPUID Base Register */
331 UInt32 ICSR; /*! 0xE000ED04 Interrupt Control State Register */
332 UInt32 VTOR; /*! 0xE000ED08 Vector Table Offset Register */
333 UInt32 AIRCR; /*! 0xE000ED0C Application Interrupt/Reset Control Register */
334 UInt32 SCR; /*! 0xE000ED10 System Control Register */
335 UInt32 CCR; /*! 0xE000ED14 Configuration Control Register */
336 UInt8 SHPR[12]; /*! 0xE000ED18 System Handlers 4-15 Priority Registers */
337 UInt32 SHCSR; /*! 0xE000ED24 System Handler Control & State Register */
338 UInt8 MMFSR; /*! 0xE000ED28 Memory Manage Fault Status Register */
339 UInt8 BFSR; /*! 0xE000ED29 Bus Fault Status Register */
340 UInt16 UFSR; /*! 0xE000ED2A Usage Fault Status Register */
341 UInt32 HFSR; /*! 0xE000ED2C Hard Fault Status Register */
342 UInt32 DFSR; /*! 0xE000ED30 Debug Fault Status Register */
343 UInt32 MMAR; /*! 0xE000ED34 Memory Manager Address Register */
344 UInt32 BFAR; /*! 0xE000ED38 Bus Fault Address Register */
345 UInt32 AFSR; /*! 0xE000ED3C Auxiliary Fault Status Register */
346 UInt32 PFR0; /*! 0xE000ED40 Processor Feature Register */
347 UInt32 PFR1; /*! 0xE000ED44 Processor Feature Register */
348 UInt32 DFR0; /*! 0xE000ED48 Debug Feature Register */
349 UInt32 AFR0; /*! 0xE000ED4C Auxiliary Feature Register */
350 UInt32 MMFR0; /*! 0xE000ED50 Memory Model Fault Register0 */
351 UInt32 MMFR1; /*! 0xE000ED54 Memory Model Fault Register1 */
352 UInt32 MMFR2; /*! 0xE000ED58 Memory Model Fault Register2 */
353 UInt32 MMFR3; /*! 0xE000ED5C Memory Model Fault Register3 */
354 UInt32 ISAR0; /*! 0xE000ED60 ISA Feature Register0 */
355 UInt32 ISAR1; /*! 0xE000ED64 ISA Feature Register1 */
356 UInt32 ISAR2; /*! 0xE000ED68 ISA Feature Register2 */
357 UInt32 ISAR3; /*! 0xE000ED6C ISA Feature Register3 */
358 UInt32 ISAR4; /*! 0xE000ED70 ISA Feature Register4 */
359 UInt32 RES_D74[5]; /*! 0xE000ED74-0xE000ED84 reserved */
360 UInt32 CPACR; /*! 0xE000ED88 Coprocessor Access Control Register */
361 UInt32 RES_D8C[93]; /*! 0xE000ED8C-0xE000EEFC reserved */
362 UInt32 STI; /*! 0xE000EF00 Software Trigger Interrupt Register */
363 UInt32 RES_F04[12]; /*! 0xE000EF04-0xE000EF30 reserved */
364 UInt32 FPCCR; /*! 0xE000EF34 FP Context Control Register */
365 UInt32 FPCAR; /*! 0xE000EF38 FP Context Address Register */
366 UInt32 FPDSCR; /*! 0xE000EF3C FP Default Status Control Register */
367 UInt32 MVFR0; /*! 0xE000EF40 Media & FP Feature Register0 */
368 UInt32 MVFR1; /*! 0xE000EF44 Media & FP Feature Register1 */
369 UInt32 RES_F48[34]; /*! 0xE000EF48-0xE000EFCC reserved */
370 UInt32 PID4; /*! 0xE000EFD0 Peripheral ID Register4 */
371 UInt32 PID5; /*! 0xE000EFD4 Peripheral ID Register5 */
372 UInt32 PID6; /*! 0xE000EFD8 Peripheral ID Register6 */
373 UInt32 PID7; /*! 0xE000EFDC Peripheral ID Register7 */
374 UInt32 PID0; /*! 0xE000EFE0 Peripheral ID Register0 */
375 UInt32 PID1; /*! 0xE000EFE4 Peripheral ID Register1 */
376 UInt32 PID2; /*! 0xE000EFE8 Peripheral ID Register2 */
377 UInt32 PID3; /*! 0xE000EFEC Peripheral ID Register3 */
378 UInt32 CID0; /*! 0xE000EFF0 Component ID Register0 */
379 UInt32 CID1; /*! 0xE000EFF4 Component ID Register1 */
380 UInt32 CID2; /*! 0xE000EFF8 Component ID Register2 */
381 UInt32 CID3; /*! 0xE000EFFC Component ID Register3 */
382 }
383
384 /*!
385 * Physical Nested Vectored Interrupt Controller Device.
386 * Short name is "Hwi_nvic"
387 * Long name is "ti_sysbios_family_arm_m3_Hwi_nvic"
388 */
389 extern volatile NVIC nvic;
390
391 /*!
392 * Virtual Nested Vectored Interrupt Controller structure
393 * written to by both cores for SMP.
394 * Short name is "Hwi_vnvic"
395 * Long name is "ti_sysbios_family_arm_m3_Hwi_vnvic"
396 */
397 extern volatile NVIC vnvic;
398
399 /*!
400 * Exception Context - Register contents at the time of an exception.
401 */
402 struct ExcContext {
403
404 BIOS.ThreadType threadType;
405
406 Ptr threadHandle;
407
408 Ptr threadStack;
409
410
411 SizeT threadStackSize;
412
413
414 Ptr r0;
415 Ptr r1;
416 Ptr r2;
417 Ptr r3;
418 Ptr r4;
419 Ptr r5;
420 Ptr r6;
421 Ptr r7;
422 Ptr r8;
423 Ptr r9;
424 Ptr r10;
425 Ptr r11;
426 Ptr r12;
427 Ptr sp;
428 Ptr lr;
429 Ptr pc;
430 Ptr psr;
431
432
433 Ptr ICSR;
434 Ptr MMFSR;
435 Ptr BFSR;
436 Ptr UFSR;
437 Ptr HFSR;
438 Ptr DFSR;
439 Ptr MMAR;
440 Ptr BFAR;
441 Ptr AFSR;
442 }
443
444 struct Struct2__ {
445 Ptr fxns;
446 UArg arg;
447 FuncPtr fxn;
448 Irp irp;
449 UInt8 priority;
450 Int16 intNum;
451 Ptr hookEnv;
452 Types.CordAddr name;
453 };
454
455 typedef Struct2__ Struct2;
456
457 /*! @_nodoc */
458 metaonly struct BasicView {
459 Ptr halHwiHandle;
460 String label;
461 String type;
462 Int intNum;
463 Int priority;
464 Int group;
465 Int subPriority;
466 String fxn;
467 UArg arg;
468 };
469
470 /*! @_nodoc */
471 metaonly struct DetailedView {
472 Ptr halHwiHandle;
473 String label;
474 String type;
475 Int intNum;
476 Int priority;
477 Int group;
478 Int subPriority;
479 String fxn;
480 UArg arg;
481 Ptr irp;
482 String status;
483 Int coreId;
484 };
485
486 /*! @_nodoc */
487 metaonly struct ModuleView {
488 String options[4];
489 String processorState;
490 String activeInterrupt;
491 String pendingInterrupt;
492 String exception;
493 String hwiStackPeak;
494 SizeT hwiStackSize;
495 Ptr hwiStackBase;
496 };
497
498 /*! @_nodoc */
499 metaonly struct VectorTableView {
500 UInt vectorNum;
501 Ptr vector;
502 String vectorLabel;
503 String type;
504 String priority;
505 Int preemptPriority;
506 Int subPriority;
507 String status;
508 String hwiHandle;
509 String hwiFxn;
510 UArg hwiArg;
511 Ptr hwiIrp;
512 };
513
514 /*! @_nodoc */
515 @Facet
516 metaonly config ViewInfo.Instance rovViewInfo =
517 ViewInfo.create({
518 viewMap: [
519 ['Basic',
520 {
521 type: ViewInfo.INSTANCE,
522 viewInitFxn: 'viewInitBasic',
523 structName: 'BasicView'
524 }
525 ],
526 ['Detailed',
527 {
528 type: ViewInfo.INSTANCE,
529 viewInitFxn: 'viewInitDetailed',
530 structName: 'DetailedView'
531 }
532 ],
533 ['Module',
534 {
535 type: ViewInfo.MODULE,
536 viewInitFxn: 'viewInitModule',
537 structName: 'ModuleView'
538 }
539 ],
540 ['Exception',
541 {
542 type: ViewInfo.TREE,
543 viewInitFxn: 'viewInitException',
544 structName: 'ExcContext'
545 }
546 ],
547 ['Vector Table',
548 {
549 type: ViewInfo.MODULE_DATA,
550 viewInitFxn: 'viewInitVectorTable',
551 structName: 'VectorTableView'
552 }
553 ]
554 ]
555 });
556
557
558
559
560
561 /*!
562 * Issued just prior to Hwi function invocation (with interrupts disabled)
563 */
564 config Log.Event LM_begin = {
565 mask: Diags.USER1 | Diags.USER2,
566 msg: "LM_begin: hwi: 0x%x, func: 0x%x, preThread: %d, intNum: %d, irp: 0x%x"
567 };
568
569 /*!
570 * Issued just after return from Hwi function (with interrupts disabled)
571 */
572 config Log.Event LD_end = {
573 mask: Diags.USER2,
574 msg: "LD_end: hwi: 0x%x"
575 };
576
577
578
579 /*! Assert when bad maskSetting parameter provided */
580 config Assert.Id A_unsupportedMaskingOption = {
581 msg: "A_unsupportedMaskingOption: unsupported maskSetting."
582 };
583
584
585
586 /*!
587 * Error raised if an attempt is made to create a Hwi
588 * with an interrupt number greater than Hwi_NUM_INTERRUPTS - 1.
589 */
590 config Error.Id E_badIntNum = {
591 msg: "E_badIntNum, intnum: %d is out of range"
592 };
593
594 /*!
595 * Error raised when Hwi is already defined
596 */
597 config Error.Id E_alreadyDefined = {
598 msg: "E_alreadyDefined: Hwi already defined: intr# %d"
599 };
600
601 /*!
602 * Error raised when the number of interrupts being created
603 * exceeds the number supported.
604 */
605 config Error.Id E_hwiLimitExceeded = {
606 msg: "E_hwiLimitExceeded: Too many interrupts defined"
607 };
608
609 /*!
610 * Error raised when an exception occurs
611 */
612 config Error.Id E_exception = {
613 msg: "E_exception: id = %d, pc = %08x.\nTo see more exception detail, set ti.sysbios.family.arm.m3.Hwi.enableException = true or,\nexamine the Exception view for the ti.sysbios.family.arm.m3.Hwi module using ROV."
614 };
615
616 /*!
617 * Error raised when an uninitialized interrupt occurs
618 */
619 config Error.Id E_noIsr = {
620 msg: "E_noIsr: id = %d, pc = %08x"
621 };
622
623 /*!
624 * Error raised when NMI exception occurs
625 */
626 config Error.Id E_NMI = {
627 msg: "E_NMI: %s"
628 };
629
630 /*!
631 * Error raised when hard fault exception occurs
632 */
633 config Error.Id E_hardFault = {
634 msg: "E_hardFault: %s"
635 };
636
637 /*!
638 * Error raised when memory fault exception occurs
639 */
640 config Error.Id E_memFault = {
641 msg: "E_memFault: %s, address: %08x"
642 };
643
644 /*!
645 * Error raised when bus fault exception occurs
646 */
647 config Error.Id E_busFault = {
648 msg: "E_busFault: %s, address: %08x"
649 };
650
651 /*!
652 * Error raised when usage fault exception occurs
653 */
654 config Error.Id E_usageFault = {
655 msg: "E_usageFault: %s"
656 };
657
658 /*!
659 * Error raised when svCall exception occurs
660 */
661 config Error.Id E_svCall = {
662 msg: "E_svCall: svNum = %d"
663 };
664
665 /*!
666 * Error raised when debugMon exception occurs
667 */
668 config Error.Id E_debugMon = {
669 msg: "E_debugMon: %s"
670 };
671
672 /*!
673 * Error raised when reserved exception occurs
674 */
675 config Error.Id E_reserved = {
676 msg: "E_reserved: %s %d"
677 };
678
679
680
681 /*!
682 * Size (in number of interrupts) of the table used by the interrupt
683 * dispatcher to locate the corresponding Hwi object. By default,
684 * Hwi.dispatchTableSize will be internally set
685 * to the number of interrupts supported by the device.
686 *
687 * When the Hwi dispatch table size is equal to the number of interrupts
688 * supported {@link #NUM_INTERRUPTS} by the device, a linear-indexed
689 * dispatch table mechanism is used that will consume 4 bytes of RAM
690 * for each interrupt supported.
691 *
692 * If the dispatch table size is set to a number less than the number
693 * of interrupts supported by the device, then a non linear-indexed
694 * dispatch table mechanism is employed that uses 12 bytes of RAM for
695 * each interrupt supported.
696 *
697 * Consequently, for applications that use less than 1/3 of the total
698 * number of interrupts supported by the device, setting this parameter
699 * to the number of interrupts ACTUALLY USED will result in less RAM
700 * memory being used than otherwise.
701 *
702 * For applications that use very few interrupts, this can be a significant RAM memory savings.</p>
703 */
704 metaonly config UInt dispatchTableSize;
705
706 /*!
707 * Location of the Runtime Interrupt Vector Table.
708 * Default is device dependent.
709 *
710 * This parameter allows the user to override the default placement
711 * of the runtime interrupt vector table.
712 * The NVIC's Vector Table Offset
713 * Register (VTOR) is also programmed to this value.
714 *
715 * Some systems require the runtime vector table to be placed at
716 * an address
717 * other than 0 but still need a copy of the two M3/M4 boot vectors
718 * (SP and reset PC), located there. To achieve this, a separate
719 * parameter {@link #resetVectorAdress} is provided. If the
720 * resetVectorAddress has a different value then the vectorTableAddress
721 * then a separate vector table is generated and placed at that
722 * address.
723 *
724 * The vector table must be placed at an address at or lower than
725 * 0x3FFFFC00 and must be aligned on an even 64 word boundary.
726 */
727 metaonly config Ptr vectorTableAddress = 0x00000000;
728
729 /*!
730 * Reset vector table address. Default is 0x00000000.
731 *
732 * This parameter is the address of the vector table used
733 * at system reset time. Typically this is placed at 0x00000000.
734 *
735 * If the Hwi.resetVectorAddress has a different value than
736 * the {@link #vectorTableAddress Hwi.vectorTableAddress}
737 * then two vector tables are generated, one at the Hwi.resetVectorAddress
738 * and another at the {@link #vectorTableAddress Hwi.vectorTableAddress}.
739 *
740 * After the initial boot code has been executed at startup, the NVIC's
741 * Vector Table Offset Register will be programmed to point to the
742 * vector table at the {@link #vectorTableAddress Hwi.vectorTableAddress}.
743 *
744 * is created and placed in the ".resetVecs" section.
745 */
746 metaonly config Ptr resetVectorAddress = 0x00000000;
747
748 /*! Reset Handler (ID/vector #1). Default is c_int00 */
749 metaonly config VectorFuncPtr resetFunc;
750
751 /*! NMI Handler (ID/vector #2). Default is set to an internal exception handler */
752 metaonly config VectorFuncPtr nmiFunc;
753
754 /*! Hard Fault Handler (ID/vector #3). Default is set to an internal exception handler */
755 metaonly config VectorFuncPtr hardFaultFunc;
756
757 /*! Mem Fault Handler (ID/vector #4). Default is set to an internal exception handler */
758 metaonly config VectorFuncPtr memFaultFunc;
759
760 /*! Bus Fault Handler (ID/vector #5). Default is set to an internal exception handler */
761 metaonly config VectorFuncPtr busFaultFunc;
762
763 /*! Usage Fault Handler (ID/vector #6). Default is set to an internal exception handler */
764 metaonly config VectorFuncPtr usageFaultFunc;
765
766 /*! SVCall Handler (ID/vector #11). Default is set to an internal exception handler */
767 metaonly config VectorFuncPtr svCallFunc;
768
769 /*! Debug Mon Handler (ID/vector #12). Default is set to an internal exception handler */
770 metaonly config VectorFuncPtr debugMonFunc;
771
772 /*! Reserved Exception Handler (ID/vector #13). Default is set to an internal exception handler */
773 metaonly config VectorFuncPtr reservedFunc;
774
775 /*! Uninitialized ISR Handler. Default is set to an internal exception handler */
776 config VectorFuncPtr nullIsrFunc;
777
778 /*! Hwi exception handler function type definition. */
779 typedef Void (*ExcHandlerFuncPtr)(UInt *, UInt);
780
781 /*!
782 * Exception handler function pointer.
783 *
784 * The default is determined by the value of Hwi.enableException.
785 *
786 * If the user does NOT set this parameter, then the following default
787 * behavior is followed:
788 *
789 * If Hwi.enableException is true, then the internal 'Hwi_excHandlerMax'
790 * function is used. This exception handler saves the exception context
791 * then does a complete exception decode and dump to the console, then
792 * raises an Error. The exception context can be viewed within CCS
793 * in the ROV Hwi module's Exception view.
794 *
795 * If Hwi.enableException is false, then the internal 'Hwi_excHandlerMin'
796 * function is used. This exception handler saves the exception context
797 * then raises an Error. The exception context can be viewed within CCS
798 * in the ROV Hwi module's Exception view.
799 *
800 * If the user sets this parameter to their own function, then the user's
801 * function will be invoked with the following arguments:
802 *
803 * Void myExceptionHandler(UInt *excStack, UInt lr);
804 *
805 * Where 'excStack' is the address of the stack containing the
806 * register context at the time of the exception, and 'lr' is the
807 * link register value when the low-level-assembly-coded exception
808 * handler was vectored to.
809 *
810 * If this parameter is set to 'null', then an infinite while loop is
811 * entered when an exception occurs. This setting minimizes code and
812 * data footprint but provides no automatic exception decoding.
813 */
814 config ExcHandlerFuncPtr excHandlerFunc = excHandlerMax;
815
816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842
843 metaonly config UInt8 intAffinity[];
844
845 /*!
846 * Enable full exception decoding
847 *
848 * When this is enabled, the exception handler will fully
849 * decode an exception and dump the registers to the
850 * system console.
851 */
852 metaonly config Bool enableException = true;
853
854 /*!
855 * User Exception Context Buffer Address
856 *
857 * By default, when an exception occurs, an {@link #ExcContext}
858 * structure is allocated on the ISR stack and filled in within the
859 * exception handler.
860 *
861 * If {@link #excContextBuffer} is initialized by the user, the
862 * {@link #ExcContext} structure will be placed at that address instead.
863 *
864 * The buffer must be large enough to contain an {@link #ExcContext}
865 * structure.
866 */
867 metaonly config Ptr excContextBuffer;
868 metaonly config Ptr excContextBuffers[];
869
870 /*!
871 * User Exception Stack Buffer Address
872 *
873 * By default, when an exception occurs, a pointer to the base address
874 * of the stack being used by the thread causing the exception is placed
875 *
876 * If {@link #excStackBuffer} is initialized by the user, the
877 * stack contents of the thread causing the exception will be
878 * copied to that address instead.
879 *
880 * The buffer must be large enough to contain the largest task stack
881 * or ISR stack defined in the application.
882 */
883 metaonly config Ptr excStackBuffer;
884 metaonly config Ptr excStackBuffers[];
885
886
887 /*!
888 * User Exception hook function.
889 *
890 * Called just after the exception context has been initialized.
891 *
892 * This function will be run on the ISR stack.
893 *
894 * This function must run to completion.
895 *
896 * It is called without any Task or Swi scheduling protection
897 * and therefore can not call any functions that may cause a Swi or Task
898 * scheduling operation (Swi_post(), Semaphore_post(), Event_post(), etc).
899 */
900 config ExceptionHookFuncPtr excHookFunc = null;
901 config ExceptionHookFuncPtr excHookFuncs[];
902
903 /*!
904 * NVIC CCR register settings
905 *
906 * These setting are written to Hwi_nvic.CCR at startup time.
907 *
908 * See the {@link http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/Bhcjabhi.html Configuration and Control Register}
909 * description provided by ARM for more details
910 * on the meanings of these parameters.
911 */
912 metaonly config CCR nvicCCR = {
913 STKALIGN: 1,
914 BFHFNMIGN: 0,
915 DIV_0_TRP: 0,
916 UNALIGN_TRP: 0,
917 USERSETMPEND: 0,
918 NONEBASETHRDENA: 0
919 };
920
921 /*!
922 * The priority that BASEPRI is set to by Hwi_disable().
923 *
924 * All interrupts configured with equal or less priority (equal or
925 * higher number) than disablePriority are disabled by
926 * {@link #disable Hwi_disable}.
927 * Interrupts configured with higher priority (smaller number) than
928 * Hwi.disablePriority are non-maskable (ie zero-latency).
929 *
930 * The default setting is the second highest interrupt priority
931 * defined for the device (typically '0x20' for devices
932 * which support 8 priority values).
933 * This results in priority 0 (and all
934 * other values in the same priority group, ie 0x00 thru 0x1f)
935 * being the zero-latency, non-maskable interrupt priority.
936 * All other priorities are disabled with Hwi_disable().
937 */
938
939 config UInt disablePriority;
940
941 /*!
942 * The PRIGROUP setting. Default is 0.
943 *
944 * This value will be written to the PRIGROUP field
945 * within the NVIC's Application Interrupt and Reset Control
946 * Register (Hwi_nvic.AIRCR). It defines how the 8 bit priority
947 * values are interpreted by the hardware.
948 *
949 * Valid settings are 0-7.
950 *
951 * The default setting of 0 causes bits 7-1 of an interrupt's
952 * priority value to be used as pre-emption priority, while bit 0
953 * is used to determine which of two simultaneous interrupts with
954 * the same pre-emption priority will be serviced first.
955 *
956 * For most TI MCU devices, this means that each of the 8 supported
957 * priority values are unique pre-emption priorities and are not
958 * subdivided into priority groups.
959 *
960 * For more details regarding priority groups see the
961 * {@link http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/Cihehdge.html AIRCR}
962 * register description provided by ARM.
963 */
964 config UInt priGroup = 0;
965
966 /*!
967 * Generate linker commands to place vector tables. Default is true.
968 *
969 * When set to true (the default), then
970 * {@link #resetVectorAddress Hwi.resetVectorAddress}
971 * and {@link #vectorTableAddress Hwi.vectorTableAddress} are used to place
972 * the reset and runtime vector tables.
973 *
974 * When set to false, it is up to the user to provide linker commands
975 * to place the sections the vector tables are contained in.
976 *
977 * The following table maps the tool chain used with the section names
978 * for the reset and runtime vector tables:
979 *
980 * @p(code)
981 * Tool Chain Reset Vectors Runtime Vectors
982 * TI .resetVecs .vecs
983 * TI CLANG .resetVecs .vecs
984 * GNU .intvecs .vtable
985 * IAR .intvec .vecs
986 * @p
987 *
988 */
989 metaonly config Bool placeVectorTables = true;
990
991
992
993 /*!
994 * ======== construct2 ========
995 * Construct a Hwi object
996 *
997 * Hwi_construct2 constructs a Hwi object. This function is identical
998 * to Hwi_construct(), but does not take an Error_Block parameter, and
999 * returns a Hwi_Handle.
1000 *
1001 * The following C code sets Hwi parameters and
1002 * constructs a Hwi object:
1003 *
1004 * @p(code)
1005 *
1006 * Hwi_Struct2 hwiStruct2;
1007 * Hwi_Handle hwi;
1008 *
1009 * Void main()
1010 * {
1011 * Hwi_Params hwiParams;
1012 *
1013 * Hwi_Params_init(&hwiParams);
1014 * hwiParams.arg = (UArg)arg;
1015 * hwiParams.priority = intPriority;
1016 *
1017 * hwi = Hwi_construct2(&hwiStruct2, intNum, hwiFxn, &hwiParams);
1018 * if (hwi == NULL) {
1019 * // Failure
1020 * }
1021 *
1022 * BIOS_start();
1023 * }
1024 * @p
1025 *
1026 * @param(hwi) Pointer to Hwi_Struct2 object.
1027 * @param(intNum) Interrupt priority
1028 * @param(hwiFxn) Hwi Function
1029 * @param(prms) Pointer to Hwi_Params structure
1030 *
1031 * @b(returns) A Hwi handle
1032 */
1033 Handle construct2(Struct2 *hwi, Int intNum, FuncPtr hwiFxn,
1034 const Params *prms);
1035
1036 /*!
1037 * ======== disable ========
1038 * Disable all non zero-latency interrupts
1039 *
1040 * Hwi_disable disables all non zero-latency hardware interrupts and
1041 * returns an
1042 * opaque key indicating whether interrupts were globally enabled or
1043 * disabled on entry to Hwi_disable().
1044 * The actual value of the key is target/device specific and is meant
1045 * to be passed to Hwi_restore().
1046 *
1047 * Call Hwi_disable before a portion of a function that needs
1048 * to run without interruption. When critical processing is complete, call
1049 * Hwi_restore or Hwi_enable to reenable hardware interrupts.
1050 *
1051 * Servicing of interrupts that occur while interrupts are disabled is
1052 * postponed until interrupts are reenabled. However, if the same type
1053 * of interrupt occurs several times while interrupts are disabled,
1054 * the interrupt's function is executed only once when interrupts are
1055 * reenabled.
1056 *
1057 * A context switch can occur when calling Hwi_enable or Hwi_restore if
1058 * an enabled interrupt occurred while interrupts are disabled.
1059 *
1060 * Hwi_disable may be called from main(). However, since Hwi interrupts
1061 * are already disabled in main(), such a call has no effect.
1062 *
1063 * @a(Implementation Note)
1064 * In order to support zero latency interrupts, rather
1065 * than setting PRIMASK (which would globally disable all NVIC
1066 * interrupts), Hwi_disable() instead writes the value of
1067 * {@link #disablePriority Hwi.disablePriority}
1068 * to the BASEPRI register. In doing so, all interrupts of equal or
1069 * lower priority than Hwi.disablePriority are disabled.
1070 *
1071 * @a(constraints)
1072 * If a Task switching API such as
1073 * {@link ti.sysbios.knl.Semaphore#pend Semaphore_pend()},
1074 * {@link ti.sysbios.knl.Semaphore#post Semaphore_post()},
1075 * {@link ti.sysbios.knl.Task#sleep Task_sleep()}, or
1076 * {@link ti.sysbios.knl.Task#yield Task_yield()}
1077 * is invoked which results in a context switch while
1078 * interrupts are disabled, an embedded call to
1079 * {@link #enable Hwi_enable} occurs
1080 * on the way to the new thread context which unconditionally re-enables
1081 * interrupts. Interrupts will remain enabled until a subsequent
1082 * {@link #disable Hwi_disable}
1083 * invocation.
1084 *
1085 * Swis always run with interrupts enabled.
1086 * See {@link ti.sysbios.knl.Swi#post Swi_post()} for a discussion Swis and
1087 * interrupts.
1088 *
1089 * @b(returns) opaque key for use by Hwi_restore()
1090 */
1091 @Macro
1092 override UInt disable();
1093
1094 /*!
1095 * ======== enable ========
1096 */
1097 @Macro
1098 override UInt enable();
1099
1100 /*!
1101 * ======== restore ========
1102 */
1103 @Macro
1104 override Void restore(UInt key);
1105
1106 /*!
1107 * @_nodoc
1108 * ======== disableFxn ========
1109 * function call implementation
1110 */
1111 UInt disableFxn();
1112
1113 /*!
1114 * @_nodoc
1115 * ======== enableFxn ========
1116 * function call implementation
1117 */
1118 UInt enableFxn();
1119
1120 /*!
1121 * @_nodoc
1122 * ======== restoreFxn ========
1123 * function call implementation
1124 */
1125 Void restoreFxn(UInt key);
1126
1127 /*!
1128 * ======== inUseMeta ========
1129 * @_nodoc
1130 * Check for Hwi already in use.
1131 * For internal SYS/BIOS use only.
1132 * Should be called prior to any internal Hwi.create().
1133 *
1134 * @param(intNum) interrupt number
1135 */
1136 metaonly Bool inUseMeta(UInt intNum);
1137
1138 /*!
1139 * ======== plug ========
1140 * Plug a non dispatched interrupt vector with an ISR address.
1141 *
1142 * Used internally by Hwi_create() and Hwi_construct().
1143 *
1144 * This API is provided for external use primarily to allow users
1145 * to plug the NMI vector (interrupt #2) at runtime.
1146 *
1147 * @a(Note)
1148 * Interrupt vectors plugged using Hwi_plug() are NOT managed by
1149 * the Hwi interrupt dispatcher. Consequently, it is not safe to
1150 * call SYS/BIOS APIs from within these ISRs.
1151 *
1152 * @param(intNum) interrupt number
1153 * @param(fxn) pointer to ISR function
1154 */
1155 Void plug(UInt intNum, Void *fxn);
1156
1157 /*!
1158 * ======== getHandle ========
1159 * Returns Hwi_handle associated with intNum
1160 *
1161 * @param(intNum) interrupt number
1162 */
1163 Handle getHandle(UInt intNum);
1164
1165 /*!
1166 * ======== setPriority ========
1167 * Set an interrupt's relative priority.
1168 *
1169 * Valid priorities are 0 - 255. 0 is highest priority.
1170 *
1171 * @a(WARNING)
1172 * Setting the priority of a dispatched Hwi to a value higher
1173 * than {@link #disablePriority Hwi.disablePriority} will make
1174 * it become non-maskable by {@link #disable Hwi_disable()}.
1175 * The behavior of your application after that will be
1176 * unpredictable and will likely yield catastrophic results!
1177 *
1178 * @param(intNum) ID of interrupt
1179 * @param(priority) priority
1180 */
1181 Void setPriority(UInt intNum, UInt priority);
1182
1183 /*!
1184 * ======== excSetBuffers ========
1185 * Set the exception context and stack buffer pointers
1186 *
1187 * @param(excContextBuffer) Address to place ExcContext
1188 * @param(excStackBuffer) Address to place ExcStack
1189 */
1190 Void excSetBuffers(Ptr excContextBuffer, Ptr excStackBuffer);
1191
1192 /*!
1193 * @_nodoc
1194 * ======== initNVIC ========
1195 * initialize everything but leave ints disabled
1196 */
1197 Void initNVIC();
1198
1199 /*!
1200 * @_nodoc
1201 * ======== initStacks ========
1202 * set up M3 split stacks
1203 */
1204 Void initStacks(Ptr hwiStack);
1205
1206 /*!
1207 * @_nodoc
1208 * ======== flushVnvic ========
1209 * Reconfigure a dispatched interrupt.
1210 *
1211 * Called by the internal function "Hwi_updateNvic()".
1212 *
1213 * This is a public API because it is also called by "Core_hwiFunc()".
1214 */
1215 Void flushVnvic();
1216
1217 /*!
1218 * @_nodoc
1219 * ======== testStaticInlines ========
1220 * test function that calls static inline function for code coverage
1221 */
1222 Void testStaticInlines();
1223
1224 instance:
1225
1226 /*!
1227 * Interrupt priority.
1228 * The default is 255 which is the lowest priority.
1229 *
1230 * Priority 0 is the highest priority and by default is
1231 * reserved for zero latency interrupts
1232 * (see {@link #disablePriority}).
1233 *
1234 * Valid priorities values are device dependent and their
1235 * nesting behaviors depend on the {@link #priGroup} setting.
1236 *
1237 * See the Cortex M3 architecture reference manual for details
1238 * on the meanings of these parameters.
1239 */
1240 override config Int priority = 255;
1241
1242 /*!
1243 * Interrupt Masking Option. Only MaskingOption_LOWER is supported.
1244 *
1245 * The NVIC interrupt controller is designed for priority based
1246 * interrupts. No support is provided for anything but
1247 * Hwi.MaskingOption_LOWER.
1248 */
1249 override config IHwi.MaskingOption maskSetting = IHwi.MaskingOption_LOWER;
1250
1251 /*!
1252 * Use the interrupt dispatcher with this interrupt. Default is true.
1253 *
1254 * If set to false, the interrupt dispatcher is NOT used. Instead,
1255 * the configured Hwi function address is placed directly in the
1256 * vector table, which results in the dispatcher being bypassed.
1257 *
1258 * @a(Warning)
1259 * Interrupts configured to bupass the dispatcher are not allowed
1260 * to call ANY SYS/BIOS APIs that effect thread scheduling. Examples
1261 * of API that should no be invoked are:
1262 *
1263 * @p(dlist)
1264 * - Swi_post(),
1265 * - Semaphore_post(),
1266 * - Event_post(),
1267 * - Task_yield()
1268 * @p
1269 *
1270 * Additionally, although the signature for a non-dispatched interrupt
1271 * function is the same as that for a dispatched interrupt
1272 * (see {@link #FuncPtr}), no argument is actually passed
1273 * to the non-dispatched ISR handler.
1274 */
1275 config Bool useDispatcher = true;
1276
1277 /*!
1278 * ======== reconfig ========
1279 * Reconfigure a dispatched interrupt.
1280 */
1281 Void reconfig(FuncPtr fxn, const Params *params);
1282
1283 internal:
1284
1285 /*!
1286 * If Hwi.dispatchTableSize is initialized by the user then
1287 * Hwi.numSparseInterrupts is set to the value of Hwi.dispatchTableSize
1288 *
1289 * If Hwi.dispatchTableSize is NOT set by the user, the normal
1290 * intNum-indexed Hwi dispatchTable mechanism is used by
1291 * the dispatcher to find the corresponding Hwi object.
1292 *
1293 * If Hwi.dispatchTableSize is set by the user, then a
1294 * RAM-based fixed sized interrupt jump table is generated
1295 * that contains a repeating pattern of the following 3 word
1296 * assembly code snippets:
1297 *
1298 * hwiX: ldr r3, hwiObjectX
1299 * ldr pc, ti_sysbios_family_arm_m3_Hwi_dispatch__I
1300 * hwiObjectX: .word 0
1301 * hwiY: ldr r3, hwiObjectY
1302 * ldr pc, ti_sysbios_family_arm_m3_Hwi_dispatch__I
1303 * hwiObjectY: .word 0
1304 * ...
1305 *
1306 * Each dispatched interrupt vector is then initialized to point
1307 * to one of these tuples, and the address of the corresponding Hwi
1308 * object is written into the hwiObjectX field.
1309 *
1310 * The low level assembly code in Hwi_dispatch__I preserves the
1311 * value of r3 when it calls Hwi_dispatchC(), which results in
1312 * the Hwi object being passed as the arg3.
1313 *
1314 * Depending on the boolean value of Hwi_numSparseInterrupts, the
1315 * dispatcher either uses the value passed in arg3 as the
1316 * Hwi object, or uses intNum to index into the standard
1317 * dispatchTable to fetch the Hwi object.
1318 */
1319 config UInt numSparseInterrupts = 0;
1320
1321 1322 1323 1324
1325 metaonly config Bool isTiva = false;
1326
1327 1328 1329 1330 1331 1332 1333 1334 1335
1336 metaonly config Bool enableWA1_1 = false;
1337
1338 1339 1340 1341 1342 1343
1344 config UInt (*swiDisable)();
1345 config Void (*swiRestore)(UInt);
1346 config Void (*swiRestoreHwi)(UInt);
1347 config UInt (*taskDisable)();
1348 config Void (*taskRestoreHwi)(UInt);
1349
1350
1351 config UInt32 ccr;
1352
1353 /*!
1354 * const array to hold all HookSet objects.
1355 */
1356 config HookSet hooks[length] = [];
1357
1358 1359 1360 1361
1362 Int postInit(Object *hwi, Error.Block *eb);
1363
1364 /*!
1365 * ======== updateNvic ========
1366 * Internal SMP function to cause the virtual NVIC to be flushed to the
1367 * actual NVIC.
1368 *
1369 * This function is called by the various user APIs that manipulate
1370 * individual NVIC register bits
1371 * (ie Hwi_enable/disable/restore/clearInterrupt())
1372 *
1373 * If the current core is the owner of "intNum", flushVnvic() is called
1374 * immediately.
1375 *
1376 * Otherwise an intercore interrupt is generated to force the other core
1377 * to perform the flushVnvic().
1378 *
1379 */
1380 Void updateNvic(UInt intNum);
1381
1382 /*!
1383 * ======== excHandlerAsm ========
1384 * asm code exception handler
1385 */
1386 Void excHandlerAsm();
1387
1388 /*!
1389 * ======== excHandler ========
1390 * exception Handler routes to
1391 * either min, max, or spin exception handler
1392 */
1393 Void excHandler(UInt *excStack, UInt lr);
1394
1395 /*!
1396 * ======== excHandlerMin ========
1397 * Minimal Exception Handler
1398 */
1399 Void excHandlerMin(UInt *excStack, UInt lr);
1400
1401 /*!
1402 * ======== excHandlerMax ========
1403 * Full Featured Exception Handler
1404 */
1405 Void excHandlerMax(UInt *excStack, UInt lr);
1406
1407 /*!
1408 * ======== excFillContext ========
1409 */
1410 Void excFillContext(UInt *excStack);
1411
1412 /*!
1413 * ======== excNmi ========
1414 */
1415 Void excNmi(UInt *excStack);
1416
1417 /*!
1418 * ======== excHardFault ========
1419 */
1420 Void excHardFault(UInt *excStack);
1421
1422 /*!
1423 * ======== excMemFault ========
1424 */
1425 Void excMemFault(UInt *excStack);
1426
1427 /*!
1428 * ======== excBusFault ========
1429 */
1430 Void excBusFault(UInt *excStack);
1431
1432 /*!
1433 * ======== excUsageFault ========
1434 */
1435 Void excUsageFault(UInt *excStack);
1436
1437 /*!
1438 * ======== excSvCall ========
1439 */
1440 Void excSvCall(UInt *excStack);
1441
1442 /*!
1443 * ======== excDebugMon ========
1444 */
1445 Void excDebugMon(UInt *excStack);
1446
1447 /*!
1448 * ======== excReserved ========
1449 */
1450 Void excReserved(UInt *excStack, UInt excNum);
1451
1452 /*!
1453 * ======== excNoIsr ========
1454 */
1455 Void excNoIsr(UInt *excStack, UInt excNum);
1456
1457 /*!
1458 * ======== excDumpRegs ========
1459 */
1460 Void excDumpRegs(UInt lr);
1461
1462 /*!
1463 * ======== pendSV ========
1464 * Used by dispatcher
1465 */
1466 Void pendSV();
1467
1468 1469 1470
1471 Void setStackLimit(Ptr stackBase);
1472
1473 1474 1475 1476
1477 UInt swiDisableNull();
1478
1479 1480 1481 1482
1483 Void swiRestoreNull(UInt key);
1484
1485 /*! Hwi vector function type definition. */
1486 typedef Void (*HandlerFuncPtr)(Handle, UInt);
1487
1488
1489 Void dispatch();
1490
1491 1492 1493 1494 1495 1496
1497 Void romInitNVIC();
1498
1499 1500 1501 1502
1503 UInt dispatchC(Irp irp, UInt32 dummy1, UInt32 dummy2, Object *hwi);
1504
1505
1506 Void doSwiRestore(UInt tskKey);
1507
1508
1509 Void doTaskRestore(UInt tskKey);
1510
1511 /*! Meta World Only Hwi Configuration Object. */
1512 metaonly struct InterruptObj {
1513 String name;
1514 Bool used;
1515 Bool useDispatcher;
1516 UInt priority;
1517 FuncPtr fxn;
1518 Handle hwi;
1519 };
1520
1521 /*!
1522 * Meta-only array of interrupt objects.
1523 * This meta-only array of Hwi config objects is initialized
1524 * in Hwi.xs:module$meta$init().
1525 */
1526 metaonly config InterruptObj interrupt[];
1527
1528 struct Instance_State {
1529 UArg arg;
1530 FuncPtr fxn;
1531 Irp irp;
1532
1533 UInt8 priority;
1534 Int16 intNum;
1535
1536
1537 Ptr hookEnv[];
1538 };
1539
1540 struct Module_State {
1541 Char *taskSP;
1542
1543 Bool excActive[];
1544 ExcContext *excContext[];
1545 Ptr excStack[];
1546 Ptr isrStack;
1547 Ptr isrStackBase;
1548 Ptr isrStackSize;
1549 Ptr vectorTableBase;
1550 UInt swiTaskKeys;
1551 Ptr dispatchTable;
1552 volatile Bool vnvicFlushRequired;
1553
1554 UInt8 intAffinity[];
1555 UInt32 intAffinityMasks[][];
1556 VectorFuncPtr vectorTable[];
1557 };
1558 }