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32 33 34
35
36 /*!
37 * ======== Core ========
38 * ICore implementation for default BIOS CoreDelegate
39 */
40 module Core inherits ti.sysbios.interfaces.ICore
41 {
42 /*!
43 * ======== id ========
44 * Non SMP Core ID, default is Core 0
45 *
46 * Used for making static decisions based on Core ID
47 */
48 config UInt id = 0;
49
50 /*!
51 * @_nodoc
52 * ======== baseClusterId ========
53 */
54 config UInt baseClusterId = 0;
55
56 override config UInt numCores = 1;
57
58 /*!
59 * ======== bootMaster ========
60 * Boolean flag indicating whether this core is boot master
61 *
62 * If a core is marked as a boot master then, it will initialize
63 * shared global peripherals like the GIC distributor. This
64 * config param should be set to false for secondary cores
65 * running in an AMP system.
66 */
67 metaonly config Bool bootMaster = true;
68
69 /*!
70 * ======== setL2DataRamLatency ========
71 * Value to set in L2CTRL[2:0] for Data RAM latency
72 *
73 * Faster CPUs need higher cycle latency for Data RAM accesses.
74 * For A72 CPUs running at 2 GHz, a value of 0x2 (3 cycles) is needed.
75 * If the A72 CPU is running slower than 2 GHz, you can set a lower
76 * value for fewer cycles of latency, but take care to ensure that this
77 * lower latency is sufficient for stable Data RAM values.
78 *
79 * This can be set to -1 to prevent any programming of L2CTRL[2:0] at all.
80 */
81 metaonly config Int setL2DataRamLatency = 0x2;
82
83 /*!
84 * ======== getClusterId ========
85 * Returns the core's cluster Id
86 */
87 UInt getClusterId();
88
89 /*!
90 * @_nodoc
91 * ======== getRevisionNumber ========
92 * Returns the major and minor revision number for the Cortex-A
93 * processor as a 2-nibble quantity [Major revision: Minor revision]
94 *
95 * This API is used internally by different modules to check
96 * the ARM IP revision number and determine whether or not an
97 * errata applies and requires a workaround.
98 */
99 UInt8 getRevisionNumber();
100
101 internal:
102
103 104 105 106
107 Void reset();
108
109 110 111
112 Void disableCaches();
113
114 115 116 117
118 Ptr getGicrBaseAddr(Ptr gicRedistributorBaseAddress);
119 }