65 #define UDMA_INST_ID_MAIN_0 (UDMA_INST_ID_0) 67 #define UDMA_INST_ID_MCU_0 (UDMA_INST_ID_1) 69 #define UDMA_INST_ID_START (UDMA_INST_ID_0) 71 #define UDMA_INST_ID_MAX (UDMA_INST_ID_1) 73 #define UDMA_NUM_INST_ID (UDMA_INST_ID_MAX - UDMA_INST_ID_START + 1U) 85 #define UDMA_SOC_CFG_UDMAP_PRESENT (1U) 88 #define UDMA_SOC_CFG_LCDMA_PRESENT (0U) 91 #define UDMA_SOC_CFG_PROXY_PRESENT (1U) 94 #define UDMA_SOC_CFG_CLEC_PRESENT (1U) 97 #define UDMA_SOC_CFG_RA_NORMAL_PRESENT (1U) 100 #define UDMA_SOC_CFG_RA_LCDMA_PRESENT (0U) 103 #define UDMA_SOC_CFG_RING_MON_PRESENT (1U) 106 #define UDMA_SOC_CFG_APPLY_RING_WORKAROUND (1U) 118 #define UDMA_TX_UHC_CHANS_FDEPTH (CSL_NAVSS_UDMAP_TX_UHC_CHANS_FDEPTH) 120 #define UDMA_TX_HC_CHANS_FDEPTH (CSL_NAVSS_UDMAP_TX_HC_CHANS_FDEPTH) 122 #define UDMA_TX_CHANS_FDEPTH (CSL_NAVSS_UDMAP_TX_CHANS_FDEPTH) 134 #define UDMA_RINGACC_ASEL_ENDPOINT_PHYSADDR (0U) 139 #define UDMA_RING_MODE_INVALID (CSL_RINGACC_RING_MODE_INVALID) 142 #define UDMA_NUM_MAPPED_TX_GROUP (0U) 155 #define UDMA_NUM_MAPPED_RX_GROUP (0U) 168 #define UDMA_NUM_UTC_INSTANCE (CSL_NAVSS_UTC_CNT) 178 #define UDMA_UTC_ID_MSMC_DRU0 (UDMA_UTC_ID0) 182 #define UDMA_UTC_START_CH_DRU0 (0U) 184 #define UDMA_UTC_NUM_CH_DRU0 (CSL_PSILCFG_NAVSS_MAIN_MSMC0_PSILS_THREAD_CNT) 186 #define UDMA_UTC_START_THREAD_ID_DRU0 (CSL_PSILCFG_NAVSS_MAIN_MSMC0_PSILD_THREAD_OFFSET) 188 #define UDMA_UTC_BASE_DRU0 (CSL_COMPUTE_CLUSTER0_DRU_BASE) 203 #define UDMA_CORE_ID_MPU1_0 (0U) 204 #define UDMA_NUM_MAIN_CORE (1U) 206 #define UDMA_CORE_ID_MCU1_0 (UDMA_NUM_MAIN_CORE + 0U) 207 #define UDMA_CORE_ID_MCU1_1 (UDMA_NUM_MAIN_CORE + 1U) 208 #define UDMA_NUM_MCU_CORE (2U) 210 #define UDMA_NUM_CORE (UDMA_NUM_MAIN_CORE + UDMA_NUM_MCU_CORE) 223 #define UDMA_DRU_CORE_ID_MPU1_0 (CSL_DRU_CORE_ID_0) 224 #define UDMA_DRU_CORE_ID_MCU1_0 (CSL_DRU_CORE_ID_1) 225 #define UDMA_DRU_CORE_ID_MCU1_1 (CSL_DRU_CORE_ID_2) 237 #define UDMA_RM_RES_ID_TX_UHC (0U) 239 #define UDMA_RM_RES_ID_TX_HC (1U) 241 #define UDMA_RM_RES_ID_TX (2U) 243 #define UDMA_RM_RES_ID_RX_UHC (3U) 245 #define UDMA_RM_RES_ID_RX_HC (4U) 247 #define UDMA_RM_RES_ID_RX (5U) 249 #define UDMA_RM_RES_ID_UTC (6U) 251 #define UDMA_RM_RES_ID_RX_FLOW (7U) 253 #define UDMA_RM_RES_ID_RING (8U) 255 #define UDMA_RM_RES_ID_GLOBAL_EVENT (9U) 257 #define UDMA_RM_RES_ID_VINTR (10U) 259 #define UDMA_RM_RES_ID_IR_INTR (11U) 261 #define UDMA_RM_RES_ID_PROXY (12U) 263 #define UDMA_RM_RES_ID_RING_MON (13U) 265 #define UDMA_RM_NUM_RES (14U) 270 #define UDMA_RM_NUM_SHARED_RES (3U) 273 #define UDMA_RM_SHARED_RES_MAX_INST (UDMA_NUM_CORE) 292 #define UDMA_PSIL_CH_MAIN_SAUL0_TX (CSL_PSILCFG_NAVSS_MAIN_SAUL0_PSILD_THREAD_OFFSET) 293 #define UDMA_PSIL_CH_MAIN_ICSS_G0_TX (CSL_PSILCFG_NAVSS_MAIN_ICSS_G0_PSILD_THREAD_OFFSET) 294 #define UDMA_PSIL_CH_MAIN_ICSS_G1_TX (CSL_PSILCFG_NAVSS_MAIN_ICSS_G1_PSILD_THREAD_OFFSET) 295 #define UDMA_PSIL_CH_MAIN_ICSS_G2_TX (CSL_PSILCFG_NAVSS_MAIN_ICSS_G2_PSILD_THREAD_OFFSET) 296 #define UDMA_PSIL_CH_MAIN_CAL0_TX (CSL_PSILCFG_NAVSS_MAIN_CAL0_PSILD_THREAD_OFFSET) 298 #define UDMA_PSIL_CH_MAIN_SAUL0_RX (CSL_PSILCFG_NAVSS_MAIN_SAUL0_PSILS_THREAD_OFFSET) 299 #define UDMA_PSIL_CH_MAIN_ICSS_G0_RX (CSL_PSILCFG_NAVSS_MAIN_ICSS_G0_PSILS_THREAD_OFFSET) 300 #define UDMA_PSIL_CH_MAIN_ICSS_G1_RX (CSL_PSILCFG_NAVSS_MAIN_ICSS_G1_PSILS_THREAD_OFFSET) 301 #define UDMA_PSIL_CH_MAIN_ICSS_G2_RX (CSL_PSILCFG_NAVSS_MAIN_ICSS_G2_PSILS_THREAD_OFFSET) 302 #define UDMA_PSIL_CH_MAIN_CAL0_RX (CSL_PSILCFG_NAVSS_MAIN_CAL0_PSILS_THREAD_OFFSET) 304 #define UDMA_PSIL_CH_MAIN_SAUL0_TX_CNT (CSL_PSILCFG_NAVSS_MAIN_SAUL0_PSILD_THREAD_CNT) 305 #define UDMA_PSIL_CH_MAIN_ICSS_G0_TX_CNT (CSL_PSILCFG_NAVSS_MAIN_ICSS_G0_PSILD_THREAD_CNT) 306 #define UDMA_PSIL_CH_MAIN_ICSS_G1_TX_CNT (CSL_PSILCFG_NAVSS_MAIN_ICSS_G1_PSILD_THREAD_CNT) 307 #define UDMA_PSIL_CH_MAIN_ICSS_G2_TX_CNT (CSL_PSILCFG_NAVSS_MAIN_ICSS_G2_PSILD_THREAD_CNT) 308 #define UDMA_PSIL_CH_MAIN_CAL0_TX_CNT (CSL_PSILCFG_NAVSS_MAIN_CAL0_PSILD_THREAD_CNT) 310 #define UDMA_PSIL_CH_MAIN_SAUL0_RX_CNT (CSL_PSILCFG_NAVSS_MAIN_SAUL0_PSILS_THREAD_CNT) 311 #define UDMA_PSIL_CH_MAIN_ICSS_G0_RX_CNT (CSL_PSILCFG_NAVSS_MAIN_ICSS_G0_PSILS_THREAD_CNT) 312 #define UDMA_PSIL_CH_MAIN_ICSS_G1_RX_CNT (CSL_PSILCFG_NAVSS_MAIN_ICSS_G1_PSILS_THREAD_CNT) 313 #define UDMA_PSIL_CH_MAIN_ICSS_G2_RX_CNT (CSL_PSILCFG_NAVSS_MAIN_ICSS_G2_PSILS_THREAD_CNT) 314 #define UDMA_PSIL_CH_MAIN_CAL0_RX_CNT (CSL_PSILCFG_NAVSS_MAIN_CAL0_PSILS_THREAD_CNT) 325 #define UDMA_PSIL_CH_MCU_CPSW0_TX (CSL_PSILCFG_NAVSS_MCU_CPSW0_PSILD_THREAD_OFFSET) 326 #define UDMA_PSIL_CH_MCU_CPSW0_RX (CSL_PSILCFG_NAVSS_MCU_CPSW0_PSILS_THREAD_OFFSET) 328 #define UDMA_PSIL_CH_MCU_CPSW0_TX_CNT (CSL_PSILCFG_NAVSS_MCU_CPSW0_PSILD_THREAD_CNT) 329 #define UDMA_PSIL_CH_MCU_CPSW0_RX_CNT (CSL_PSILCFG_NAVSS_MCU_CPSW0_PSILS_THREAD_CNT) 354 #define UDMA_PDMA_CH_MAIN_MCASP0_TX (CSL_PDMA_CH_MAIN_MCASP0_CH0_TX) 355 #define UDMA_PDMA_CH_MAIN_MCASP1_TX (CSL_PDMA_CH_MAIN_MCASP1_CH0_TX) 356 #define UDMA_PDMA_CH_MAIN_MCASP2_TX (CSL_PDMA_CH_MAIN_MCASP2_CH0_TX) 360 #define UDMA_PDMA_CH_MAIN_MCSPI0_CH0_TX (CSL_PDMA_CH_MAIN_MCSPI0_CH0_TX) 361 #define UDMA_PDMA_CH_MAIN_MCSPI0_CH1_TX (CSL_PDMA_CH_MAIN_MCSPI0_CH1_TX) 362 #define UDMA_PDMA_CH_MAIN_MCSPI0_CH2_TX (CSL_PDMA_CH_MAIN_MCSPI0_CH2_TX) 363 #define UDMA_PDMA_CH_MAIN_MCSPI0_CH3_TX (CSL_PDMA_CH_MAIN_MCSPI0_CH3_TX) 364 #define UDMA_PDMA_CH_MAIN_MCSPI1_CH0_TX (CSL_PDMA_CH_MAIN_MCSPI1_CH0_TX) 365 #define UDMA_PDMA_CH_MAIN_MCSPI1_CH1_TX (CSL_PDMA_CH_MAIN_MCSPI1_CH1_TX) 366 #define UDMA_PDMA_CH_MAIN_MCSPI1_CH2_TX (CSL_PDMA_CH_MAIN_MCSPI1_CH2_TX) 367 #define UDMA_PDMA_CH_MAIN_MCSPI1_CH3_TX (CSL_PDMA_CH_MAIN_MCSPI1_CH3_TX) 368 #define UDMA_PDMA_CH_MAIN_MCSPI2_CH0_TX (CSL_PDMA_CH_MAIN_MCSPI2_CH0_TX) 369 #define UDMA_PDMA_CH_MAIN_MCSPI2_CH1_TX (CSL_PDMA_CH_MAIN_MCSPI2_CH1_TX) 370 #define UDMA_PDMA_CH_MAIN_MCSPI2_CH2_TX (CSL_PDMA_CH_MAIN_MCSPI2_CH2_TX) 371 #define UDMA_PDMA_CH_MAIN_MCSPI2_CH3_TX (CSL_PDMA_CH_MAIN_MCSPI2_CH3_TX) 372 #define UDMA_PDMA_CH_MAIN_MCSPI3_CH0_TX (CSL_PDMA_CH_MAIN_MCSPI3_CH0_TX) 373 #define UDMA_PDMA_CH_MAIN_MCSPI3_CH1_TX (CSL_PDMA_CH_MAIN_MCSPI3_CH1_TX) 374 #define UDMA_PDMA_CH_MAIN_MCSPI3_CH2_TX (CSL_PDMA_CH_MAIN_MCSPI3_CH2_TX) 375 #define UDMA_PDMA_CH_MAIN_MCSPI3_CH3_TX (CSL_PDMA_CH_MAIN_MCSPI3_CH3_TX) 376 #define UDMA_PDMA_CH_MAIN_MCSPI4_CH0_TX (CSL_PDMA_CH_MAIN_MCSPI4_CH0_TX) 377 #define UDMA_PDMA_CH_MAIN_MCSPI4_CH1_TX (CSL_PDMA_CH_MAIN_MCSPI4_CH1_TX) 378 #define UDMA_PDMA_CH_MAIN_MCSPI4_CH2_TX (CSL_PDMA_CH_MAIN_MCSPI4_CH2_TX) 379 #define UDMA_PDMA_CH_MAIN_MCSPI4_CH3_TX (CSL_PDMA_CH_MAIN_MCSPI4_CH3_TX) 383 #define UDMA_PDMA_CH_MAIN_UART0_TX (CSL_PDMA_CH_MAIN_UART0_CH0_TX) 384 #define UDMA_PDMA_CH_MAIN_UART1_TX (CSL_PDMA_CH_MAIN_UART1_CH0_TX) 385 #define UDMA_PDMA_CH_MAIN_UART2_TX (CSL_PDMA_CH_MAIN_UART2_CH0_TX) 399 #define UDMA_PDMA_CH_MCU_MCSPI0_CH0_TX (CSL_PDMA_CH_MCU_MCSPI0_CH0_TX) 400 #define UDMA_PDMA_CH_MCU_MCSPI0_CH1_TX (CSL_PDMA_CH_MCU_MCSPI0_CH1_TX) 401 #define UDMA_PDMA_CH_MCU_MCSPI0_CH2_TX (CSL_PDMA_CH_MCU_MCSPI0_CH2_TX) 402 #define UDMA_PDMA_CH_MCU_MCSPI0_CH3_TX (CSL_PDMA_CH_MCU_MCSPI0_CH3_TX) 403 #define UDMA_PDMA_CH_MCU_MCSPI1_CH0_TX (CSL_PDMA_CH_MCU_MCSPI1_CH0_TX) 404 #define UDMA_PDMA_CH_MCU_MCSPI1_CH1_TX (CSL_PDMA_CH_MCU_MCSPI1_CH1_TX) 405 #define UDMA_PDMA_CH_MCU_MCSPI1_CH2_TX (CSL_PDMA_CH_MCU_MCSPI1_CH2_TX) 406 #define UDMA_PDMA_CH_MCU_MCSPI1_CH3_TX (CSL_PDMA_CH_MCU_MCSPI1_CH3_TX) 407 #define UDMA_PDMA_CH_MCU_MCSPI2_CH0_TX (CSL_PDMA_CH_MCU_MCSPI2_CH0_TX) 408 #define UDMA_PDMA_CH_MCU_MCSPI2_CH1_TX (CSL_PDMA_CH_MCU_MCSPI2_CH1_TX) 409 #define UDMA_PDMA_CH_MCU_MCSPI2_CH2_TX (CSL_PDMA_CH_MCU_MCSPI2_CH2_TX) 410 #define UDMA_PDMA_CH_MCU_MCSPI2_CH3_TX (CSL_PDMA_CH_MCU_MCSPI2_CH3_TX) 414 #define UDMA_PDMA_CH_MCU_MCAN0_CH0_TX (CSL_PDMA_CH_MCU_MCAN0_CH0_TX) 415 #define UDMA_PDMA_CH_MCU_MCAN0_CH1_TX (CSL_PDMA_CH_MCU_MCAN0_CH1_TX) 416 #define UDMA_PDMA_CH_MCU_MCAN0_CH2_TX (CSL_PDMA_CH_MCU_MCAN0_CH2_TX) 417 #define UDMA_PDMA_CH_MCU_MCAN1_CH0_TX (CSL_PDMA_CH_MCU_MCAN1_CH0_TX) 418 #define UDMA_PDMA_CH_MCU_MCAN1_CH1_TX (CSL_PDMA_CH_MCU_MCAN1_CH1_TX) 419 #define UDMA_PDMA_CH_MCU_MCAN1_CH2_TX (CSL_PDMA_CH_MCU_MCAN1_CH2_TX) 423 #define UDMA_PDMA_CH_MCU_UART0_TX (CSL_PDMA_CH_MCU_UART0_CH0_TX) 437 #define UDMA_PDMA_CH_MAIN_MCASP0_RX (CSL_PDMA_CH_MAIN_MCASP0_CH0_RX) 438 #define UDMA_PDMA_CH_MAIN_MCASP1_RX (CSL_PDMA_CH_MAIN_MCASP1_CH0_RX) 439 #define UDMA_PDMA_CH_MAIN_MCASP2_RX (CSL_PDMA_CH_MAIN_MCASP2_CH0_RX) 443 #define UDMA_PDMA_CH_MAIN_MCSPI0_CH0_RX (CSL_PDMA_CH_MAIN_MCSPI0_CH0_RX) 444 #define UDMA_PDMA_CH_MAIN_MCSPI0_CH1_RX (CSL_PDMA_CH_MAIN_MCSPI0_CH1_RX) 445 #define UDMA_PDMA_CH_MAIN_MCSPI0_CH2_RX (CSL_PDMA_CH_MAIN_MCSPI0_CH2_RX) 446 #define UDMA_PDMA_CH_MAIN_MCSPI0_CH3_RX (CSL_PDMA_CH_MAIN_MCSPI0_CH3_RX) 447 #define UDMA_PDMA_CH_MAIN_MCSPI1_CH0_RX (CSL_PDMA_CH_MAIN_MCSPI1_CH0_RX) 448 #define UDMA_PDMA_CH_MAIN_MCSPI1_CH1_RX (CSL_PDMA_CH_MAIN_MCSPI1_CH1_RX) 449 #define UDMA_PDMA_CH_MAIN_MCSPI1_CH2_RX (CSL_PDMA_CH_MAIN_MCSPI1_CH2_RX) 450 #define UDMA_PDMA_CH_MAIN_MCSPI1_CH3_RX (CSL_PDMA_CH_MAIN_MCSPI1_CH3_RX) 451 #define UDMA_PDMA_CH_MAIN_MCSPI2_CH0_RX (CSL_PDMA_CH_MAIN_MCSPI2_CH0_RX) 452 #define UDMA_PDMA_CH_MAIN_MCSPI2_CH1_RX (CSL_PDMA_CH_MAIN_MCSPI2_CH1_RX) 453 #define UDMA_PDMA_CH_MAIN_MCSPI2_CH2_RX (CSL_PDMA_CH_MAIN_MCSPI2_CH2_RX) 454 #define UDMA_PDMA_CH_MAIN_MCSPI2_CH3_RX (CSL_PDMA_CH_MAIN_MCSPI2_CH3_RX) 455 #define UDMA_PDMA_CH_MAIN_MCSPI3_CH0_RX (CSL_PDMA_CH_MAIN_MCSPI3_CH0_RX) 456 #define UDMA_PDMA_CH_MAIN_MCSPI3_CH1_RX (CSL_PDMA_CH_MAIN_MCSPI3_CH1_RX) 457 #define UDMA_PDMA_CH_MAIN_MCSPI3_CH2_RX (CSL_PDMA_CH_MAIN_MCSPI3_CH2_RX) 458 #define UDMA_PDMA_CH_MAIN_MCSPI3_CH3_RX (CSL_PDMA_CH_MAIN_MCSPI3_CH3_RX) 459 #define UDMA_PDMA_CH_MAIN_MCSPI4_CH0_RX (CSL_PDMA_CH_MAIN_MCSPI4_CH0_RX) 460 #define UDMA_PDMA_CH_MAIN_MCSPI4_CH1_RX (CSL_PDMA_CH_MAIN_MCSPI4_CH1_RX) 461 #define UDMA_PDMA_CH_MAIN_MCSPI4_CH2_RX (CSL_PDMA_CH_MAIN_MCSPI4_CH2_RX) 462 #define UDMA_PDMA_CH_MAIN_MCSPI4_CH3_RX (CSL_PDMA_CH_MAIN_MCSPI4_CH3_RX) 466 #define UDMA_PDMA_CH_MAIN_UART0_RX (CSL_PDMA_CH_MAIN_UART0_CH0_RX) 467 #define UDMA_PDMA_CH_MAIN_UART1_RX (CSL_PDMA_CH_MAIN_UART1_CH0_RX) 468 #define UDMA_PDMA_CH_MAIN_UART2_RX (CSL_PDMA_CH_MAIN_UART2_CH0_RX) 482 #define UDMA_PDMA_CH_MCU_ADC0_CH0_RX (CSL_PDMA_CH_MCU_ADC0_CH0_RX) 483 #define UDMA_PDMA_CH_MCU_ADC0_CH1_RX (CSL_PDMA_CH_MCU_ADC0_CH1_RX) 484 #define UDMA_PDMA_CH_MCU_ADC1_CH0_RX (CSL_PDMA_CH_MCU_ADC1_CH0_RX) 485 #define UDMA_PDMA_CH_MCU_ADC1_CH1_RX (CSL_PDMA_CH_MCU_ADC1_CH1_RX) 489 #define UDMA_PDMA_CH_MCU_MCSPI0_CH0_RX (CSL_PDMA_CH_MCU_MCSPI0_CH0_RX) 490 #define UDMA_PDMA_CH_MCU_MCSPI0_CH1_RX (CSL_PDMA_CH_MCU_MCSPI0_CH1_RX) 491 #define UDMA_PDMA_CH_MCU_MCSPI0_CH2_RX (CSL_PDMA_CH_MCU_MCSPI0_CH2_RX) 492 #define UDMA_PDMA_CH_MCU_MCSPI0_CH3_RX (CSL_PDMA_CH_MCU_MCSPI0_CH3_RX) 493 #define UDMA_PDMA_CH_MCU_MCSPI1_CH0_RX (CSL_PDMA_CH_MCU_MCSPI1_CH0_RX) 494 #define UDMA_PDMA_CH_MCU_MCSPI1_CH1_RX (CSL_PDMA_CH_MCU_MCSPI1_CH1_RX) 495 #define UDMA_PDMA_CH_MCU_MCSPI1_CH2_RX (CSL_PDMA_CH_MCU_MCSPI1_CH2_RX) 496 #define UDMA_PDMA_CH_MCU_MCSPI1_CH3_RX (CSL_PDMA_CH_MCU_MCSPI1_CH3_RX) 497 #define UDMA_PDMA_CH_MCU_MCSPI2_CH0_RX (CSL_PDMA_CH_MCU_MCSPI2_CH0_RX) 498 #define UDMA_PDMA_CH_MCU_MCSPI2_CH1_RX (CSL_PDMA_CH_MCU_MCSPI2_CH1_RX) 499 #define UDMA_PDMA_CH_MCU_MCSPI2_CH2_RX (CSL_PDMA_CH_MCU_MCSPI2_CH2_RX) 500 #define UDMA_PDMA_CH_MCU_MCSPI2_CH3_RX (CSL_PDMA_CH_MCU_MCSPI2_CH3_RX) 504 #define UDMA_PDMA_CH_MCU_MCAN0_CH0_RX (CSL_PDMA_CH_MCU_MCAN0_CH0_RX) 505 #define UDMA_PDMA_CH_MCU_MCAN0_CH1_RX (CSL_PDMA_CH_MCU_MCAN0_CH1_RX) 506 #define UDMA_PDMA_CH_MCU_MCAN0_CH2_RX (CSL_PDMA_CH_MCU_MCAN0_CH2_RX) 507 #define UDMA_PDMA_CH_MCU_MCAN1_CH0_RX (CSL_PDMA_CH_MCU_MCAN1_CH0_RX) 508 #define UDMA_PDMA_CH_MCU_MCAN1_CH1_RX (CSL_PDMA_CH_MCU_MCAN1_CH1_RX) 509 #define UDMA_PDMA_CH_MCU_MCAN1_CH2_RX (CSL_PDMA_CH_MCU_MCAN1_CH2_RX) 513 #define UDMA_PDMA_CH_MCU_UART0_RX (CSL_PDMA_CH_MCU_UART0_CH0_RX) uint32_t Udma_isCacheCoherent(void)
Returns TRUE if the memory is cache coherent.
uint32_t Udma_getCoreId(void)
Returns the core ID.
uint16_t Udma_getCoreSciDevId(void)
Returns the core tisci device ID.