C6x Register Usage

C28x DSP/BIOS Register Usage

This document provides tables describing the TMS320C28000TM register conventions in terms of preservation across multi-threaded context switching and preconditions.

Overview

In a multi-threaded application using DSP/BIOS, it is necessary to know which registers can or cannot be modified. Furthermore, users need to understand which registers need to be saved/restored across a function call or an interrupt.

The following definitions describe the various possible register handling behaviors:

  • Scratch register. These registers are saved/restored by the Hwi dispatcher with temporary register bit masks.
  • Preserved register. These registers are saved/restored during a Task context switch.
  • Initialized register. These registers are set to a particular value during Hwi processing and restored to their incoming value upon exiting from the interrupt routine.
  • Read-Only register. These registers may be read but must not be modified.
  • Global register. These registers are shared across all threads in the system. To make a temporary change, save the register, make the change, and then restore it.
  • Other. These registers do not fit into one of the categories above.

Register Conventions

Table 1 Register and Status Bit Handling

 

 

Register

Status Bit

Register or Status Bit Name

Type

Notes

ACC (AL, AH)

 

Accumulator

Scratch

Hardware saves during ISR

XAR0 (AR0, AR0H)

 

Auxiliary register 0

Scratch

Hardware saves AR0 during ISR

XAR1 (AR1, AR1H)

 

Auxiliary register 1

Preserved Hardware saves AR1 during ISR

 

XAR2 (AR2, AR2H)

 

Auxiliary register 2

Preserved

 

XAR3 (AR3, AR3H)

 

Auxiliary register 3

Preserved

 

XAR4 (AR4, AR4H)

 

Auxiliary register 4

Scratch

 

XAR5 (AR5, AR5H)

 

Auxiliary register 5

Scratch

 

XAR6 (AR6, AR6H)

 

Auxiliary register 6

Scratch

 

XAR7 (AR7, AR7H)

 

Auxiliary register 7

Scratch

 

DP

 

Data-page pointer

Don't care

Hardware saves during ISR, DSP/BIOS not used

IFR

 

Interrupt flag register

Don't care

DSP/BIOS not used

IER

 

Interrupt enable register

Don't care

Hardware saves during ISR

DBGIER

 

Debug interrupt enable register

Don't care

 

DBGSTAT

 

Debug status register

Read-Only

Hardware saves during ISR

P (PL, PH)

 

Product register

Scratch

Hardware saves during ISR

RPC

 

Return program counter

Preserved

SP Stack pointer Initialized HWI sets to HWI stack before calling ISR

ST0

 

Status register 0

Scratch

Hardware saves during ISR

 

OVC/OVCU

Overflow counter

Don't care

 

 

PM

Product shift mode bits

Initialized

(001 No shift)

 

V

Overflow flag

Don't care

 

 

N

Negative flag

Don't care

 

 

Z

Zero flag

Don't care

 

 

C

Carry bit

Don't care

 

 

TC

Test/control flag

Don't care

 

 

OVM

Overflow mode bit

Initialized

(0: Normal)

 

SXM

Sign-extension mode bit

Don't care

 

ST1

 

Status register 1

Scratch

Hardware saves during ISR

 

ARP

Auxiliary register pointer

Don't care

 

 

XF

XF status bit

Other

Do not use with DSP/BIOS. Use GPIO instead

 

M0M1MAP

M0 and M1 mapping mode bit

Read-Only (1: 28x mode)

DSP/BIOS not support ‘C27x , DSP/BIOS initialized during boot process

 

OBJMODE

Object compatibility mode bit

Read-Only (1: 28x mode)

DSP/BIOS not support ‘C27x, DSP/BIOS initialized during boot process

 

AMODE

Address mode bit

Initialized (0: C28ADDR)

 

 

IDLESTAT

IDLE status bit

Read-Only

 

 

EALLOW

Emulation access enable bit

Don't care

 

 

LOOP

Loop instruction status bit

Don't care

 

 

SPA

Stack pointer alignment bit

Preserved

 

 

VMAP

Vector map bit

Read-Only

DSP/BIOS initialized to configured value during boot process

 

PAGE0

PAGE0 addressing mode configuration bit

Initialized

(0: Stack addressing)

 

DBGM

Debug enable mask bit

Don't care

 

 

INTM

Interrupt global mask bit

Don't care

 

XT (T, TL)

 

Multiplicand register

Scratch

Hardware saves T during ISR