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PDK API Guide for AM65xx
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File containing the AM65xx specific interrupt management data for RM.
uint8_t vint_usage_count_NAVSS0_UDMASS_INTA0[256] = {0} |
uint8_t vint_usage_count_NAVSS0_MODSS_INTA0[64] = {0} |
uint8_t vint_usage_count_NAVSS0_MODSS_INTA1[64] = {0} |
uint8_t vint_usage_count_MCU_NAVSS0_INTR_AGGR_0[256] = {0} |
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struct Sciclient_rmIaInst gRmIaInstances[SCICLIENT_RM_IA_NUM_INST] |
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struct Sciclient_rmIrInst gRmIrInstances[SCICLIENT_RM_IR_NUM_INST] |
const struct Sciclient_rmIrqIf cal_main_0_bus_int_cal_l_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_11_11 |
const struct Sciclient_rmIrqIf* const tisci_if_CAL0[] |
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const struct Sciclient_rmIrqIf cmp_event_introuter_main_0_bus_outp_0_15_to_gic500ss_main_0_bus_spi_544_559 |
const struct Sciclient_rmIrqIf cmp_event_introuter_main_0_bus_outp_24_31_to_pdma_main1_main_0_bus_levent_in_8_15 |
const struct Sciclient_rmIrqIf* const tisci_if_CMPEVENT_INTRTR0[] |
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const struct Sciclient_rmIrqIf cpsw_2guss_mcu_0_bus_cpts_comp_6_6_to_cmp_event_introuter_main_0_bus_in_7_7 |
const struct Sciclient_rmIrqIf cpsw_2guss_mcu_0_bus_cpts_genf0_3_3_to_timesync_event_introuter_main_0_bus_in_12_12 |
const struct Sciclient_rmIrqIf cpsw_2guss_mcu_0_bus_cpts_genf1_4_4_to_timesync_event_introuter_main_0_bus_in_13_13 |
const struct Sciclient_rmIrqIf cpsw_2guss_mcu_0_bus_cpts_sync_5_5_to_timesync_event_introuter_main_0_bus_in_31_31 |
const struct Sciclient_rmIrqIf* const tisci_if_MCU_CPSW0[] |
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const struct Sciclient_rmIrqIf dcc_main_0_bus_intr_done_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_120_120 |
const struct Sciclient_rmIrqIf* const tisci_if_DCC0[] |
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const struct Sciclient_rmIrqIf dcc_main_1_bus_intr_done_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_121_121 |
const struct Sciclient_rmIrqIf* const tisci_if_DCC1[] |
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const struct Sciclient_rmIrqIf dcc_main_2_bus_intr_done_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_122_122 |
const struct Sciclient_rmIrqIf* const tisci_if_DCC2[] |
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const struct Sciclient_rmIrqIf dcc_main_3_bus_intr_done_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_123_123 |
const struct Sciclient_rmIrqIf* const tisci_if_DCC3[] |
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const struct Sciclient_rmIrqIf dcc_main_4_bus_intr_done_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_124_124 |
const struct Sciclient_rmIrqIf* const tisci_if_DCC4[] |
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const struct Sciclient_rmIrqIf dcc_main_5_bus_intr_done_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_125_125 |
const struct Sciclient_rmIrqIf* const tisci_if_DCC5[] |
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const struct Sciclient_rmIrqIf dcc_main_6_bus_intr_done_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_126_126 |
const struct Sciclient_rmIrqIf* const tisci_if_DCC6[] |
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const struct Sciclient_rmIrqIf dcc_main_7_bus_intr_done_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_127_127 |
const struct Sciclient_rmIrqIf* const tisci_if_DCC7[] |
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const struct Sciclient_rmIrqIf ddr39ss_gs80_main_0_bus_ddrss_v2h_other_err_lvl_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_10_10 |
const struct Sciclient_rmIrqIf* const tisci_if_DDRSS0[] |
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const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_0_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_108_108 |
const struct Sciclient_rmIrqIf* const tisci_if_TIMER0[] |
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const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_1_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_109_109 |
const struct Sciclient_rmIrqIf* const tisci_if_TIMER1[] |
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const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_10_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_118_118 |
const struct Sciclient_rmIrqIf* const tisci_if_TIMER10[] |
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const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_11_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_119_119 |
const struct Sciclient_rmIrqIf* const tisci_if_TIMER11[] |
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const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_2_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_110_110 |
const struct Sciclient_rmIrqIf* const tisci_if_TIMER2[] |
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const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_3_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_111_111 |
const struct Sciclient_rmIrqIf* const tisci_if_TIMER3[] |
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const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_4_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_112_112 |
const struct Sciclient_rmIrqIf* const tisci_if_TIMER4[] |
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const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_5_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_113_113 |
const struct Sciclient_rmIrqIf* const tisci_if_TIMER5[] |
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const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_6_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_114_114 |
const struct Sciclient_rmIrqIf* const tisci_if_TIMER6[] |
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const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_7_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_115_115 |
const struct Sciclient_rmIrqIf* const tisci_if_TIMER7[] |
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const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_8_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_116_116 |
const struct Sciclient_rmIrqIf* const tisci_if_TIMER8[] |
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const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_9_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_117_117 |
const struct Sciclient_rmIrqIf* const tisci_if_TIMER9[] |
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const struct Sciclient_rmIrqIf ecap_main_0_bus_ecap_int_0_0_to_main2mcu_pls_introuter_main_0_bus_in_17_17 |
const struct Sciclient_rmIrqIf* const tisci_if_ECAP0[] |
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const struct Sciclient_rmIrqIf ehrpwm_main_0_bus_epwm_etint_2_2_to_main2mcu_pls_introuter_main_0_bus_in_2_2 |
const struct Sciclient_rmIrqIf ehrpwm_main_0_bus_epwm_tripzint_0_0_to_main2mcu_pls_introuter_main_0_bus_in_8_8 |
const struct Sciclient_rmIrqIf* const tisci_if_EHRPWM0[] |
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const struct Sciclient_rmIrqIf ehrpwm_main_1_bus_epwm_etint_2_2_to_main2mcu_pls_introuter_main_0_bus_in_3_3 |
const struct Sciclient_rmIrqIf ehrpwm_main_1_bus_epwm_tripzint_0_0_to_main2mcu_pls_introuter_main_0_bus_in_9_9 |
const struct Sciclient_rmIrqIf* const tisci_if_EHRPWM1[] |
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const struct Sciclient_rmIrqIf ehrpwm_main_2_bus_epwm_etint_2_2_to_main2mcu_pls_introuter_main_0_bus_in_4_4 |
const struct Sciclient_rmIrqIf ehrpwm_main_2_bus_epwm_tripzint_0_0_to_main2mcu_pls_introuter_main_0_bus_in_10_10 |
const struct Sciclient_rmIrqIf* const tisci_if_EHRPWM2[] |
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const struct Sciclient_rmIrqIf ehrpwm_main_3_bus_epwm_etint_2_2_to_main2mcu_pls_introuter_main_0_bus_in_5_5 |
const struct Sciclient_rmIrqIf ehrpwm_main_3_bus_epwm_tripzint_0_0_to_main2mcu_pls_introuter_main_0_bus_in_11_11 |
const struct Sciclient_rmIrqIf* const tisci_if_EHRPWM3[] |
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const struct Sciclient_rmIrqIf ehrpwm_main_4_bus_epwm_etint_2_2_to_main2mcu_pls_introuter_main_0_bus_in_6_6 |
const struct Sciclient_rmIrqIf ehrpwm_main_4_bus_epwm_tripzint_0_0_to_main2mcu_pls_introuter_main_0_bus_in_12_12 |
const struct Sciclient_rmIrqIf* const tisci_if_EHRPWM4[] |
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const struct Sciclient_rmIrqIf ehrpwm_main_5_bus_epwm_etint_2_2_to_main2mcu_pls_introuter_main_0_bus_in_7_7 |
const struct Sciclient_rmIrqIf ehrpwm_main_5_bus_epwm_tripzint_0_0_to_main2mcu_pls_introuter_main_0_bus_in_13_13 |
const struct Sciclient_rmIrqIf* const tisci_if_EHRPWM5[] |
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const struct Sciclient_rmIrqIf elm_main_0_bus_elm_porocpsinterrupt_lvl_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_7_7 |
const struct Sciclient_rmIrqIf* const tisci_if_ELM0[] |
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const struct Sciclient_rmIrqIf emmc2sd3ss_gs80_main_0_bus_emmcsdss_intr_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_29_29 |
const struct Sciclient_rmIrqIf* const tisci_if_MMCSD0[] |
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const struct Sciclient_rmIrqIf emmc4sd3ss_gs80_main_0_bus_emmcsdss_intr_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_28_28 |
const struct Sciclient_rmIrqIf* const tisci_if_MMCSD1[] |
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const struct Sciclient_rmIrqIf eqep_main_0_bus_eqep_int_0_0_to_main2mcu_pls_introuter_main_0_bus_in_14_14 |
const struct Sciclient_rmIrqIf* const tisci_if_EQEP0[] |
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const struct Sciclient_rmIrqIf eqep_main_1_bus_eqep_int_0_0_to_main2mcu_pls_introuter_main_0_bus_in_15_15 |
const struct Sciclient_rmIrqIf* const tisci_if_EQEP1[] |
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const struct Sciclient_rmIrqIf eqep_main_2_bus_eqep_int_0_0_to_main2mcu_pls_introuter_main_0_bus_in_16_16 |
const struct Sciclient_rmIrqIf* const tisci_if_EQEP2[] |
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const struct Sciclient_rmIrqIf gpio_144_main_0_bus_gpio_0_95_to_main_gpiomux_introuter_main_0_bus_in_0_95 |
const struct Sciclient_rmIrqIf gpio_144_main_0_bus_gpio_bank_256_261_to_main_gpiomux_introuter_main_0_bus_in_192_197 |
const struct Sciclient_rmIrqIf* const tisci_if_GPIO0[] |
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const struct Sciclient_rmIrqIf gpio_144_main_1_bus_gpio_0_89_to_main_gpiomux_introuter_main_0_bus_in_96_185 |
const struct Sciclient_rmIrqIf gpio_144_main_1_bus_gpio_bank_256_261_to_main_gpiomux_introuter_main_0_bus_in_200_205 |
const struct Sciclient_rmIrqIf* const tisci_if_GPIO1[] |
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const struct Sciclient_rmIrqIf gpio_144_wkup_0_bus_gpio_0_55_to_wkup_gpiomux_introuter_wkup_0_bus_in_0_55 |
const struct Sciclient_rmIrqIf gpio_144_wkup_0_bus_gpio_bank_128_131_to_wkup_gpiomux_introuter_wkup_0_bus_in_60_63 |
const struct Sciclient_rmIrqIf* const tisci_if_WKUP_GPIO0[] |
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const struct Sciclient_rmIrqIf gpmc_main_0_bus_gpmc_sinterrupt_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_8_8 |
const struct Sciclient_rmIrqIf* const tisci_if_GPMC0[] |
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const struct Sciclient_rmIrqIf icss_g_main_0_bus_pr1_rx_sof_intr_req_284_285_to_main2mcu_pls_introuter_main_0_bus_in_20_21 |
const struct Sciclient_rmIrqIf icss_g_main_0_bus_pr1_tx_sof_intr_req_302_303_to_main2mcu_pls_introuter_main_0_bus_in_22_23 |
const struct Sciclient_rmIrqIf icss_g_main_0_bus_pr1_host_intr_req_286_293_to_cmp_event_introuter_main_0_bus_in_8_15 |
const struct Sciclient_rmIrqIf icss_g_main_0_bus_pr1_iep0_cmp_intr_req_268_283_to_cmp_event_introuter_main_0_bus_in_32_47 |
const struct Sciclient_rmIrqIf icss_g_main_0_bus_pr1_iep1_cmp_intr_req_256_261_to_cmp_event_introuter_main_0_bus_in_48_53 |
const struct Sciclient_rmIrqIf icss_g_main_0_bus_pr1_iep1_cmp_intr_req_6_15_to_cmp_event_introuter_main_0_bus_in_54_63 |
const struct Sciclient_rmIrqIf icss_g_main_0_bus_pr1_edc0_sync0_out_304_304_to_timesync_event_introuter_main_0_bus_in_16_16 |
const struct Sciclient_rmIrqIf icss_g_main_0_bus_pr1_edc0_sync1_out_305_305_to_timesync_event_introuter_main_0_bus_in_17_17 |
const struct Sciclient_rmIrqIf icss_g_main_0_bus_pr1_edc1_sync0_out_306_306_to_timesync_event_introuter_main_0_bus_in_18_18 |
const struct Sciclient_rmIrqIf icss_g_main_0_bus_pr1_edc1_sync1_out_307_307_to_timesync_event_introuter_main_0_bus_in_19_19 |
const struct Sciclient_rmIrqIf icss_g_main_0_bus_pr1_host_intr_pend_294_301_to_main2mcu_lvl_introuter_main_0_bus_in_32_39 |
const struct Sciclient_rmIrqIf* const tisci_if_PRU_ICSSG0[] |
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const struct Sciclient_rmIrqIf icss_g_main_1_bus_pr1_rx_sof_intr_req_284_285_to_main2mcu_pls_introuter_main_0_bus_in_24_25 |
const struct Sciclient_rmIrqIf icss_g_main_1_bus_pr1_tx_sof_intr_req_302_303_to_main2mcu_pls_introuter_main_0_bus_in_26_27 |
const struct Sciclient_rmIrqIf icss_g_main_1_bus_pr1_host_intr_req_286_293_to_cmp_event_introuter_main_0_bus_in_16_23 |
const struct Sciclient_rmIrqIf icss_g_main_1_bus_pr1_iep0_cmp_intr_req_268_283_to_cmp_event_introuter_main_0_bus_in_64_79 |
const struct Sciclient_rmIrqIf icss_g_main_1_bus_pr1_iep1_cmp_intr_req_256_261_to_cmp_event_introuter_main_0_bus_in_80_85 |
const struct Sciclient_rmIrqIf icss_g_main_1_bus_pr1_iep1_cmp_intr_req_6_15_to_cmp_event_introuter_main_0_bus_in_86_95 |
const struct Sciclient_rmIrqIf icss_g_main_1_bus_pr1_edc0_sync0_out_304_304_to_timesync_event_introuter_main_0_bus_in_20_20 |
const struct Sciclient_rmIrqIf icss_g_main_1_bus_pr1_edc0_sync1_out_305_305_to_timesync_event_introuter_main_0_bus_in_21_21 |
const struct Sciclient_rmIrqIf icss_g_main_1_bus_pr1_edc1_sync0_out_306_306_to_timesync_event_introuter_main_0_bus_in_22_22 |
const struct Sciclient_rmIrqIf icss_g_main_1_bus_pr1_edc1_sync1_out_307_307_to_timesync_event_introuter_main_0_bus_in_23_23 |
const struct Sciclient_rmIrqIf icss_g_main_1_bus_pr1_host_intr_pend_294_301_to_main2mcu_lvl_introuter_main_0_bus_in_40_47 |
const struct Sciclient_rmIrqIf* const tisci_if_PRU_ICSSG1[] |
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const struct Sciclient_rmIrqIf icss_g_main_2_bus_pr1_rx_sof_intr_req_284_285_to_main2mcu_pls_introuter_main_0_bus_in_28_29 |
const struct Sciclient_rmIrqIf icss_g_main_2_bus_pr1_tx_sof_intr_req_302_303_to_main2mcu_pls_introuter_main_0_bus_in_30_31 |
const struct Sciclient_rmIrqIf icss_g_main_2_bus_pr1_host_intr_req_286_293_to_cmp_event_introuter_main_0_bus_in_24_31 |
const struct Sciclient_rmIrqIf icss_g_main_2_bus_pr1_iep0_cmp_intr_req_268_283_to_cmp_event_introuter_main_0_bus_in_96_111 |
const struct Sciclient_rmIrqIf icss_g_main_2_bus_pr1_iep1_cmp_intr_req_256_261_to_cmp_event_introuter_main_0_bus_in_112_117 |
const struct Sciclient_rmIrqIf icss_g_main_2_bus_pr1_iep1_cmp_intr_req_6_15_to_cmp_event_introuter_main_0_bus_in_118_127 |
const struct Sciclient_rmIrqIf icss_g_main_2_bus_pr1_edc0_sync0_out_304_304_to_timesync_event_introuter_main_0_bus_in_24_24 |
const struct Sciclient_rmIrqIf icss_g_main_2_bus_pr1_edc0_sync1_out_305_305_to_timesync_event_introuter_main_0_bus_in_25_25 |
const struct Sciclient_rmIrqIf icss_g_main_2_bus_pr1_edc1_sync0_out_306_306_to_timesync_event_introuter_main_0_bus_in_26_26 |
const struct Sciclient_rmIrqIf icss_g_main_2_bus_pr1_edc1_sync1_out_307_307_to_timesync_event_introuter_main_0_bus_in_27_27 |
const struct Sciclient_rmIrqIf icss_g_main_2_bus_pr1_host_intr_pend_294_301_to_main2mcu_lvl_introuter_main_0_bus_in_48_55 |
const struct Sciclient_rmIrqIf* const tisci_if_PRU_ICSSG2[] |
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const struct Sciclient_rmIrqIf k3_boltv2_main_0_bus_gpu_irq_3_3_to_main2mcu_lvl_introuter_main_0_bus_in_56_56 |
const struct Sciclient_rmIrqIf k3_boltv2_main_0_bus_exp_intr_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_57_57 |
const struct Sciclient_rmIrqIf k3_boltv2_main_0_bus_init_err_4_4_to_main2mcu_lvl_introuter_main_0_bus_in_58_58 |
const struct Sciclient_rmIrqIf k3_boltv2_main_0_bus_target_err_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_59_59 |
const struct Sciclient_rmIrqIf* const tisci_if_GPU0[] |
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const struct Sciclient_rmIrqIf k3_cc_debug_cell_main_0_bus_aqcmpintr_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_13_13 |
const struct Sciclient_rmIrqIf* const tisci_if_CCDEBUGSS0[] |
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const struct Sciclient_rmIrqIf k3_dss_ul_main_0_bus_dispc_intr_req_0_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_2_2 |
const struct Sciclient_rmIrqIf k3_dss_ul_main_0_bus_dispc_intr_req_1_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_3_3 |
const struct Sciclient_rmIrqIf* const tisci_if_DSS0[] |
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const struct Sciclient_rmIrqIf k3_main_debug_cell_main_0_bus_aqcmpintr_level_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_14_14 |
const struct Sciclient_rmIrqIf k3_main_debug_cell_main_0_bus_ctm_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_15_15 |
const struct Sciclient_rmIrqIf* const tisci_if_DEBUGSS0[] |
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const struct Sciclient_rmIrqIf m4_main_cbass_main_0_bus_LPSC_per_common_err_intr_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_172_172 |
const struct Sciclient_rmIrqIf* const tisci_if_CBASS0[] |
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const struct Sciclient_rmIrqIf m4_main_dbg_cbass_main_0_bus_LPSC_main_debug_err_intr_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_173_173 |
const struct Sciclient_rmIrqIf* const tisci_if_CBASS_DEBUG0[] |
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const struct Sciclient_rmIrqIf m4_main_fw_cbass_main_0_bus_LPSC_main_infra_err_intr_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_174_174 |
const struct Sciclient_rmIrqIf* const tisci_if_CBASS_FW0[] |
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const struct Sciclient_rmIrqIf m4_main_infra_cbass_main_0_bus_LPSC_main_infra_err_intr_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_175_175 |
const struct Sciclient_rmIrqIf* const tisci_if_CBASS_INFRA0[] |
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const struct Sciclient_rmIrqIf main2mcu_lvl_introuter_main_0_bus_outl_0_63_to_mcu_armss0_cpu0_bus_intr_160_223 |
const struct Sciclient_rmIrqIf main2mcu_lvl_introuter_main_0_bus_outl_0_63_to_mcu_armss0_cpu1_bus_intr_160_223 |
const struct Sciclient_rmIrqIf* const tisci_if_MAIN2MCU_LVL_INTRTR0[] |
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static |
const struct Sciclient_rmIrqIf main2mcu_pls_introuter_main_0_bus_outp_0_47_to_mcu_armss0_cpu1_bus_intr_224_271 |
const struct Sciclient_rmIrqIf main2mcu_pls_introuter_main_0_bus_outp_0_47_to_mcu_armss0_cpu0_bus_intr_224_271 |
const struct Sciclient_rmIrqIf* const tisci_if_MAIN2MCU_PLS_INTRTR0[] |
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const struct Sciclient_rmIrqIf main_ctrl_mmr_main_0_bus_access_err_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_6_6 |
const struct Sciclient_rmIrqIf* const tisci_if_CTRL_MMR0[] |
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static |
const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_20_25_to_icss_g_main_1_bus_pr1_iep0_cap_intr_req_262_267 |
const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_26_31_to_icss_g_main_1_bus_pr1_iep1_cap_intr_req_0_5 |
const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_24_31_to_icss_g_main_1_bus_pr1_slv_intr_88_95 |
const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_20_25_to_icss_g_main_0_bus_pr1_iep0_cap_intr_req_262_267 |
const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_26_31_to_icss_g_main_0_bus_pr1_iep1_cap_intr_req_0_5 |
const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_24_31_to_icss_g_main_0_bus_pr1_slv_intr_88_95 |
const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_0_31_to_gic500ss_main_0_bus_spi_392_423 |
const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_20_25_to_icss_g_main_2_bus_pr1_iep0_cap_intr_req_262_267 |
const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_26_31_to_icss_g_main_2_bus_pr1_iep1_cap_intr_req_0_5 |
const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_24_31_to_icss_g_main_2_bus_pr1_slv_intr_88_95 |
const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_0_7_to_esm_main_main_0_bus_esm_pls_event0_512_519 |
const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_0_7_to_esm_main_main_0_bus_esm_pls_event1_520_527 |
const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_0_7_to_esm_main_main_0_bus_esm_pls_event2_248_255 |
const struct Sciclient_rmIrqIf* const tisci_if_GPIOMUX_INTRTR0[] |
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const struct Sciclient_rmIrqIf mcasp_main_0_bus_xmit_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_16_16 |
const struct Sciclient_rmIrqIf mcasp_main_0_bus_rec_intr_pend_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_17_17 |
const struct Sciclient_rmIrqIf* const tisci_if_MCASP0[] |
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static |
const struct Sciclient_rmIrqIf mcasp_main_1_bus_xmit_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_18_18 |
const struct Sciclient_rmIrqIf mcasp_main_1_bus_rec_intr_pend_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_19_19 |
const struct Sciclient_rmIrqIf* const tisci_if_MCASP1[] |
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static |
const struct Sciclient_rmIrqIf mcasp_main_2_bus_xmit_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_20_20 |
const struct Sciclient_rmIrqIf mcasp_main_2_bus_rec_intr_pend_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_21_21 |
const struct Sciclient_rmIrqIf* const tisci_if_MCASP2[] |
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static |
const struct Sciclient_rmIrqIf mshsi2c_main_0_bus_pointrpend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_100_100 |
const struct Sciclient_rmIrqIf* const tisci_if_I2C0[] |
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static |
const struct Sciclient_rmIrqIf mshsi2c_main_1_bus_pointrpend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_101_101 |
const struct Sciclient_rmIrqIf* const tisci_if_I2C1[] |
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static |
const struct Sciclient_rmIrqIf mshsi2c_main_2_bus_pointrpend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_102_102 |
const struct Sciclient_rmIrqIf* const tisci_if_I2C2[] |
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static |
const struct Sciclient_rmIrqIf mshsi2c_main_3_bus_pointrpend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_103_103 |
const struct Sciclient_rmIrqIf* const tisci_if_I2C3[] |
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static |
const struct Sciclient_rmIrqIf navss256l_main_0_bus_cpts0_comp_9_9_to_cmp_event_introuter_main_0_bus_in_4_4 |
const struct Sciclient_rmIrqIf navss256l_main_0_bus_cpts0_genf0_10_10_to_timesync_event_introuter_main_0_bus_in_4_4 |
const struct Sciclient_rmIrqIf navss256l_main_0_bus_cpts0_genf1_11_11_to_timesync_event_introuter_main_0_bus_in_5_5 |
const struct Sciclient_rmIrqIf navss256l_main_0_bus_cpts0_genf2_12_12_to_timesync_event_introuter_main_0_bus_in_6_6 |
const struct Sciclient_rmIrqIf navss256l_main_0_bus_cpts0_genf3_13_13_to_timesync_event_introuter_main_0_bus_in_7_7 |
const struct Sciclient_rmIrqIf navss256l_main_0_bus_cpts0_genf4_14_14_to_timesync_event_introuter_main_0_bus_in_8_8 |
const struct Sciclient_rmIrqIf navss256l_main_0_bus_cpts0_genf5_15_15_to_timesync_event_introuter_main_0_bus_in_9_9 |
const struct Sciclient_rmIrqIf navss256l_main_0_bus_cpts0_sync_16_16_to_timesync_event_introuter_main_0_bus_in_30_30 |
const struct Sciclient_rmIrqIf* const tisci_if_NAVSS0[] |
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static |
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie_cpts_comp_19_19_to_cmp_event_introuter_main_0_bus_in_5_5 |
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie_cpts_genf0_20_20_to_timesync_event_introuter_main_0_bus_in_10_10 |
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie_cpts_hw1_push_17_17_to_timesync_event_introuter_main_0_bus_in_14_14 |
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie_cpts_sync_21_21_to_timesync_event_introuter_main_0_bus_in_28_28 |
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie0_pend_13_13_to_main2mcu_lvl_introuter_main_0_bus_in_64_64 |
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie1_pend_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_65_65 |
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie2_pend_7_7_to_main2mcu_lvl_introuter_main_0_bus_in_66_66 |
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie3_pend_4_4_to_main2mcu_lvl_introuter_main_0_bus_in_67_67 |
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie4_pend_5_5_to_main2mcu_lvl_introuter_main_0_bus_in_68_68 |
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie5_pend_3_3_to_main2mcu_lvl_introuter_main_0_bus_in_69_69 |
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie6_pend_11_11_to_main2mcu_lvl_introuter_main_0_bus_in_70_70 |
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie7_pend_8_8_to_main2mcu_lvl_introuter_main_0_bus_in_71_71 |
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie8_pend_9_9_to_main2mcu_lvl_introuter_main_0_bus_in_72_72 |
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie9_pend_16_16_to_main2mcu_lvl_introuter_main_0_bus_in_73_73 |
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie10_pend_15_15_to_main2mcu_lvl_introuter_main_0_bus_in_74_74 |
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie11_pend_14_14_to_main2mcu_lvl_introuter_main_0_bus_in_75_75 |
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie12_pend_6_6_to_main2mcu_lvl_introuter_main_0_bus_in_76_76 |
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie13_pend_10_10_to_main2mcu_lvl_introuter_main_0_bus_in_77_77 |
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie14_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_78_78 |
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie_cpts_pend_12_12_to_main2mcu_lvl_introuter_main_0_bus_in_79_79 |
const struct Sciclient_rmIrqIf* const tisci_if_PCIE0[] |
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static |
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie_cpts_comp_19_19_to_cmp_event_introuter_main_0_bus_in_6_6 |
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie_cpts_genf0_20_20_to_timesync_event_introuter_main_0_bus_in_11_11 |
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie_cpts_hw1_push_17_17_to_timesync_event_introuter_main_0_bus_in_15_15 |
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie_cpts_sync_21_21_to_timesync_event_introuter_main_0_bus_in_29_29 |
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie0_pend_13_13_to_main2mcu_lvl_introuter_main_0_bus_in_80_80 |
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie1_pend_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_81_81 |
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie2_pend_7_7_to_main2mcu_lvl_introuter_main_0_bus_in_82_82 |
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie3_pend_4_4_to_main2mcu_lvl_introuter_main_0_bus_in_83_83 |
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie4_pend_5_5_to_main2mcu_lvl_introuter_main_0_bus_in_84_84 |
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie5_pend_3_3_to_main2mcu_lvl_introuter_main_0_bus_in_85_85 |
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie6_pend_11_11_to_main2mcu_lvl_introuter_main_0_bus_in_86_86 |
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie7_pend_8_8_to_main2mcu_lvl_introuter_main_0_bus_in_87_87 |
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie8_pend_9_9_to_main2mcu_lvl_introuter_main_0_bus_in_88_88 |
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie9_pend_16_16_to_main2mcu_lvl_introuter_main_0_bus_in_89_89 |
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie10_pend_15_15_to_main2mcu_lvl_introuter_main_0_bus_in_90_90 |
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie11_pend_14_14_to_main2mcu_lvl_introuter_main_0_bus_in_91_91 |
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie12_pend_6_6_to_main2mcu_lvl_introuter_main_0_bus_in_92_92 |
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie13_pend_10_10_to_main2mcu_lvl_introuter_main_0_bus_in_93_93 |
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie14_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_94_94 |
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie_cpts_pend_12_12_to_main2mcu_lvl_introuter_main_0_bus_in_95_95 |
const struct Sciclient_rmIrqIf* const tisci_if_PCIE1[] |
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static |
const struct Sciclient_rmIrqIf sa2_ul_main_0_bus_sa_ul_trng_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_4_4 |
const struct Sciclient_rmIrqIf sa2_ul_main_0_bus_sa_ul_pka_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_5_5 |
const struct Sciclient_rmIrqIf* const tisci_if_SA2_UL0[] |
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static |
const struct Sciclient_rmIrqIf spi_main_0_bus_intr_spi_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_96_96 |
const struct Sciclient_rmIrqIf* const tisci_if_MCSPI0[] |
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static |
const struct Sciclient_rmIrqIf spi_main_1_bus_intr_spi_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_97_97 |
const struct Sciclient_rmIrqIf* const tisci_if_MCSPI1[] |
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static |
const struct Sciclient_rmIrqIf spi_main_2_bus_intr_spi_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_98_98 |
const struct Sciclient_rmIrqIf* const tisci_if_MCSPI2[] |
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static |
const struct Sciclient_rmIrqIf spi_main_3_bus_intr_spi_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_99_99 |
const struct Sciclient_rmIrqIf* const tisci_if_MCSPI3[] |
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static |
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_32_39_to_pdma_main1_main_0_bus_levent_in_0_7 |
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_20_20_to_pcie_g3x2_main_0_bus_pcie_cpts_hw2_push_18_18 |
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_21_21_to_pcie_g3x2_main_1_bus_pcie_cpts_hw2_push_18_18 |
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_8_8_to_icss_g_main_0_bus_pr1_edc0_latch0_in_308_308 |
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_9_9_to_icss_g_main_0_bus_pr1_edc0_latch1_in_309_309 |
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_10_10_to_icss_g_main_0_bus_pr1_edc1_latch0_in_310_310 |
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_11_11_to_icss_g_main_0_bus_pr1_edc1_latch1_in_311_311 |
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_12_12_to_icss_g_main_1_bus_pr1_edc0_latch0_in_308_308 |
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_13_13_to_icss_g_main_1_bus_pr1_edc0_latch1_in_309_309 |
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_14_14_to_icss_g_main_1_bus_pr1_edc1_latch0_in_310_310 |
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_15_15_to_icss_g_main_1_bus_pr1_edc1_latch1_in_311_311 |
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_16_16_to_icss_g_main_2_bus_pr1_edc0_latch0_in_308_308 |
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_17_17_to_icss_g_main_2_bus_pr1_edc0_latch1_in_309_309 |
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_18_18_to_icss_g_main_2_bus_pr1_edc1_latch0_in_310_310 |
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_19_19_to_icss_g_main_2_bus_pr1_edc1_latch1_in_311_311 |
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_24_24_to_cpsw_2guss_mcu_0_bus_cpts_hw3_push_0_0 |
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_25_25_to_cpsw_2guss_mcu_0_bus_cpts_hw4_push_2_2 |
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_0_0_to_navss256l_main_0_bus_cpts0_hw1_push_0_0 |
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_1_1_to_navss256l_main_0_bus_cpts0_hw2_push_2_2 |
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_2_2_to_navss256l_main_0_bus_cpts0_hw3_push_3_3 |
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_3_3_to_navss256l_main_0_bus_cpts0_hw4_push_4_4 |
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_4_4_to_navss256l_main_0_bus_cpts0_hw5_push_5_5 |
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_5_5_to_navss256l_main_0_bus_cpts0_hw6_push_6_6 |
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_6_6_to_navss256l_main_0_bus_cpts0_hw7_push_7_7 |
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_7_7_to_navss256l_main_0_bus_cpts0_hw8_push_8_8 |
const struct Sciclient_rmIrqIf* const tisci_if_TIMESYNC_INTRTR0[] |
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static |
const struct Sciclient_rmIrqIf usart_main_0_bus_usart_irq_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_104_104 |
const struct Sciclient_rmIrqIf* const tisci_if_UART0[] |
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static |
const struct Sciclient_rmIrqIf usart_main_1_bus_usart_irq_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_105_105 |
const struct Sciclient_rmIrqIf* const tisci_if_UART1[] |
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static |
const struct Sciclient_rmIrqIf usart_main_2_bus_usart_irq_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_106_106 |
const struct Sciclient_rmIrqIf* const tisci_if_UART2[] |
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static |
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_otg_lvl_14_14_to_main2mcu_lvl_introuter_main_0_bus_in_128_128 |
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_misc_lvl_17_17_to_main2mcu_lvl_introuter_main_0_bus_in_129_129 |
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_bc_lvl_18_18_to_main2mcu_lvl_introuter_main_0_bus_in_130_130 |
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_pme_gen_lvl_16_16_to_main2mcu_lvl_introuter_main_0_bus_in_131_131 |
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i00_lvl_19_19_to_main2mcu_lvl_introuter_main_0_bus_in_132_132 |
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i01_lvl_8_8_to_main2mcu_lvl_introuter_main_0_bus_in_133_133 |
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i02_lvl_7_7_to_main2mcu_lvl_introuter_main_0_bus_in_134_134 |
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i03_lvl_13_13_to_main2mcu_lvl_introuter_main_0_bus_in_135_135 |
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i04_lvl_3_3_to_main2mcu_lvl_introuter_main_0_bus_in_136_136 |
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i05_lvl_12_12_to_main2mcu_lvl_introuter_main_0_bus_in_137_137 |
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i06_lvl_4_4_to_main2mcu_lvl_introuter_main_0_bus_in_138_138 |
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i07_lvl_6_6_to_main2mcu_lvl_introuter_main_0_bus_in_139_139 |
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i08_lvl_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_140_140 |
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i09_lvl_11_11_to_main2mcu_lvl_introuter_main_0_bus_in_141_141 |
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i10_lvl_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_142_142 |
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i11_lvl_20_20_to_main2mcu_lvl_introuter_main_0_bus_in_143_143 |
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i12_lvl_9_9_to_main2mcu_lvl_introuter_main_0_bus_in_144_144 |
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i13_lvl_15_15_to_main2mcu_lvl_introuter_main_0_bus_in_145_145 |
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i14_lvl_5_5_to_main2mcu_lvl_introuter_main_0_bus_in_146_146 |
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i15_lvl_10_10_to_main2mcu_lvl_introuter_main_0_bus_in_147_147 |
const struct Sciclient_rmIrqIf* const tisci_if_USB3SS0[] |
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const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_otg_lvl_14_14_to_main2mcu_lvl_introuter_main_0_bus_in_148_148 |
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_misc_lvl_17_17_to_main2mcu_lvl_introuter_main_0_bus_in_149_149 |
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_bc_lvl_18_18_to_main2mcu_lvl_introuter_main_0_bus_in_150_150 |
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_pme_gen_lvl_16_16_to_main2mcu_lvl_introuter_main_0_bus_in_151_151 |
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i00_lvl_19_19_to_main2mcu_lvl_introuter_main_0_bus_in_152_152 |
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i01_lvl_8_8_to_main2mcu_lvl_introuter_main_0_bus_in_153_153 |
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i02_lvl_7_7_to_main2mcu_lvl_introuter_main_0_bus_in_154_154 |
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i03_lvl_13_13_to_main2mcu_lvl_introuter_main_0_bus_in_155_155 |
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i04_lvl_3_3_to_main2mcu_lvl_introuter_main_0_bus_in_156_156 |
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i05_lvl_12_12_to_main2mcu_lvl_introuter_main_0_bus_in_157_157 |
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i06_lvl_4_4_to_main2mcu_lvl_introuter_main_0_bus_in_158_158 |
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i07_lvl_6_6_to_main2mcu_lvl_introuter_main_0_bus_in_159_159 |
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i08_lvl_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_160_160 |
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i09_lvl_11_11_to_main2mcu_lvl_introuter_main_0_bus_in_161_161 |
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i10_lvl_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_162_162 |
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i11_lvl_20_20_to_main2mcu_lvl_introuter_main_0_bus_in_163_163 |
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i12_lvl_9_9_to_main2mcu_lvl_introuter_main_0_bus_in_164_164 |
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i13_lvl_15_15_to_main2mcu_lvl_introuter_main_0_bus_in_165_165 |
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i14_lvl_5_5_to_main2mcu_lvl_introuter_main_0_bus_in_166_166 |
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i15_lvl_10_10_to_main2mcu_lvl_introuter_main_0_bus_in_167_167 |
const struct Sciclient_rmIrqIf* const tisci_if_USB3SS1[] |
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const struct Sciclient_rmIrqIf wkup_gpiomux_introuter_wkup_0_bus_outp_0_15_to_mcu_armss0_cpu0_bus_intr_124_139 |
const struct Sciclient_rmIrqIf wkup_gpiomux_introuter_wkup_0_bus_outp_0_15_to_mcu_armss0_cpu1_bus_intr_124_139 |
const struct Sciclient_rmIrqIf wkup_gpiomux_introuter_wkup_0_bus_outp_0_15_to_gic500ss_main_0_bus_spi_712_727 |
const struct Sciclient_rmIrqIf wkup_gpiomux_introuter_wkup_0_bus_outp_0_11_to_dmsc_wkup_0_bus_int_8_19 |
const struct Sciclient_rmIrqIf wkup_gpiomux_introuter_wkup_0_bus_outp_8_15_to_esm_wkup_wkup_0_bus_esm_pls_event0_256_263 |
const struct Sciclient_rmIrqIf wkup_gpiomux_introuter_wkup_0_bus_outp_8_15_to_esm_wkup_wkup_0_bus_esm_pls_event1_264_271 |
const struct Sciclient_rmIrqIf wkup_gpiomux_introuter_wkup_0_bus_outp_8_15_to_esm_wkup_wkup_0_bus_esm_pls_event2_88_95 |
const struct Sciclient_rmIrqIf* const tisci_if_WKUP_GPIOMUX_INTRTR0[] |
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const struct Sciclient_rmIrqIf navss0_cpts0_event_pend_intr_0_0_to_navss0_intr_router_0_in_intr_391_391 |
const struct Sciclient_rmIrqIf* const tisci_if_navss0_cpts0[] |
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const struct Sciclient_rmIrqIf navss0_mailbox0_cluster0_pend_intr_0_3_to_navss0_intr_router_0_in_intr_436_439 |
const struct Sciclient_rmIrqIf* const tisci_if_navss0_mailbox0_cluster0[] |
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const struct Sciclient_rmIrqIf navss0_mailbox0_cluster1_pend_intr_0_3_to_navss0_intr_router_0_in_intr_432_435 |
const struct Sciclient_rmIrqIf* const tisci_if_navss0_mailbox0_cluster1[] |
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const struct Sciclient_rmIrqIf navss0_mailbox0_cluster2_pend_intr_0_3_to_navss0_intr_router_0_in_intr_428_431 |
const struct Sciclient_rmIrqIf* const tisci_if_navss0_mailbox0_cluster2[] |
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const struct Sciclient_rmIrqIf navss0_mailbox0_cluster3_pend_intr_0_3_to_navss0_intr_router_0_in_intr_424_427 |
const struct Sciclient_rmIrqIf* const tisci_if_navss0_mailbox0_cluster3[] |
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const struct Sciclient_rmIrqIf navss0_mailbox0_cluster4_pend_intr_0_3_to_navss0_intr_router_0_in_intr_420_423 |
const struct Sciclient_rmIrqIf* const tisci_if_navss0_mailbox0_cluster4[] |
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const struct Sciclient_rmIrqIf navss0_mailbox0_cluster5_pend_intr_0_3_to_navss0_intr_router_0_in_intr_416_419 |
const struct Sciclient_rmIrqIf* const tisci_if_navss0_mailbox0_cluster5[] |
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const struct Sciclient_rmIrqIf navss0_mailbox0_cluster6_pend_intr_0_3_to_navss0_intr_router_0_in_intr_412_415 |
const struct Sciclient_rmIrqIf* const tisci_if_navss0_mailbox0_cluster6[] |
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const struct Sciclient_rmIrqIf navss0_mailbox0_cluster7_pend_intr_0_3_to_navss0_intr_router_0_in_intr_408_411 |
const struct Sciclient_rmIrqIf* const tisci_if_navss0_mailbox0_cluster7[] |
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const struct Sciclient_rmIrqIf navss0_mailbox0_cluster8_pend_intr_0_3_to_navss0_intr_router_0_in_intr_404_407 |
const struct Sciclient_rmIrqIf* const tisci_if_navss0_mailbox0_cluster8[] |
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const struct Sciclient_rmIrqIf navss0_mailbox0_cluster9_pend_intr_0_3_to_navss0_intr_router_0_in_intr_400_403 |
const struct Sciclient_rmIrqIf* const tisci_if_navss0_mailbox0_cluster9[] |
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const struct Sciclient_rmIrqIf navss0_mailbox0_cluster10_pend_intr_0_3_to_navss0_intr_router_0_in_intr_396_399 |
const struct Sciclient_rmIrqIf* const tisci_if_navss0_mailbox0_cluster10[] |
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const struct Sciclient_rmIrqIf navss0_mailbox0_cluster11_pend_intr_0_3_to_navss0_intr_router_0_in_intr_392_395 |
const struct Sciclient_rmIrqIf* const tisci_if_navss0_mailbox0_cluster11[] |
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const struct Sciclient_rmIrqIf navss0_mcrc0_dma_event_intr_0_3_to_navss0_intr_router_0_in_intr_384_387 |
const struct Sciclient_rmIrqIf navss0_mcrc0_int_mcrc_intr_8_8_to_navss0_intr_router_0_in_intr_388_388 |
const struct Sciclient_rmIrqIf navss0_mcrc0_dma_event_intr_0_3_to_navss0_udmass_inta0_intaggr_levt_pend_0_3 |
const struct Sciclient_rmIrqIf* const tisci_if_navss0_mcrc0[] |
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const struct Sciclient_rmIrqIf navss0_pvu0_pend_intr_0_0_to_navss0_intr_router_0_in_intr_390_390 |
const struct Sciclient_rmIrqIf* const tisci_if_navss0_pvu0[] |
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const struct Sciclient_rmIrqIf navss0_pvu1_pend_intr_0_0_to_navss0_intr_router_0_in_intr_389_389 |
const struct Sciclient_rmIrqIf* const tisci_if_navss0_pvu1[] |
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const struct Sciclient_rmIrqIf navss0_udmass_inta0_intaggr_vintr_pend_0_255_to_navss0_intr_router_0_in_intr_0_255 |
const struct Sciclient_rmIrqIf* const tisci_if_navss0_udmass_inta0[] |
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const struct Sciclient_rmIrqIf navss0_modss_inta0_intaggr_vintr_pend_0_63_to_navss0_intr_router_0_in_intr_320_383 |
const struct Sciclient_rmIrqIf* const tisci_if_navss0_modss_inta0[] |
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const struct Sciclient_rmIrqIf navss0_modss_inta1_intaggr_vintr_pend_0_63_to_navss0_intr_router_0_in_intr_256_319 |
const struct Sciclient_rmIrqIf* const tisci_if_navss0_modss_inta1[] |
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const struct Sciclient_rmIrqIf navss0_intr_router_0_outl_intr_136_143_to_icss_g_main_1_bus_pr1_slv_intr_46_53 |
const struct Sciclient_rmIrqIf navss0_intr_router_0_outl_intr_128_135_to_icss_g_main_0_bus_pr1_slv_intr_46_53 |
const struct Sciclient_rmIrqIf navss0_intr_router_0_outl_intr_0_63_to_gic500ss_main_0_bus_spi_64_127 |
const struct Sciclient_rmIrqIf navss0_intr_router_0_outl_intr_64_119_to_gic500ss_main_0_bus_spi_448_503 |
const struct Sciclient_rmIrqIf navss0_intr_router_0_outl_intr_144_151_to_icss_g_main_2_bus_pr1_slv_intr_46_53 |
const struct Sciclient_rmIrqIf navss0_intr_router_0_outl_intr_120_127_to_main2mcu_lvl_introuter_main_0_bus_in_184_191 |
const struct Sciclient_rmIrqIf* const tisci_if_navss0_intr_router_0[] |
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const struct Sciclient_rmIrqIf mcu_navss0_intr_aggr_0_intaggr_vintr_pend_0_255_to_mcu_navss0_intr_router_0_in_intr_0_255 |
const struct Sciclient_rmIrqIf* const tisci_if_mcu_navss0_intr_aggr_0[] |
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const struct Sciclient_rmIrqIf mcu_navss0_intr_router_0_outl_intr_0_31_to_mcu_armss0_cpu0_bus_intr_64_95 |
const struct Sciclient_rmIrqIf mcu_navss0_intr_router_0_outl_intr_32_63_to_mcu_armss0_cpu1_bus_intr_64_95 |
const struct Sciclient_rmIrqIf* const tisci_if_mcu_navss0_intr_router_0[] |
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const struct Sciclient_rmIrqNode* const gRmIrqTree[] |
const uint32_t gRmIrqTreeCount = sizeof(gRmIrqTree)/sizeof(gRmIrqTree[0]) |