PDK API Guide for AM65xx
sciclient_irq_rm.c File Reference

Introduction

File containing the AM65xx specific interrupt management data for RM.

Variables

uint8_t vint_usage_count_NAVSS0_UDMASS_INTA0 [256] = {0}
 
uint8_t vint_usage_count_NAVSS0_MODSS_INTA0 [64] = {0}
 
uint8_t vint_usage_count_NAVSS0_MODSS_INTA1 [64] = {0}
 
uint8_t vint_usage_count_MCU_NAVSS0_INTR_AGGR_0 [256] = {0}
 
static struct Sciclient_rmIaUsedMapping rom_usage_MCU_NAVSS0_INTR_AGGR_0 [3u]
 
struct Sciclient_rmIaInst gRmIaInstances [SCICLIENT_RM_IA_NUM_INST]
 
static struct Sciclient_rmIrUsedMapping rom_usage_MAIN2MCU_LVL_INTRTR0 [2U]
 
static struct Sciclient_rmIrUsedMapping rom_usage_mcu_navss0_intr_router_0 [1U]
 
struct Sciclient_rmIrInst gRmIrInstances [SCICLIENT_RM_IR_NUM_INST]
 
const struct Sciclient_rmIrqIf cal_main_0_bus_int_cal_l_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_11_11
 
const struct Sciclient_rmIrqIf *const tisci_if_CAL0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_CAL0
 
const struct Sciclient_rmIrqIf cmp_event_introuter_main_0_bus_outp_0_15_to_gic500ss_main_0_bus_spi_544_559
 
const struct Sciclient_rmIrqIf cmp_event_introuter_main_0_bus_outp_24_31_to_pdma_main1_main_0_bus_levent_in_8_15
 
const struct Sciclient_rmIrqIf *const tisci_if_CMPEVENT_INTRTR0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_CMPEVENT_INTRTR0
 
const struct Sciclient_rmIrqIf cpsw_2guss_mcu_0_bus_cpts_comp_6_6_to_cmp_event_introuter_main_0_bus_in_7_7
 
const struct Sciclient_rmIrqIf cpsw_2guss_mcu_0_bus_cpts_genf0_3_3_to_timesync_event_introuter_main_0_bus_in_12_12
 
const struct Sciclient_rmIrqIf cpsw_2guss_mcu_0_bus_cpts_genf1_4_4_to_timesync_event_introuter_main_0_bus_in_13_13
 
const struct Sciclient_rmIrqIf cpsw_2guss_mcu_0_bus_cpts_sync_5_5_to_timesync_event_introuter_main_0_bus_in_31_31
 
const struct Sciclient_rmIrqIf *const tisci_if_MCU_CPSW0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_MCU_CPSW0
 
const struct Sciclient_rmIrqIf dcc_main_0_bus_intr_done_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_120_120
 
const struct Sciclient_rmIrqIf *const tisci_if_DCC0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_DCC0
 
const struct Sciclient_rmIrqIf dcc_main_1_bus_intr_done_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_121_121
 
const struct Sciclient_rmIrqIf *const tisci_if_DCC1 []
 
static const struct Sciclient_rmIrqNode tisci_irq_DCC1
 
const struct Sciclient_rmIrqIf dcc_main_2_bus_intr_done_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_122_122
 
const struct Sciclient_rmIrqIf *const tisci_if_DCC2 []
 
static const struct Sciclient_rmIrqNode tisci_irq_DCC2
 
const struct Sciclient_rmIrqIf dcc_main_3_bus_intr_done_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_123_123
 
const struct Sciclient_rmIrqIf *const tisci_if_DCC3 []
 
static const struct Sciclient_rmIrqNode tisci_irq_DCC3
 
const struct Sciclient_rmIrqIf dcc_main_4_bus_intr_done_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_124_124
 
const struct Sciclient_rmIrqIf *const tisci_if_DCC4 []
 
static const struct Sciclient_rmIrqNode tisci_irq_DCC4
 
const struct Sciclient_rmIrqIf dcc_main_5_bus_intr_done_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_125_125
 
const struct Sciclient_rmIrqIf *const tisci_if_DCC5 []
 
static const struct Sciclient_rmIrqNode tisci_irq_DCC5
 
const struct Sciclient_rmIrqIf dcc_main_6_bus_intr_done_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_126_126
 
const struct Sciclient_rmIrqIf *const tisci_if_DCC6 []
 
static const struct Sciclient_rmIrqNode tisci_irq_DCC6
 
const struct Sciclient_rmIrqIf dcc_main_7_bus_intr_done_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_127_127
 
const struct Sciclient_rmIrqIf *const tisci_if_DCC7 []
 
static const struct Sciclient_rmIrqNode tisci_irq_DCC7
 
const struct Sciclient_rmIrqIf ddr39ss_gs80_main_0_bus_ddrss_v2h_other_err_lvl_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_10_10
 
const struct Sciclient_rmIrqIf *const tisci_if_DDRSS0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_DDRSS0
 
const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_0_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_108_108
 
const struct Sciclient_rmIrqIf *const tisci_if_TIMER0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_TIMER0
 
const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_1_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_109_109
 
const struct Sciclient_rmIrqIf *const tisci_if_TIMER1 []
 
static const struct Sciclient_rmIrqNode tisci_irq_TIMER1
 
const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_10_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_118_118
 
const struct Sciclient_rmIrqIf *const tisci_if_TIMER10 []
 
static const struct Sciclient_rmIrqNode tisci_irq_TIMER10
 
const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_11_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_119_119
 
const struct Sciclient_rmIrqIf *const tisci_if_TIMER11 []
 
static const struct Sciclient_rmIrqNode tisci_irq_TIMER11
 
const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_2_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_110_110
 
const struct Sciclient_rmIrqIf *const tisci_if_TIMER2 []
 
static const struct Sciclient_rmIrqNode tisci_irq_TIMER2
 
const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_3_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_111_111
 
const struct Sciclient_rmIrqIf *const tisci_if_TIMER3 []
 
static const struct Sciclient_rmIrqNode tisci_irq_TIMER3
 
const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_4_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_112_112
 
const struct Sciclient_rmIrqIf *const tisci_if_TIMER4 []
 
static const struct Sciclient_rmIrqNode tisci_irq_TIMER4
 
const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_5_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_113_113
 
const struct Sciclient_rmIrqIf *const tisci_if_TIMER5 []
 
static const struct Sciclient_rmIrqNode tisci_irq_TIMER5
 
const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_6_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_114_114
 
const struct Sciclient_rmIrqIf *const tisci_if_TIMER6 []
 
static const struct Sciclient_rmIrqNode tisci_irq_TIMER6
 
const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_7_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_115_115
 
const struct Sciclient_rmIrqIf *const tisci_if_TIMER7 []
 
static const struct Sciclient_rmIrqNode tisci_irq_TIMER7
 
const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_8_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_116_116
 
const struct Sciclient_rmIrqIf *const tisci_if_TIMER8 []
 
static const struct Sciclient_rmIrqNode tisci_irq_TIMER8
 
const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_9_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_117_117
 
const struct Sciclient_rmIrqIf *const tisci_if_TIMER9 []
 
static const struct Sciclient_rmIrqNode tisci_irq_TIMER9
 
const struct Sciclient_rmIrqIf ecap_main_0_bus_ecap_int_0_0_to_main2mcu_pls_introuter_main_0_bus_in_17_17
 
const struct Sciclient_rmIrqIf *const tisci_if_ECAP0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_ECAP0
 
const struct Sciclient_rmIrqIf ehrpwm_main_0_bus_epwm_etint_2_2_to_main2mcu_pls_introuter_main_0_bus_in_2_2
 
const struct Sciclient_rmIrqIf ehrpwm_main_0_bus_epwm_tripzint_0_0_to_main2mcu_pls_introuter_main_0_bus_in_8_8
 
const struct Sciclient_rmIrqIf *const tisci_if_EHRPWM0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_EHRPWM0
 
const struct Sciclient_rmIrqIf ehrpwm_main_1_bus_epwm_etint_2_2_to_main2mcu_pls_introuter_main_0_bus_in_3_3
 
const struct Sciclient_rmIrqIf ehrpwm_main_1_bus_epwm_tripzint_0_0_to_main2mcu_pls_introuter_main_0_bus_in_9_9
 
const struct Sciclient_rmIrqIf *const tisci_if_EHRPWM1 []
 
static const struct Sciclient_rmIrqNode tisci_irq_EHRPWM1
 
const struct Sciclient_rmIrqIf ehrpwm_main_2_bus_epwm_etint_2_2_to_main2mcu_pls_introuter_main_0_bus_in_4_4
 
const struct Sciclient_rmIrqIf ehrpwm_main_2_bus_epwm_tripzint_0_0_to_main2mcu_pls_introuter_main_0_bus_in_10_10
 
const struct Sciclient_rmIrqIf *const tisci_if_EHRPWM2 []
 
static const struct Sciclient_rmIrqNode tisci_irq_EHRPWM2
 
const struct Sciclient_rmIrqIf ehrpwm_main_3_bus_epwm_etint_2_2_to_main2mcu_pls_introuter_main_0_bus_in_5_5
 
const struct Sciclient_rmIrqIf ehrpwm_main_3_bus_epwm_tripzint_0_0_to_main2mcu_pls_introuter_main_0_bus_in_11_11
 
const struct Sciclient_rmIrqIf *const tisci_if_EHRPWM3 []
 
static const struct Sciclient_rmIrqNode tisci_irq_EHRPWM3
 
const struct Sciclient_rmIrqIf ehrpwm_main_4_bus_epwm_etint_2_2_to_main2mcu_pls_introuter_main_0_bus_in_6_6
 
const struct Sciclient_rmIrqIf ehrpwm_main_4_bus_epwm_tripzint_0_0_to_main2mcu_pls_introuter_main_0_bus_in_12_12
 
const struct Sciclient_rmIrqIf *const tisci_if_EHRPWM4 []
 
static const struct Sciclient_rmIrqNode tisci_irq_EHRPWM4
 
const struct Sciclient_rmIrqIf ehrpwm_main_5_bus_epwm_etint_2_2_to_main2mcu_pls_introuter_main_0_bus_in_7_7
 
const struct Sciclient_rmIrqIf ehrpwm_main_5_bus_epwm_tripzint_0_0_to_main2mcu_pls_introuter_main_0_bus_in_13_13
 
const struct Sciclient_rmIrqIf *const tisci_if_EHRPWM5 []
 
static const struct Sciclient_rmIrqNode tisci_irq_EHRPWM5
 
const struct Sciclient_rmIrqIf elm_main_0_bus_elm_porocpsinterrupt_lvl_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_7_7
 
const struct Sciclient_rmIrqIf *const tisci_if_ELM0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_ELM0
 
const struct Sciclient_rmIrqIf emmc2sd3ss_gs80_main_0_bus_emmcsdss_intr_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_29_29
 
const struct Sciclient_rmIrqIf *const tisci_if_MMCSD0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_MMCSD0
 
const struct Sciclient_rmIrqIf emmc4sd3ss_gs80_main_0_bus_emmcsdss_intr_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_28_28
 
const struct Sciclient_rmIrqIf *const tisci_if_MMCSD1 []
 
static const struct Sciclient_rmIrqNode tisci_irq_MMCSD1
 
const struct Sciclient_rmIrqIf eqep_main_0_bus_eqep_int_0_0_to_main2mcu_pls_introuter_main_0_bus_in_14_14
 
const struct Sciclient_rmIrqIf *const tisci_if_EQEP0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_EQEP0
 
const struct Sciclient_rmIrqIf eqep_main_1_bus_eqep_int_0_0_to_main2mcu_pls_introuter_main_0_bus_in_15_15
 
const struct Sciclient_rmIrqIf *const tisci_if_EQEP1 []
 
static const struct Sciclient_rmIrqNode tisci_irq_EQEP1
 
const struct Sciclient_rmIrqIf eqep_main_2_bus_eqep_int_0_0_to_main2mcu_pls_introuter_main_0_bus_in_16_16
 
const struct Sciclient_rmIrqIf *const tisci_if_EQEP2 []
 
static const struct Sciclient_rmIrqNode tisci_irq_EQEP2
 
const struct Sciclient_rmIrqIf gpio_144_main_0_bus_gpio_0_95_to_main_gpiomux_introuter_main_0_bus_in_0_95
 
const struct Sciclient_rmIrqIf gpio_144_main_0_bus_gpio_bank_256_261_to_main_gpiomux_introuter_main_0_bus_in_192_197
 
const struct Sciclient_rmIrqIf *const tisci_if_GPIO0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_GPIO0
 
const struct Sciclient_rmIrqIf gpio_144_main_1_bus_gpio_0_89_to_main_gpiomux_introuter_main_0_bus_in_96_185
 
const struct Sciclient_rmIrqIf gpio_144_main_1_bus_gpio_bank_256_261_to_main_gpiomux_introuter_main_0_bus_in_200_205
 
const struct Sciclient_rmIrqIf *const tisci_if_GPIO1 []
 
static const struct Sciclient_rmIrqNode tisci_irq_GPIO1
 
const struct Sciclient_rmIrqIf gpio_144_wkup_0_bus_gpio_0_55_to_wkup_gpiomux_introuter_wkup_0_bus_in_0_55
 
const struct Sciclient_rmIrqIf gpio_144_wkup_0_bus_gpio_bank_128_131_to_wkup_gpiomux_introuter_wkup_0_bus_in_60_63
 
const struct Sciclient_rmIrqIf *const tisci_if_WKUP_GPIO0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_WKUP_GPIO0
 
const struct Sciclient_rmIrqIf gpmc_main_0_bus_gpmc_sinterrupt_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_8_8
 
const struct Sciclient_rmIrqIf *const tisci_if_GPMC0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_GPMC0
 
const struct Sciclient_rmIrqIf icss_g_main_0_bus_pr1_rx_sof_intr_req_284_285_to_main2mcu_pls_introuter_main_0_bus_in_20_21
 
const struct Sciclient_rmIrqIf icss_g_main_0_bus_pr1_tx_sof_intr_req_302_303_to_main2mcu_pls_introuter_main_0_bus_in_22_23
 
const struct Sciclient_rmIrqIf icss_g_main_0_bus_pr1_host_intr_req_286_293_to_cmp_event_introuter_main_0_bus_in_8_15
 
const struct Sciclient_rmIrqIf icss_g_main_0_bus_pr1_iep0_cmp_intr_req_268_283_to_cmp_event_introuter_main_0_bus_in_32_47
 
const struct Sciclient_rmIrqIf icss_g_main_0_bus_pr1_iep1_cmp_intr_req_256_261_to_cmp_event_introuter_main_0_bus_in_48_53
 
const struct Sciclient_rmIrqIf icss_g_main_0_bus_pr1_iep1_cmp_intr_req_6_15_to_cmp_event_introuter_main_0_bus_in_54_63
 
const struct Sciclient_rmIrqIf icss_g_main_0_bus_pr1_edc0_sync0_out_304_304_to_timesync_event_introuter_main_0_bus_in_16_16
 
const struct Sciclient_rmIrqIf icss_g_main_0_bus_pr1_edc0_sync1_out_305_305_to_timesync_event_introuter_main_0_bus_in_17_17
 
const struct Sciclient_rmIrqIf icss_g_main_0_bus_pr1_edc1_sync0_out_306_306_to_timesync_event_introuter_main_0_bus_in_18_18
 
const struct Sciclient_rmIrqIf icss_g_main_0_bus_pr1_edc1_sync1_out_307_307_to_timesync_event_introuter_main_0_bus_in_19_19
 
const struct Sciclient_rmIrqIf icss_g_main_0_bus_pr1_host_intr_pend_294_301_to_main2mcu_lvl_introuter_main_0_bus_in_32_39
 
const struct Sciclient_rmIrqIf *const tisci_if_PRU_ICSSG0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_PRU_ICSSG0
 
const struct Sciclient_rmIrqIf icss_g_main_1_bus_pr1_rx_sof_intr_req_284_285_to_main2mcu_pls_introuter_main_0_bus_in_24_25
 
const struct Sciclient_rmIrqIf icss_g_main_1_bus_pr1_tx_sof_intr_req_302_303_to_main2mcu_pls_introuter_main_0_bus_in_26_27
 
const struct Sciclient_rmIrqIf icss_g_main_1_bus_pr1_host_intr_req_286_293_to_cmp_event_introuter_main_0_bus_in_16_23
 
const struct Sciclient_rmIrqIf icss_g_main_1_bus_pr1_iep0_cmp_intr_req_268_283_to_cmp_event_introuter_main_0_bus_in_64_79
 
const struct Sciclient_rmIrqIf icss_g_main_1_bus_pr1_iep1_cmp_intr_req_256_261_to_cmp_event_introuter_main_0_bus_in_80_85
 
const struct Sciclient_rmIrqIf icss_g_main_1_bus_pr1_iep1_cmp_intr_req_6_15_to_cmp_event_introuter_main_0_bus_in_86_95
 
const struct Sciclient_rmIrqIf icss_g_main_1_bus_pr1_edc0_sync0_out_304_304_to_timesync_event_introuter_main_0_bus_in_20_20
 
const struct Sciclient_rmIrqIf icss_g_main_1_bus_pr1_edc0_sync1_out_305_305_to_timesync_event_introuter_main_0_bus_in_21_21
 
const struct Sciclient_rmIrqIf icss_g_main_1_bus_pr1_edc1_sync0_out_306_306_to_timesync_event_introuter_main_0_bus_in_22_22
 
const struct Sciclient_rmIrqIf icss_g_main_1_bus_pr1_edc1_sync1_out_307_307_to_timesync_event_introuter_main_0_bus_in_23_23
 
const struct Sciclient_rmIrqIf icss_g_main_1_bus_pr1_host_intr_pend_294_301_to_main2mcu_lvl_introuter_main_0_bus_in_40_47
 
const struct Sciclient_rmIrqIf *const tisci_if_PRU_ICSSG1 []
 
static const struct Sciclient_rmIrqNode tisci_irq_PRU_ICSSG1
 
const struct Sciclient_rmIrqIf icss_g_main_2_bus_pr1_rx_sof_intr_req_284_285_to_main2mcu_pls_introuter_main_0_bus_in_28_29
 
const struct Sciclient_rmIrqIf icss_g_main_2_bus_pr1_tx_sof_intr_req_302_303_to_main2mcu_pls_introuter_main_0_bus_in_30_31
 
const struct Sciclient_rmIrqIf icss_g_main_2_bus_pr1_host_intr_req_286_293_to_cmp_event_introuter_main_0_bus_in_24_31
 
const struct Sciclient_rmIrqIf icss_g_main_2_bus_pr1_iep0_cmp_intr_req_268_283_to_cmp_event_introuter_main_0_bus_in_96_111
 
const struct Sciclient_rmIrqIf icss_g_main_2_bus_pr1_iep1_cmp_intr_req_256_261_to_cmp_event_introuter_main_0_bus_in_112_117
 
const struct Sciclient_rmIrqIf icss_g_main_2_bus_pr1_iep1_cmp_intr_req_6_15_to_cmp_event_introuter_main_0_bus_in_118_127
 
const struct Sciclient_rmIrqIf icss_g_main_2_bus_pr1_edc0_sync0_out_304_304_to_timesync_event_introuter_main_0_bus_in_24_24
 
const struct Sciclient_rmIrqIf icss_g_main_2_bus_pr1_edc0_sync1_out_305_305_to_timesync_event_introuter_main_0_bus_in_25_25
 
const struct Sciclient_rmIrqIf icss_g_main_2_bus_pr1_edc1_sync0_out_306_306_to_timesync_event_introuter_main_0_bus_in_26_26
 
const struct Sciclient_rmIrqIf icss_g_main_2_bus_pr1_edc1_sync1_out_307_307_to_timesync_event_introuter_main_0_bus_in_27_27
 
const struct Sciclient_rmIrqIf icss_g_main_2_bus_pr1_host_intr_pend_294_301_to_main2mcu_lvl_introuter_main_0_bus_in_48_55
 
const struct Sciclient_rmIrqIf *const tisci_if_PRU_ICSSG2 []
 
static const struct Sciclient_rmIrqNode tisci_irq_PRU_ICSSG2
 
const struct Sciclient_rmIrqIf k3_boltv2_main_0_bus_gpu_irq_3_3_to_main2mcu_lvl_introuter_main_0_bus_in_56_56
 
const struct Sciclient_rmIrqIf k3_boltv2_main_0_bus_exp_intr_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_57_57
 
const struct Sciclient_rmIrqIf k3_boltv2_main_0_bus_init_err_4_4_to_main2mcu_lvl_introuter_main_0_bus_in_58_58
 
const struct Sciclient_rmIrqIf k3_boltv2_main_0_bus_target_err_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_59_59
 
const struct Sciclient_rmIrqIf *const tisci_if_GPU0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_GPU0
 
const struct Sciclient_rmIrqIf k3_cc_debug_cell_main_0_bus_aqcmpintr_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_13_13
 
const struct Sciclient_rmIrqIf *const tisci_if_CCDEBUGSS0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_CCDEBUGSS0
 
const struct Sciclient_rmIrqIf k3_dss_ul_main_0_bus_dispc_intr_req_0_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_2_2
 
const struct Sciclient_rmIrqIf k3_dss_ul_main_0_bus_dispc_intr_req_1_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_3_3
 
const struct Sciclient_rmIrqIf *const tisci_if_DSS0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_DSS0
 
const struct Sciclient_rmIrqIf k3_main_debug_cell_main_0_bus_aqcmpintr_level_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_14_14
 
const struct Sciclient_rmIrqIf k3_main_debug_cell_main_0_bus_ctm_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_15_15
 
const struct Sciclient_rmIrqIf *const tisci_if_DEBUGSS0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_DEBUGSS0
 
const struct Sciclient_rmIrqIf m4_main_cbass_main_0_bus_LPSC_per_common_err_intr_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_172_172
 
const struct Sciclient_rmIrqIf *const tisci_if_CBASS0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_CBASS0
 
const struct Sciclient_rmIrqIf m4_main_dbg_cbass_main_0_bus_LPSC_main_debug_err_intr_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_173_173
 
const struct Sciclient_rmIrqIf *const tisci_if_CBASS_DEBUG0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_CBASS_DEBUG0
 
const struct Sciclient_rmIrqIf m4_main_fw_cbass_main_0_bus_LPSC_main_infra_err_intr_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_174_174
 
const struct Sciclient_rmIrqIf *const tisci_if_CBASS_FW0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_CBASS_FW0
 
const struct Sciclient_rmIrqIf m4_main_infra_cbass_main_0_bus_LPSC_main_infra_err_intr_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_175_175
 
const struct Sciclient_rmIrqIf *const tisci_if_CBASS_INFRA0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_CBASS_INFRA0
 
const struct Sciclient_rmIrqIf main2mcu_lvl_introuter_main_0_bus_outl_0_63_to_mcu_armss0_cpu0_bus_intr_160_223
 
const struct Sciclient_rmIrqIf main2mcu_lvl_introuter_main_0_bus_outl_0_63_to_mcu_armss0_cpu1_bus_intr_160_223
 
const struct Sciclient_rmIrqIf *const tisci_if_MAIN2MCU_LVL_INTRTR0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_MAIN2MCU_LVL_INTRTR0
 
const struct Sciclient_rmIrqIf main2mcu_pls_introuter_main_0_bus_outp_0_47_to_mcu_armss0_cpu1_bus_intr_224_271
 
const struct Sciclient_rmIrqIf main2mcu_pls_introuter_main_0_bus_outp_0_47_to_mcu_armss0_cpu0_bus_intr_224_271
 
const struct Sciclient_rmIrqIf *const tisci_if_MAIN2MCU_PLS_INTRTR0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_MAIN2MCU_PLS_INTRTR0
 
const struct Sciclient_rmIrqIf main_ctrl_mmr_main_0_bus_access_err_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_6_6
 
const struct Sciclient_rmIrqIf *const tisci_if_CTRL_MMR0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_CTRL_MMR0
 
const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_20_25_to_icss_g_main_1_bus_pr1_iep0_cap_intr_req_262_267
 
const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_26_31_to_icss_g_main_1_bus_pr1_iep1_cap_intr_req_0_5
 
const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_24_31_to_icss_g_main_1_bus_pr1_slv_intr_88_95
 
const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_20_25_to_icss_g_main_0_bus_pr1_iep0_cap_intr_req_262_267
 
const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_26_31_to_icss_g_main_0_bus_pr1_iep1_cap_intr_req_0_5
 
const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_24_31_to_icss_g_main_0_bus_pr1_slv_intr_88_95
 
const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_0_31_to_gic500ss_main_0_bus_spi_392_423
 
const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_20_25_to_icss_g_main_2_bus_pr1_iep0_cap_intr_req_262_267
 
const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_26_31_to_icss_g_main_2_bus_pr1_iep1_cap_intr_req_0_5
 
const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_24_31_to_icss_g_main_2_bus_pr1_slv_intr_88_95
 
const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_0_7_to_esm_main_main_0_bus_esm_pls_event0_512_519
 
const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_0_7_to_esm_main_main_0_bus_esm_pls_event1_520_527
 
const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_0_7_to_esm_main_main_0_bus_esm_pls_event2_248_255
 
const struct Sciclient_rmIrqIf *const tisci_if_GPIOMUX_INTRTR0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_GPIOMUX_INTRTR0
 
const struct Sciclient_rmIrqIf mcasp_main_0_bus_xmit_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_16_16
 
const struct Sciclient_rmIrqIf mcasp_main_0_bus_rec_intr_pend_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_17_17
 
const struct Sciclient_rmIrqIf *const tisci_if_MCASP0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_MCASP0
 
const struct Sciclient_rmIrqIf mcasp_main_1_bus_xmit_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_18_18
 
const struct Sciclient_rmIrqIf mcasp_main_1_bus_rec_intr_pend_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_19_19
 
const struct Sciclient_rmIrqIf *const tisci_if_MCASP1 []
 
static const struct Sciclient_rmIrqNode tisci_irq_MCASP1
 
const struct Sciclient_rmIrqIf mcasp_main_2_bus_xmit_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_20_20
 
const struct Sciclient_rmIrqIf mcasp_main_2_bus_rec_intr_pend_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_21_21
 
const struct Sciclient_rmIrqIf *const tisci_if_MCASP2 []
 
static const struct Sciclient_rmIrqNode tisci_irq_MCASP2
 
const struct Sciclient_rmIrqIf mshsi2c_main_0_bus_pointrpend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_100_100
 
const struct Sciclient_rmIrqIf *const tisci_if_I2C0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_I2C0
 
const struct Sciclient_rmIrqIf mshsi2c_main_1_bus_pointrpend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_101_101
 
const struct Sciclient_rmIrqIf *const tisci_if_I2C1 []
 
static const struct Sciclient_rmIrqNode tisci_irq_I2C1
 
const struct Sciclient_rmIrqIf mshsi2c_main_2_bus_pointrpend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_102_102
 
const struct Sciclient_rmIrqIf *const tisci_if_I2C2 []
 
static const struct Sciclient_rmIrqNode tisci_irq_I2C2
 
const struct Sciclient_rmIrqIf mshsi2c_main_3_bus_pointrpend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_103_103
 
const struct Sciclient_rmIrqIf *const tisci_if_I2C3 []
 
static const struct Sciclient_rmIrqNode tisci_irq_I2C3
 
const struct Sciclient_rmIrqIf navss256l_main_0_bus_cpts0_comp_9_9_to_cmp_event_introuter_main_0_bus_in_4_4
 
const struct Sciclient_rmIrqIf navss256l_main_0_bus_cpts0_genf0_10_10_to_timesync_event_introuter_main_0_bus_in_4_4
 
const struct Sciclient_rmIrqIf navss256l_main_0_bus_cpts0_genf1_11_11_to_timesync_event_introuter_main_0_bus_in_5_5
 
const struct Sciclient_rmIrqIf navss256l_main_0_bus_cpts0_genf2_12_12_to_timesync_event_introuter_main_0_bus_in_6_6
 
const struct Sciclient_rmIrqIf navss256l_main_0_bus_cpts0_genf3_13_13_to_timesync_event_introuter_main_0_bus_in_7_7
 
const struct Sciclient_rmIrqIf navss256l_main_0_bus_cpts0_genf4_14_14_to_timesync_event_introuter_main_0_bus_in_8_8
 
const struct Sciclient_rmIrqIf navss256l_main_0_bus_cpts0_genf5_15_15_to_timesync_event_introuter_main_0_bus_in_9_9
 
const struct Sciclient_rmIrqIf navss256l_main_0_bus_cpts0_sync_16_16_to_timesync_event_introuter_main_0_bus_in_30_30
 
const struct Sciclient_rmIrqIf *const tisci_if_NAVSS0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_NAVSS0
 
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie_cpts_comp_19_19_to_cmp_event_introuter_main_0_bus_in_5_5
 
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie_cpts_genf0_20_20_to_timesync_event_introuter_main_0_bus_in_10_10
 
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie_cpts_hw1_push_17_17_to_timesync_event_introuter_main_0_bus_in_14_14
 
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie_cpts_sync_21_21_to_timesync_event_introuter_main_0_bus_in_28_28
 
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie0_pend_13_13_to_main2mcu_lvl_introuter_main_0_bus_in_64_64
 
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie1_pend_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_65_65
 
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie2_pend_7_7_to_main2mcu_lvl_introuter_main_0_bus_in_66_66
 
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie3_pend_4_4_to_main2mcu_lvl_introuter_main_0_bus_in_67_67
 
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie4_pend_5_5_to_main2mcu_lvl_introuter_main_0_bus_in_68_68
 
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie5_pend_3_3_to_main2mcu_lvl_introuter_main_0_bus_in_69_69
 
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie6_pend_11_11_to_main2mcu_lvl_introuter_main_0_bus_in_70_70
 
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie7_pend_8_8_to_main2mcu_lvl_introuter_main_0_bus_in_71_71
 
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie8_pend_9_9_to_main2mcu_lvl_introuter_main_0_bus_in_72_72
 
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie9_pend_16_16_to_main2mcu_lvl_introuter_main_0_bus_in_73_73
 
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie10_pend_15_15_to_main2mcu_lvl_introuter_main_0_bus_in_74_74
 
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie11_pend_14_14_to_main2mcu_lvl_introuter_main_0_bus_in_75_75
 
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie12_pend_6_6_to_main2mcu_lvl_introuter_main_0_bus_in_76_76
 
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie13_pend_10_10_to_main2mcu_lvl_introuter_main_0_bus_in_77_77
 
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie14_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_78_78
 
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie_cpts_pend_12_12_to_main2mcu_lvl_introuter_main_0_bus_in_79_79
 
const struct Sciclient_rmIrqIf *const tisci_if_PCIE0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_PCIE0
 
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie_cpts_comp_19_19_to_cmp_event_introuter_main_0_bus_in_6_6
 
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie_cpts_genf0_20_20_to_timesync_event_introuter_main_0_bus_in_11_11
 
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie_cpts_hw1_push_17_17_to_timesync_event_introuter_main_0_bus_in_15_15
 
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie_cpts_sync_21_21_to_timesync_event_introuter_main_0_bus_in_29_29
 
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie0_pend_13_13_to_main2mcu_lvl_introuter_main_0_bus_in_80_80
 
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie1_pend_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_81_81
 
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie2_pend_7_7_to_main2mcu_lvl_introuter_main_0_bus_in_82_82
 
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie3_pend_4_4_to_main2mcu_lvl_introuter_main_0_bus_in_83_83
 
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie4_pend_5_5_to_main2mcu_lvl_introuter_main_0_bus_in_84_84
 
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie5_pend_3_3_to_main2mcu_lvl_introuter_main_0_bus_in_85_85
 
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie6_pend_11_11_to_main2mcu_lvl_introuter_main_0_bus_in_86_86
 
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie7_pend_8_8_to_main2mcu_lvl_introuter_main_0_bus_in_87_87
 
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie8_pend_9_9_to_main2mcu_lvl_introuter_main_0_bus_in_88_88
 
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie9_pend_16_16_to_main2mcu_lvl_introuter_main_0_bus_in_89_89
 
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie10_pend_15_15_to_main2mcu_lvl_introuter_main_0_bus_in_90_90
 
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie11_pend_14_14_to_main2mcu_lvl_introuter_main_0_bus_in_91_91
 
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie12_pend_6_6_to_main2mcu_lvl_introuter_main_0_bus_in_92_92
 
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie13_pend_10_10_to_main2mcu_lvl_introuter_main_0_bus_in_93_93
 
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie14_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_94_94
 
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie_cpts_pend_12_12_to_main2mcu_lvl_introuter_main_0_bus_in_95_95
 
const struct Sciclient_rmIrqIf *const tisci_if_PCIE1 []
 
static const struct Sciclient_rmIrqNode tisci_irq_PCIE1
 
const struct Sciclient_rmIrqIf sa2_ul_main_0_bus_sa_ul_trng_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_4_4
 
const struct Sciclient_rmIrqIf sa2_ul_main_0_bus_sa_ul_pka_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_5_5
 
const struct Sciclient_rmIrqIf *const tisci_if_SA2_UL0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_SA2_UL0
 
const struct Sciclient_rmIrqIf spi_main_0_bus_intr_spi_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_96_96
 
const struct Sciclient_rmIrqIf *const tisci_if_MCSPI0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_MCSPI0
 
const struct Sciclient_rmIrqIf spi_main_1_bus_intr_spi_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_97_97
 
const struct Sciclient_rmIrqIf *const tisci_if_MCSPI1 []
 
static const struct Sciclient_rmIrqNode tisci_irq_MCSPI1
 
const struct Sciclient_rmIrqIf spi_main_2_bus_intr_spi_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_98_98
 
const struct Sciclient_rmIrqIf *const tisci_if_MCSPI2 []
 
static const struct Sciclient_rmIrqNode tisci_irq_MCSPI2
 
const struct Sciclient_rmIrqIf spi_main_3_bus_intr_spi_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_99_99
 
const struct Sciclient_rmIrqIf *const tisci_if_MCSPI3 []
 
static const struct Sciclient_rmIrqNode tisci_irq_MCSPI3
 
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_32_39_to_pdma_main1_main_0_bus_levent_in_0_7
 
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_20_20_to_pcie_g3x2_main_0_bus_pcie_cpts_hw2_push_18_18
 
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_21_21_to_pcie_g3x2_main_1_bus_pcie_cpts_hw2_push_18_18
 
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_8_8_to_icss_g_main_0_bus_pr1_edc0_latch0_in_308_308
 
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_9_9_to_icss_g_main_0_bus_pr1_edc0_latch1_in_309_309
 
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_10_10_to_icss_g_main_0_bus_pr1_edc1_latch0_in_310_310
 
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_11_11_to_icss_g_main_0_bus_pr1_edc1_latch1_in_311_311
 
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_12_12_to_icss_g_main_1_bus_pr1_edc0_latch0_in_308_308
 
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_13_13_to_icss_g_main_1_bus_pr1_edc0_latch1_in_309_309
 
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_14_14_to_icss_g_main_1_bus_pr1_edc1_latch0_in_310_310
 
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_15_15_to_icss_g_main_1_bus_pr1_edc1_latch1_in_311_311
 
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_16_16_to_icss_g_main_2_bus_pr1_edc0_latch0_in_308_308
 
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_17_17_to_icss_g_main_2_bus_pr1_edc0_latch1_in_309_309
 
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_18_18_to_icss_g_main_2_bus_pr1_edc1_latch0_in_310_310
 
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_19_19_to_icss_g_main_2_bus_pr1_edc1_latch1_in_311_311
 
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_24_24_to_cpsw_2guss_mcu_0_bus_cpts_hw3_push_0_0
 
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_25_25_to_cpsw_2guss_mcu_0_bus_cpts_hw4_push_2_2
 
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_0_0_to_navss256l_main_0_bus_cpts0_hw1_push_0_0
 
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_1_1_to_navss256l_main_0_bus_cpts0_hw2_push_2_2
 
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_2_2_to_navss256l_main_0_bus_cpts0_hw3_push_3_3
 
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_3_3_to_navss256l_main_0_bus_cpts0_hw4_push_4_4
 
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_4_4_to_navss256l_main_0_bus_cpts0_hw5_push_5_5
 
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_5_5_to_navss256l_main_0_bus_cpts0_hw6_push_6_6
 
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_6_6_to_navss256l_main_0_bus_cpts0_hw7_push_7_7
 
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_7_7_to_navss256l_main_0_bus_cpts0_hw8_push_8_8
 
const struct Sciclient_rmIrqIf *const tisci_if_TIMESYNC_INTRTR0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_TIMESYNC_INTRTR0
 
const struct Sciclient_rmIrqIf usart_main_0_bus_usart_irq_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_104_104
 
const struct Sciclient_rmIrqIf *const tisci_if_UART0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_UART0
 
const struct Sciclient_rmIrqIf usart_main_1_bus_usart_irq_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_105_105
 
const struct Sciclient_rmIrqIf *const tisci_if_UART1 []
 
static const struct Sciclient_rmIrqNode tisci_irq_UART1
 
const struct Sciclient_rmIrqIf usart_main_2_bus_usart_irq_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_106_106
 
const struct Sciclient_rmIrqIf *const tisci_if_UART2 []
 
static const struct Sciclient_rmIrqNode tisci_irq_UART2
 
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_otg_lvl_14_14_to_main2mcu_lvl_introuter_main_0_bus_in_128_128
 
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_misc_lvl_17_17_to_main2mcu_lvl_introuter_main_0_bus_in_129_129
 
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_bc_lvl_18_18_to_main2mcu_lvl_introuter_main_0_bus_in_130_130
 
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_pme_gen_lvl_16_16_to_main2mcu_lvl_introuter_main_0_bus_in_131_131
 
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i00_lvl_19_19_to_main2mcu_lvl_introuter_main_0_bus_in_132_132
 
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i01_lvl_8_8_to_main2mcu_lvl_introuter_main_0_bus_in_133_133
 
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i02_lvl_7_7_to_main2mcu_lvl_introuter_main_0_bus_in_134_134
 
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i03_lvl_13_13_to_main2mcu_lvl_introuter_main_0_bus_in_135_135
 
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i04_lvl_3_3_to_main2mcu_lvl_introuter_main_0_bus_in_136_136
 
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i05_lvl_12_12_to_main2mcu_lvl_introuter_main_0_bus_in_137_137
 
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i06_lvl_4_4_to_main2mcu_lvl_introuter_main_0_bus_in_138_138
 
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i07_lvl_6_6_to_main2mcu_lvl_introuter_main_0_bus_in_139_139
 
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i08_lvl_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_140_140
 
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i09_lvl_11_11_to_main2mcu_lvl_introuter_main_0_bus_in_141_141
 
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i10_lvl_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_142_142
 
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i11_lvl_20_20_to_main2mcu_lvl_introuter_main_0_bus_in_143_143
 
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i12_lvl_9_9_to_main2mcu_lvl_introuter_main_0_bus_in_144_144
 
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i13_lvl_15_15_to_main2mcu_lvl_introuter_main_0_bus_in_145_145
 
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i14_lvl_5_5_to_main2mcu_lvl_introuter_main_0_bus_in_146_146
 
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i15_lvl_10_10_to_main2mcu_lvl_introuter_main_0_bus_in_147_147
 
const struct Sciclient_rmIrqIf *const tisci_if_USB3SS0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_USB3SS0
 
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_otg_lvl_14_14_to_main2mcu_lvl_introuter_main_0_bus_in_148_148
 
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_misc_lvl_17_17_to_main2mcu_lvl_introuter_main_0_bus_in_149_149
 
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_bc_lvl_18_18_to_main2mcu_lvl_introuter_main_0_bus_in_150_150
 
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_pme_gen_lvl_16_16_to_main2mcu_lvl_introuter_main_0_bus_in_151_151
 
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i00_lvl_19_19_to_main2mcu_lvl_introuter_main_0_bus_in_152_152
 
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i01_lvl_8_8_to_main2mcu_lvl_introuter_main_0_bus_in_153_153
 
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i02_lvl_7_7_to_main2mcu_lvl_introuter_main_0_bus_in_154_154
 
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i03_lvl_13_13_to_main2mcu_lvl_introuter_main_0_bus_in_155_155
 
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i04_lvl_3_3_to_main2mcu_lvl_introuter_main_0_bus_in_156_156
 
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i05_lvl_12_12_to_main2mcu_lvl_introuter_main_0_bus_in_157_157
 
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i06_lvl_4_4_to_main2mcu_lvl_introuter_main_0_bus_in_158_158
 
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i07_lvl_6_6_to_main2mcu_lvl_introuter_main_0_bus_in_159_159
 
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i08_lvl_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_160_160
 
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i09_lvl_11_11_to_main2mcu_lvl_introuter_main_0_bus_in_161_161
 
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i10_lvl_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_162_162
 
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i11_lvl_20_20_to_main2mcu_lvl_introuter_main_0_bus_in_163_163
 
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i12_lvl_9_9_to_main2mcu_lvl_introuter_main_0_bus_in_164_164
 
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i13_lvl_15_15_to_main2mcu_lvl_introuter_main_0_bus_in_165_165
 
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i14_lvl_5_5_to_main2mcu_lvl_introuter_main_0_bus_in_166_166
 
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i15_lvl_10_10_to_main2mcu_lvl_introuter_main_0_bus_in_167_167
 
const struct Sciclient_rmIrqIf *const tisci_if_USB3SS1 []
 
static const struct Sciclient_rmIrqNode tisci_irq_USB3SS1
 
const struct Sciclient_rmIrqIf wkup_gpiomux_introuter_wkup_0_bus_outp_0_15_to_mcu_armss0_cpu0_bus_intr_124_139
 
const struct Sciclient_rmIrqIf wkup_gpiomux_introuter_wkup_0_bus_outp_0_15_to_mcu_armss0_cpu1_bus_intr_124_139
 
const struct Sciclient_rmIrqIf wkup_gpiomux_introuter_wkup_0_bus_outp_0_15_to_gic500ss_main_0_bus_spi_712_727
 
const struct Sciclient_rmIrqIf wkup_gpiomux_introuter_wkup_0_bus_outp_0_11_to_dmsc_wkup_0_bus_int_8_19
 
const struct Sciclient_rmIrqIf wkup_gpiomux_introuter_wkup_0_bus_outp_8_15_to_esm_wkup_wkup_0_bus_esm_pls_event0_256_263
 
const struct Sciclient_rmIrqIf wkup_gpiomux_introuter_wkup_0_bus_outp_8_15_to_esm_wkup_wkup_0_bus_esm_pls_event1_264_271
 
const struct Sciclient_rmIrqIf wkup_gpiomux_introuter_wkup_0_bus_outp_8_15_to_esm_wkup_wkup_0_bus_esm_pls_event2_88_95
 
const struct Sciclient_rmIrqIf *const tisci_if_WKUP_GPIOMUX_INTRTR0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_WKUP_GPIOMUX_INTRTR0
 
const struct Sciclient_rmIrqIf navss0_cpts0_event_pend_intr_0_0_to_navss0_intr_router_0_in_intr_391_391
 
const struct Sciclient_rmIrqIf *const tisci_if_navss0_cpts0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_navss0_cpts0
 
const struct Sciclient_rmIrqIf navss0_mailbox0_cluster0_pend_intr_0_3_to_navss0_intr_router_0_in_intr_436_439
 
const struct Sciclient_rmIrqIf *const tisci_if_navss0_mailbox0_cluster0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_navss0_mailbox0_cluster0
 
const struct Sciclient_rmIrqIf navss0_mailbox0_cluster1_pend_intr_0_3_to_navss0_intr_router_0_in_intr_432_435
 
const struct Sciclient_rmIrqIf *const tisci_if_navss0_mailbox0_cluster1 []
 
static const struct Sciclient_rmIrqNode tisci_irq_navss0_mailbox0_cluster1
 
const struct Sciclient_rmIrqIf navss0_mailbox0_cluster2_pend_intr_0_3_to_navss0_intr_router_0_in_intr_428_431
 
const struct Sciclient_rmIrqIf *const tisci_if_navss0_mailbox0_cluster2 []
 
static const struct Sciclient_rmIrqNode tisci_irq_navss0_mailbox0_cluster2
 
const struct Sciclient_rmIrqIf navss0_mailbox0_cluster3_pend_intr_0_3_to_navss0_intr_router_0_in_intr_424_427
 
const struct Sciclient_rmIrqIf *const tisci_if_navss0_mailbox0_cluster3 []
 
static const struct Sciclient_rmIrqNode tisci_irq_navss0_mailbox0_cluster3
 
const struct Sciclient_rmIrqIf navss0_mailbox0_cluster4_pend_intr_0_3_to_navss0_intr_router_0_in_intr_420_423
 
const struct Sciclient_rmIrqIf *const tisci_if_navss0_mailbox0_cluster4 []
 
static const struct Sciclient_rmIrqNode tisci_irq_navss0_mailbox0_cluster4
 
const struct Sciclient_rmIrqIf navss0_mailbox0_cluster5_pend_intr_0_3_to_navss0_intr_router_0_in_intr_416_419
 
const struct Sciclient_rmIrqIf *const tisci_if_navss0_mailbox0_cluster5 []
 
static const struct Sciclient_rmIrqNode tisci_irq_navss0_mailbox0_cluster5
 
const struct Sciclient_rmIrqIf navss0_mailbox0_cluster6_pend_intr_0_3_to_navss0_intr_router_0_in_intr_412_415
 
const struct Sciclient_rmIrqIf *const tisci_if_navss0_mailbox0_cluster6 []
 
static const struct Sciclient_rmIrqNode tisci_irq_navss0_mailbox0_cluster6
 
const struct Sciclient_rmIrqIf navss0_mailbox0_cluster7_pend_intr_0_3_to_navss0_intr_router_0_in_intr_408_411
 
const struct Sciclient_rmIrqIf *const tisci_if_navss0_mailbox0_cluster7 []
 
static const struct Sciclient_rmIrqNode tisci_irq_navss0_mailbox0_cluster7
 
const struct Sciclient_rmIrqIf navss0_mailbox0_cluster8_pend_intr_0_3_to_navss0_intr_router_0_in_intr_404_407
 
const struct Sciclient_rmIrqIf *const tisci_if_navss0_mailbox0_cluster8 []
 
static const struct Sciclient_rmIrqNode tisci_irq_navss0_mailbox0_cluster8
 
const struct Sciclient_rmIrqIf navss0_mailbox0_cluster9_pend_intr_0_3_to_navss0_intr_router_0_in_intr_400_403
 
const struct Sciclient_rmIrqIf *const tisci_if_navss0_mailbox0_cluster9 []
 
static const struct Sciclient_rmIrqNode tisci_irq_navss0_mailbox0_cluster9
 
const struct Sciclient_rmIrqIf navss0_mailbox0_cluster10_pend_intr_0_3_to_navss0_intr_router_0_in_intr_396_399
 
const struct Sciclient_rmIrqIf *const tisci_if_navss0_mailbox0_cluster10 []
 
static const struct Sciclient_rmIrqNode tisci_irq_navss0_mailbox0_cluster10
 
const struct Sciclient_rmIrqIf navss0_mailbox0_cluster11_pend_intr_0_3_to_navss0_intr_router_0_in_intr_392_395
 
const struct Sciclient_rmIrqIf *const tisci_if_navss0_mailbox0_cluster11 []
 
static const struct Sciclient_rmIrqNode tisci_irq_navss0_mailbox0_cluster11
 
const struct Sciclient_rmIrqIf navss0_mcrc0_dma_event_intr_0_3_to_navss0_intr_router_0_in_intr_384_387
 
const struct Sciclient_rmIrqIf navss0_mcrc0_int_mcrc_intr_8_8_to_navss0_intr_router_0_in_intr_388_388
 
const struct Sciclient_rmIrqIf navss0_mcrc0_dma_event_intr_0_3_to_navss0_udmass_inta0_intaggr_levt_pend_0_3
 
const struct Sciclient_rmIrqIf *const tisci_if_navss0_mcrc0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_navss0_mcrc0
 
const struct Sciclient_rmIrqIf navss0_pvu0_pend_intr_0_0_to_navss0_intr_router_0_in_intr_390_390
 
const struct Sciclient_rmIrqIf *const tisci_if_navss0_pvu0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_navss0_pvu0
 
const struct Sciclient_rmIrqIf navss0_pvu1_pend_intr_0_0_to_navss0_intr_router_0_in_intr_389_389
 
const struct Sciclient_rmIrqIf *const tisci_if_navss0_pvu1 []
 
static const struct Sciclient_rmIrqNode tisci_irq_navss0_pvu1
 
const struct Sciclient_rmIrqIf navss0_udmass_inta0_intaggr_vintr_pend_0_255_to_navss0_intr_router_0_in_intr_0_255
 
const struct Sciclient_rmIrqIf *const tisci_if_navss0_udmass_inta0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_navss0_udmass_inta0
 
const struct Sciclient_rmIrqIf navss0_modss_inta0_intaggr_vintr_pend_0_63_to_navss0_intr_router_0_in_intr_320_383
 
const struct Sciclient_rmIrqIf *const tisci_if_navss0_modss_inta0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_navss0_modss_inta0
 
const struct Sciclient_rmIrqIf navss0_modss_inta1_intaggr_vintr_pend_0_63_to_navss0_intr_router_0_in_intr_256_319
 
const struct Sciclient_rmIrqIf *const tisci_if_navss0_modss_inta1 []
 
static const struct Sciclient_rmIrqNode tisci_irq_navss0_modss_inta1
 
const struct Sciclient_rmIrqIf navss0_intr_router_0_outl_intr_136_143_to_icss_g_main_1_bus_pr1_slv_intr_46_53
 
const struct Sciclient_rmIrqIf navss0_intr_router_0_outl_intr_128_135_to_icss_g_main_0_bus_pr1_slv_intr_46_53
 
const struct Sciclient_rmIrqIf navss0_intr_router_0_outl_intr_0_63_to_gic500ss_main_0_bus_spi_64_127
 
const struct Sciclient_rmIrqIf navss0_intr_router_0_outl_intr_64_119_to_gic500ss_main_0_bus_spi_448_503
 
const struct Sciclient_rmIrqIf navss0_intr_router_0_outl_intr_144_151_to_icss_g_main_2_bus_pr1_slv_intr_46_53
 
const struct Sciclient_rmIrqIf navss0_intr_router_0_outl_intr_120_127_to_main2mcu_lvl_introuter_main_0_bus_in_184_191
 
const struct Sciclient_rmIrqIf *const tisci_if_navss0_intr_router_0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_navss0_intr_router_0
 
const struct Sciclient_rmIrqIf mcu_navss0_intr_aggr_0_intaggr_vintr_pend_0_255_to_mcu_navss0_intr_router_0_in_intr_0_255
 
const struct Sciclient_rmIrqIf *const tisci_if_mcu_navss0_intr_aggr_0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_mcu_navss0_intr_aggr_0
 
const struct Sciclient_rmIrqIf mcu_navss0_intr_router_0_outl_intr_0_31_to_mcu_armss0_cpu0_bus_intr_64_95
 
const struct Sciclient_rmIrqIf mcu_navss0_intr_router_0_outl_intr_32_63_to_mcu_armss0_cpu1_bus_intr_64_95
 
const struct Sciclient_rmIrqIf *const tisci_if_mcu_navss0_intr_router_0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_mcu_navss0_intr_router_0
 
const struct Sciclient_rmIrqNode *const gRmIrqTree []
 
const uint32_t gRmIrqTreeCount = sizeof(gRmIrqTree)/sizeof(gRmIrqTree[0])
 

Variable Documentation

◆ vint_usage_count_NAVSS0_UDMASS_INTA0

uint8_t vint_usage_count_NAVSS0_UDMASS_INTA0[256] = {0}

◆ vint_usage_count_NAVSS0_MODSS_INTA0

uint8_t vint_usage_count_NAVSS0_MODSS_INTA0[64] = {0}

◆ vint_usage_count_NAVSS0_MODSS_INTA1

uint8_t vint_usage_count_NAVSS0_MODSS_INTA1[64] = {0}

◆ vint_usage_count_MCU_NAVSS0_INTR_AGGR_0

uint8_t vint_usage_count_MCU_NAVSS0_INTR_AGGR_0[256] = {0}

◆ rom_usage_MCU_NAVSS0_INTR_AGGR_0

struct Sciclient_rmIaUsedMapping rom_usage_MCU_NAVSS0_INTR_AGGR_0[3u]
static
Initial value:
= {
{
.event = 16404U,
.cleared = false,
},
{
.event = 16405U,
.cleared = false,
},
{
.event = 16414U,
.cleared = false,
}
}

◆ gRmIaInstances

struct Sciclient_rmIaInst gRmIaInstances[SCICLIENT_RM_IA_NUM_INST]

◆ rom_usage_MAIN2MCU_LVL_INTRTR0

struct Sciclient_rmIrUsedMapping rom_usage_MAIN2MCU_LVL_INTRTR0[2U]
static
Initial value:
= {
{
.inp_start = 64U,
.outp_start = 0U,
.length = 32U,
.cleared = false,
.opCleared = false,
},
{
.inp_start = 28U,
.outp_start = 32U,
.length = 2U,
.cleared = false,
.opCleared = false,
},
}

◆ rom_usage_mcu_navss0_intr_router_0

struct Sciclient_rmIrUsedMapping rom_usage_mcu_navss0_intr_router_0[1U]
static
Initial value:
= {
{
.inp_start = 1U,
.outp_start = 0U,
.length = 2U,
.cleared = false,
.opCleared = false,
},
}

◆ gRmIrInstances

struct Sciclient_rmIrInst gRmIrInstances[SCICLIENT_RM_IR_NUM_INST]

◆ cal_main_0_bus_int_cal_l_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_11_11

const struct Sciclient_rmIrqIf cal_main_0_bus_int_cal_l_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_11_11
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 11,
}

◆ tisci_if_CAL0

const struct Sciclient_rmIrqIf* const tisci_if_CAL0[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf cal_main_0_bus_int_cal_l_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_11_11
Definition: sciclient_irq_rm.c:222

◆ tisci_irq_CAL0

const struct Sciclient_rmIrqNode tisci_irq_CAL0
static
Initial value:
= {
.id = TISCI_DEV_CAL0,
.n_if = 1,
.p_if = &tisci_if_CAL0[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_CAL0[]
Definition: sciclient_irq_rm.c:228

◆ cmp_event_introuter_main_0_bus_outp_0_15_to_gic500ss_main_0_bus_spi_544_559

const struct Sciclient_rmIrqIf cmp_event_introuter_main_0_bus_outp_0_15_to_gic500ss_main_0_bus_spi_544_559
Initial value:
= {
.lbase = 0,
.len = 16,
.rid = TISCI_DEV_GIC0,
.rbase = 544,
}

◆ cmp_event_introuter_main_0_bus_outp_24_31_to_pdma_main1_main_0_bus_levent_in_8_15

const struct Sciclient_rmIrqIf cmp_event_introuter_main_0_bus_outp_24_31_to_pdma_main1_main_0_bus_levent_in_8_15
Initial value:
= {
.lbase = 24,
.len = 8,
.rid = TISCI_DEV_PDMA1,
.rbase = 8,
}

◆ tisci_if_CMPEVENT_INTRTR0

const struct Sciclient_rmIrqIf* const tisci_if_CMPEVENT_INTRTR0[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf cmp_event_introuter_main_0_bus_outp_0_15_to_gic500ss_main_0_bus_spi_544_559
Definition: sciclient_irq_rm.c:238
const struct Sciclient_rmIrqIf cmp_event_introuter_main_0_bus_outp_24_31_to_pdma_main1_main_0_bus_levent_in_8_15
Definition: sciclient_irq_rm.c:244

◆ tisci_irq_CMPEVENT_INTRTR0

const struct Sciclient_rmIrqNode tisci_irq_CMPEVENT_INTRTR0
static
Initial value:
= {
.id = TISCI_DEV_CMPEVENT_INTRTR0,
.n_if = 2,
}
const struct Sciclient_rmIrqIf *const tisci_if_CMPEVENT_INTRTR0[]
Definition: sciclient_irq_rm.c:250

◆ cpsw_2guss_mcu_0_bus_cpts_comp_6_6_to_cmp_event_introuter_main_0_bus_in_7_7

const struct Sciclient_rmIrqIf cpsw_2guss_mcu_0_bus_cpts_comp_6_6_to_cmp_event_introuter_main_0_bus_in_7_7
Initial value:
= {
.lbase = 6,
.len = 1,
.rid = TISCI_DEV_CMPEVENT_INTRTR0,
.rbase = 7,
}

◆ cpsw_2guss_mcu_0_bus_cpts_genf0_3_3_to_timesync_event_introuter_main_0_bus_in_12_12

const struct Sciclient_rmIrqIf cpsw_2guss_mcu_0_bus_cpts_genf0_3_3_to_timesync_event_introuter_main_0_bus_in_12_12
Initial value:
= {
.lbase = 3,
.len = 1,
.rid = TISCI_DEV_TIMESYNC_INTRTR0,
.rbase = 12,
}

◆ cpsw_2guss_mcu_0_bus_cpts_genf1_4_4_to_timesync_event_introuter_main_0_bus_in_13_13

const struct Sciclient_rmIrqIf cpsw_2guss_mcu_0_bus_cpts_genf1_4_4_to_timesync_event_introuter_main_0_bus_in_13_13
Initial value:
= {
.lbase = 4,
.len = 1,
.rid = TISCI_DEV_TIMESYNC_INTRTR0,
.rbase = 13,
}

◆ cpsw_2guss_mcu_0_bus_cpts_sync_5_5_to_timesync_event_introuter_main_0_bus_in_31_31

const struct Sciclient_rmIrqIf cpsw_2guss_mcu_0_bus_cpts_sync_5_5_to_timesync_event_introuter_main_0_bus_in_31_31
Initial value:
= {
.lbase = 5,
.len = 1,
.rid = TISCI_DEV_TIMESYNC_INTRTR0,
.rbase = 31,
}

◆ tisci_if_MCU_CPSW0

const struct Sciclient_rmIrqIf* const tisci_if_MCU_CPSW0[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf cpsw_2guss_mcu_0_bus_cpts_sync_5_5_to_timesync_event_introuter_main_0_bus_in_31_31
Definition: sciclient_irq_rm.c:279
const struct Sciclient_rmIrqIf cpsw_2guss_mcu_0_bus_cpts_comp_6_6_to_cmp_event_introuter_main_0_bus_in_7_7
Definition: sciclient_irq_rm.c:261
const struct Sciclient_rmIrqIf cpsw_2guss_mcu_0_bus_cpts_genf0_3_3_to_timesync_event_introuter_main_0_bus_in_12_12
Definition: sciclient_irq_rm.c:267
const struct Sciclient_rmIrqIf cpsw_2guss_mcu_0_bus_cpts_genf1_4_4_to_timesync_event_introuter_main_0_bus_in_13_13
Definition: sciclient_irq_rm.c:273

◆ tisci_irq_MCU_CPSW0

const struct Sciclient_rmIrqNode tisci_irq_MCU_CPSW0
static
Initial value:
= {
.id = TISCI_DEV_MCU_CPSW0,
.n_if = 4,
.p_if = &tisci_if_MCU_CPSW0[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_MCU_CPSW0[]
Definition: sciclient_irq_rm.c:285

◆ dcc_main_0_bus_intr_done_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_120_120

const struct Sciclient_rmIrqIf dcc_main_0_bus_intr_done_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_120_120
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 120,
}

◆ tisci_if_DCC0

const struct Sciclient_rmIrqIf* const tisci_if_DCC0[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf dcc_main_0_bus_intr_done_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_120_120
Definition: sciclient_irq_rm.c:298

◆ tisci_irq_DCC0

const struct Sciclient_rmIrqNode tisci_irq_DCC0
static
Initial value:
= {
.id = TISCI_DEV_DCC0,
.n_if = 1,
.p_if = &tisci_if_DCC0[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_DCC0[]
Definition: sciclient_irq_rm.c:304

◆ dcc_main_1_bus_intr_done_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_121_121

const struct Sciclient_rmIrqIf dcc_main_1_bus_intr_done_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_121_121
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 121,
}

◆ tisci_if_DCC1

const struct Sciclient_rmIrqIf* const tisci_if_DCC1[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf dcc_main_1_bus_intr_done_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_121_121
Definition: sciclient_irq_rm.c:314

◆ tisci_irq_DCC1

const struct Sciclient_rmIrqNode tisci_irq_DCC1
static
Initial value:
= {
.id = TISCI_DEV_DCC1,
.n_if = 1,
.p_if = &tisci_if_DCC1[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_DCC1[]
Definition: sciclient_irq_rm.c:320

◆ dcc_main_2_bus_intr_done_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_122_122

const struct Sciclient_rmIrqIf dcc_main_2_bus_intr_done_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_122_122
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 122,
}

◆ tisci_if_DCC2

const struct Sciclient_rmIrqIf* const tisci_if_DCC2[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf dcc_main_2_bus_intr_done_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_122_122
Definition: sciclient_irq_rm.c:330

◆ tisci_irq_DCC2

const struct Sciclient_rmIrqNode tisci_irq_DCC2
static
Initial value:
= {
.id = TISCI_DEV_DCC2,
.n_if = 1,
.p_if = &tisci_if_DCC2[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_DCC2[]
Definition: sciclient_irq_rm.c:336

◆ dcc_main_3_bus_intr_done_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_123_123

const struct Sciclient_rmIrqIf dcc_main_3_bus_intr_done_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_123_123
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 123,
}

◆ tisci_if_DCC3

const struct Sciclient_rmIrqIf* const tisci_if_DCC3[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf dcc_main_3_bus_intr_done_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_123_123
Definition: sciclient_irq_rm.c:346

◆ tisci_irq_DCC3

const struct Sciclient_rmIrqNode tisci_irq_DCC3
static
Initial value:
= {
.id = TISCI_DEV_DCC3,
.n_if = 1,
.p_if = &tisci_if_DCC3[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_DCC3[]
Definition: sciclient_irq_rm.c:352

◆ dcc_main_4_bus_intr_done_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_124_124

const struct Sciclient_rmIrqIf dcc_main_4_bus_intr_done_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_124_124
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 124,
}

◆ tisci_if_DCC4

const struct Sciclient_rmIrqIf* const tisci_if_DCC4[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf dcc_main_4_bus_intr_done_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_124_124
Definition: sciclient_irq_rm.c:362

◆ tisci_irq_DCC4

const struct Sciclient_rmIrqNode tisci_irq_DCC4
static
Initial value:
= {
.id = TISCI_DEV_DCC4,
.n_if = 1,
.p_if = &tisci_if_DCC4[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_DCC4[]
Definition: sciclient_irq_rm.c:368

◆ dcc_main_5_bus_intr_done_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_125_125

const struct Sciclient_rmIrqIf dcc_main_5_bus_intr_done_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_125_125
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 125,
}

◆ tisci_if_DCC5

const struct Sciclient_rmIrqIf* const tisci_if_DCC5[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf dcc_main_5_bus_intr_done_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_125_125
Definition: sciclient_irq_rm.c:378

◆ tisci_irq_DCC5

const struct Sciclient_rmIrqNode tisci_irq_DCC5
static
Initial value:
= {
.id = TISCI_DEV_DCC5,
.n_if = 1,
.p_if = &tisci_if_DCC5[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_DCC5[]
Definition: sciclient_irq_rm.c:384

◆ dcc_main_6_bus_intr_done_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_126_126

const struct Sciclient_rmIrqIf dcc_main_6_bus_intr_done_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_126_126
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 126,
}

◆ tisci_if_DCC6

const struct Sciclient_rmIrqIf* const tisci_if_DCC6[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf dcc_main_6_bus_intr_done_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_126_126
Definition: sciclient_irq_rm.c:394

◆ tisci_irq_DCC6

const struct Sciclient_rmIrqNode tisci_irq_DCC6
static
Initial value:
= {
.id = TISCI_DEV_DCC6,
.n_if = 1,
.p_if = &tisci_if_DCC6[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_DCC6[]
Definition: sciclient_irq_rm.c:400

◆ dcc_main_7_bus_intr_done_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_127_127

const struct Sciclient_rmIrqIf dcc_main_7_bus_intr_done_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_127_127
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 127,
}

◆ tisci_if_DCC7

const struct Sciclient_rmIrqIf* const tisci_if_DCC7[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf dcc_main_7_bus_intr_done_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_127_127
Definition: sciclient_irq_rm.c:410

◆ tisci_irq_DCC7

const struct Sciclient_rmIrqNode tisci_irq_DCC7
static
Initial value:
= {
.id = TISCI_DEV_DCC7,
.n_if = 1,
.p_if = &tisci_if_DCC7[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_DCC7[]
Definition: sciclient_irq_rm.c:416

◆ ddr39ss_gs80_main_0_bus_ddrss_v2h_other_err_lvl_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_10_10

const struct Sciclient_rmIrqIf ddr39ss_gs80_main_0_bus_ddrss_v2h_other_err_lvl_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_10_10
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 10,
}

◆ tisci_if_DDRSS0

const struct Sciclient_rmIrqIf* const tisci_if_DDRSS0[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf ddr39ss_gs80_main_0_bus_ddrss_v2h_other_err_lvl_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_10_10
Definition: sciclient_irq_rm.c:426

◆ tisci_irq_DDRSS0

const struct Sciclient_rmIrqNode tisci_irq_DDRSS0
static
Initial value:
= {
.id = TISCI_DEV_DDRSS0,
.n_if = 1,
.p_if = &tisci_if_DDRSS0[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_DDRSS0[]
Definition: sciclient_irq_rm.c:432

◆ dmtimer_dmc1ms_main_0_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_108_108

const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_0_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_108_108
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 108,
}

◆ tisci_if_TIMER0

const struct Sciclient_rmIrqIf* const tisci_if_TIMER0[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_0_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_108_108
Definition: sciclient_irq_rm.c:442

◆ tisci_irq_TIMER0

const struct Sciclient_rmIrqNode tisci_irq_TIMER0
static
Initial value:
= {
.id = TISCI_DEV_TIMER0,
.n_if = 1,
.p_if = &tisci_if_TIMER0[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_TIMER0[]
Definition: sciclient_irq_rm.c:448

◆ dmtimer_dmc1ms_main_1_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_109_109

const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_1_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_109_109
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 109,
}

◆ tisci_if_TIMER1

const struct Sciclient_rmIrqIf* const tisci_if_TIMER1[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_1_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_109_109
Definition: sciclient_irq_rm.c:458

◆ tisci_irq_TIMER1

const struct Sciclient_rmIrqNode tisci_irq_TIMER1
static
Initial value:
= {
.id = TISCI_DEV_TIMER1,
.n_if = 1,
.p_if = &tisci_if_TIMER1[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_TIMER1[]
Definition: sciclient_irq_rm.c:464

◆ dmtimer_dmc1ms_main_10_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_118_118

const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_10_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_118_118
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 118,
}

◆ tisci_if_TIMER10

const struct Sciclient_rmIrqIf* const tisci_if_TIMER10[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_10_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_118_118
Definition: sciclient_irq_rm.c:474

◆ tisci_irq_TIMER10

const struct Sciclient_rmIrqNode tisci_irq_TIMER10
static
Initial value:
= {
.id = TISCI_DEV_TIMER10,
.n_if = 1,
.p_if = &tisci_if_TIMER10[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_TIMER10[]
Definition: sciclient_irq_rm.c:480

◆ dmtimer_dmc1ms_main_11_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_119_119

const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_11_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_119_119
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 119,
}

◆ tisci_if_TIMER11

const struct Sciclient_rmIrqIf* const tisci_if_TIMER11[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_11_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_119_119
Definition: sciclient_irq_rm.c:490

◆ tisci_irq_TIMER11

const struct Sciclient_rmIrqNode tisci_irq_TIMER11
static
Initial value:
= {
.id = TISCI_DEV_TIMER11,
.n_if = 1,
.p_if = &tisci_if_TIMER11[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_TIMER11[]
Definition: sciclient_irq_rm.c:496

◆ dmtimer_dmc1ms_main_2_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_110_110

const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_2_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_110_110
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 110,
}

◆ tisci_if_TIMER2

const struct Sciclient_rmIrqIf* const tisci_if_TIMER2[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_2_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_110_110
Definition: sciclient_irq_rm.c:506

◆ tisci_irq_TIMER2

const struct Sciclient_rmIrqNode tisci_irq_TIMER2
static
Initial value:
= {
.id = TISCI_DEV_TIMER2,
.n_if = 1,
.p_if = &tisci_if_TIMER2[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_TIMER2[]
Definition: sciclient_irq_rm.c:512

◆ dmtimer_dmc1ms_main_3_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_111_111

const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_3_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_111_111
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 111,
}

◆ tisci_if_TIMER3

const struct Sciclient_rmIrqIf* const tisci_if_TIMER3[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_3_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_111_111
Definition: sciclient_irq_rm.c:522

◆ tisci_irq_TIMER3

const struct Sciclient_rmIrqNode tisci_irq_TIMER3
static
Initial value:
= {
.id = TISCI_DEV_TIMER3,
.n_if = 1,
.p_if = &tisci_if_TIMER3[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_TIMER3[]
Definition: sciclient_irq_rm.c:528

◆ dmtimer_dmc1ms_main_4_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_112_112

const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_4_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_112_112
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 112,
}

◆ tisci_if_TIMER4

const struct Sciclient_rmIrqIf* const tisci_if_TIMER4[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_4_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_112_112
Definition: sciclient_irq_rm.c:538

◆ tisci_irq_TIMER4

const struct Sciclient_rmIrqNode tisci_irq_TIMER4
static
Initial value:
= {
.id = TISCI_DEV_TIMER4,
.n_if = 1,
.p_if = &tisci_if_TIMER4[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_TIMER4[]
Definition: sciclient_irq_rm.c:544

◆ dmtimer_dmc1ms_main_5_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_113_113

const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_5_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_113_113
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 113,
}

◆ tisci_if_TIMER5

const struct Sciclient_rmIrqIf* const tisci_if_TIMER5[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_5_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_113_113
Definition: sciclient_irq_rm.c:554

◆ tisci_irq_TIMER5

const struct Sciclient_rmIrqNode tisci_irq_TIMER5
static
Initial value:
= {
.id = TISCI_DEV_TIMER5,
.n_if = 1,
.p_if = &tisci_if_TIMER5[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_TIMER5[]
Definition: sciclient_irq_rm.c:560

◆ dmtimer_dmc1ms_main_6_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_114_114

const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_6_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_114_114
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 114,
}

◆ tisci_if_TIMER6

const struct Sciclient_rmIrqIf* const tisci_if_TIMER6[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_6_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_114_114
Definition: sciclient_irq_rm.c:570

◆ tisci_irq_TIMER6

const struct Sciclient_rmIrqNode tisci_irq_TIMER6
static
Initial value:
= {
.id = TISCI_DEV_TIMER6,
.n_if = 1,
.p_if = &tisci_if_TIMER6[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_TIMER6[]
Definition: sciclient_irq_rm.c:576

◆ dmtimer_dmc1ms_main_7_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_115_115

const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_7_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_115_115
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 115,
}

◆ tisci_if_TIMER7

const struct Sciclient_rmIrqIf* const tisci_if_TIMER7[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_7_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_115_115
Definition: sciclient_irq_rm.c:586

◆ tisci_irq_TIMER7

const struct Sciclient_rmIrqNode tisci_irq_TIMER7
static
Initial value:
= {
.id = TISCI_DEV_TIMER7,
.n_if = 1,
.p_if = &tisci_if_TIMER7[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_TIMER7[]
Definition: sciclient_irq_rm.c:592

◆ dmtimer_dmc1ms_main_8_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_116_116

const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_8_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_116_116
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 116,
}

◆ tisci_if_TIMER8

const struct Sciclient_rmIrqIf* const tisci_if_TIMER8[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_8_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_116_116
Definition: sciclient_irq_rm.c:602

◆ tisci_irq_TIMER8

const struct Sciclient_rmIrqNode tisci_irq_TIMER8
static
Initial value:
= {
.id = TISCI_DEV_TIMER8,
.n_if = 1,
.p_if = &tisci_if_TIMER8[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_TIMER8[]
Definition: sciclient_irq_rm.c:608

◆ dmtimer_dmc1ms_main_9_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_117_117

const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_9_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_117_117
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 117,
}

◆ tisci_if_TIMER9

const struct Sciclient_rmIrqIf* const tisci_if_TIMER9[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf dmtimer_dmc1ms_main_9_bus_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_117_117
Definition: sciclient_irq_rm.c:618

◆ tisci_irq_TIMER9

const struct Sciclient_rmIrqNode tisci_irq_TIMER9
static
Initial value:
= {
.id = TISCI_DEV_TIMER9,
.n_if = 1,
.p_if = &tisci_if_TIMER9[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_TIMER9[]
Definition: sciclient_irq_rm.c:624

◆ ecap_main_0_bus_ecap_int_0_0_to_main2mcu_pls_introuter_main_0_bus_in_17_17

const struct Sciclient_rmIrqIf ecap_main_0_bus_ecap_int_0_0_to_main2mcu_pls_introuter_main_0_bus_in_17_17
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_PLS_INTRTR0,
.rbase = 17,
}

◆ tisci_if_ECAP0

const struct Sciclient_rmIrqIf* const tisci_if_ECAP0[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf ecap_main_0_bus_ecap_int_0_0_to_main2mcu_pls_introuter_main_0_bus_in_17_17
Definition: sciclient_irq_rm.c:634

◆ tisci_irq_ECAP0

const struct Sciclient_rmIrqNode tisci_irq_ECAP0
static
Initial value:
= {
.id = TISCI_DEV_ECAP0,
.n_if = 1,
.p_if = &tisci_if_ECAP0[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_ECAP0[]
Definition: sciclient_irq_rm.c:640

◆ ehrpwm_main_0_bus_epwm_etint_2_2_to_main2mcu_pls_introuter_main_0_bus_in_2_2

const struct Sciclient_rmIrqIf ehrpwm_main_0_bus_epwm_etint_2_2_to_main2mcu_pls_introuter_main_0_bus_in_2_2
Initial value:
= {
.lbase = 2,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_PLS_INTRTR0,
.rbase = 2,
}

◆ ehrpwm_main_0_bus_epwm_tripzint_0_0_to_main2mcu_pls_introuter_main_0_bus_in_8_8

const struct Sciclient_rmIrqIf ehrpwm_main_0_bus_epwm_tripzint_0_0_to_main2mcu_pls_introuter_main_0_bus_in_8_8
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_PLS_INTRTR0,
.rbase = 8,
}

◆ tisci_if_EHRPWM0

const struct Sciclient_rmIrqIf* const tisci_if_EHRPWM0[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf ehrpwm_main_0_bus_epwm_tripzint_0_0_to_main2mcu_pls_introuter_main_0_bus_in_8_8
Definition: sciclient_irq_rm.c:656
const struct Sciclient_rmIrqIf ehrpwm_main_0_bus_epwm_etint_2_2_to_main2mcu_pls_introuter_main_0_bus_in_2_2
Definition: sciclient_irq_rm.c:650

◆ tisci_irq_EHRPWM0

const struct Sciclient_rmIrqNode tisci_irq_EHRPWM0
static
Initial value:
= {
.id = TISCI_DEV_EHRPWM0,
.n_if = 2,
.p_if = &tisci_if_EHRPWM0[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_EHRPWM0[]
Definition: sciclient_irq_rm.c:662

◆ ehrpwm_main_1_bus_epwm_etint_2_2_to_main2mcu_pls_introuter_main_0_bus_in_3_3

const struct Sciclient_rmIrqIf ehrpwm_main_1_bus_epwm_etint_2_2_to_main2mcu_pls_introuter_main_0_bus_in_3_3
Initial value:
= {
.lbase = 2,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_PLS_INTRTR0,
.rbase = 3,
}

◆ ehrpwm_main_1_bus_epwm_tripzint_0_0_to_main2mcu_pls_introuter_main_0_bus_in_9_9

const struct Sciclient_rmIrqIf ehrpwm_main_1_bus_epwm_tripzint_0_0_to_main2mcu_pls_introuter_main_0_bus_in_9_9
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_PLS_INTRTR0,
.rbase = 9,
}

◆ tisci_if_EHRPWM1

const struct Sciclient_rmIrqIf* const tisci_if_EHRPWM1[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf ehrpwm_main_1_bus_epwm_etint_2_2_to_main2mcu_pls_introuter_main_0_bus_in_3_3
Definition: sciclient_irq_rm.c:673
const struct Sciclient_rmIrqIf ehrpwm_main_1_bus_epwm_tripzint_0_0_to_main2mcu_pls_introuter_main_0_bus_in_9_9
Definition: sciclient_irq_rm.c:679

◆ tisci_irq_EHRPWM1

const struct Sciclient_rmIrqNode tisci_irq_EHRPWM1
static
Initial value:
= {
.id = TISCI_DEV_EHRPWM1,
.n_if = 2,
.p_if = &tisci_if_EHRPWM1[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_EHRPWM1[]
Definition: sciclient_irq_rm.c:685

◆ ehrpwm_main_2_bus_epwm_etint_2_2_to_main2mcu_pls_introuter_main_0_bus_in_4_4

const struct Sciclient_rmIrqIf ehrpwm_main_2_bus_epwm_etint_2_2_to_main2mcu_pls_introuter_main_0_bus_in_4_4
Initial value:
= {
.lbase = 2,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_PLS_INTRTR0,
.rbase = 4,
}

◆ ehrpwm_main_2_bus_epwm_tripzint_0_0_to_main2mcu_pls_introuter_main_0_bus_in_10_10

const struct Sciclient_rmIrqIf ehrpwm_main_2_bus_epwm_tripzint_0_0_to_main2mcu_pls_introuter_main_0_bus_in_10_10
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_PLS_INTRTR0,
.rbase = 10,
}

◆ tisci_if_EHRPWM2

const struct Sciclient_rmIrqIf* const tisci_if_EHRPWM2[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf ehrpwm_main_2_bus_epwm_tripzint_0_0_to_main2mcu_pls_introuter_main_0_bus_in_10_10
Definition: sciclient_irq_rm.c:702
const struct Sciclient_rmIrqIf ehrpwm_main_2_bus_epwm_etint_2_2_to_main2mcu_pls_introuter_main_0_bus_in_4_4
Definition: sciclient_irq_rm.c:696

◆ tisci_irq_EHRPWM2

const struct Sciclient_rmIrqNode tisci_irq_EHRPWM2
static
Initial value:
= {
.id = TISCI_DEV_EHRPWM2,
.n_if = 2,
.p_if = &tisci_if_EHRPWM2[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_EHRPWM2[]
Definition: sciclient_irq_rm.c:708

◆ ehrpwm_main_3_bus_epwm_etint_2_2_to_main2mcu_pls_introuter_main_0_bus_in_5_5

const struct Sciclient_rmIrqIf ehrpwm_main_3_bus_epwm_etint_2_2_to_main2mcu_pls_introuter_main_0_bus_in_5_5
Initial value:
= {
.lbase = 2,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_PLS_INTRTR0,
.rbase = 5,
}

◆ ehrpwm_main_3_bus_epwm_tripzint_0_0_to_main2mcu_pls_introuter_main_0_bus_in_11_11

const struct Sciclient_rmIrqIf ehrpwm_main_3_bus_epwm_tripzint_0_0_to_main2mcu_pls_introuter_main_0_bus_in_11_11
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_PLS_INTRTR0,
.rbase = 11,
}

◆ tisci_if_EHRPWM3

const struct Sciclient_rmIrqIf* const tisci_if_EHRPWM3[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf ehrpwm_main_3_bus_epwm_etint_2_2_to_main2mcu_pls_introuter_main_0_bus_in_5_5
Definition: sciclient_irq_rm.c:719
const struct Sciclient_rmIrqIf ehrpwm_main_3_bus_epwm_tripzint_0_0_to_main2mcu_pls_introuter_main_0_bus_in_11_11
Definition: sciclient_irq_rm.c:725

◆ tisci_irq_EHRPWM3

const struct Sciclient_rmIrqNode tisci_irq_EHRPWM3
static
Initial value:
= {
.id = TISCI_DEV_EHRPWM3,
.n_if = 2,
.p_if = &tisci_if_EHRPWM3[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_EHRPWM3[]
Definition: sciclient_irq_rm.c:731

◆ ehrpwm_main_4_bus_epwm_etint_2_2_to_main2mcu_pls_introuter_main_0_bus_in_6_6

const struct Sciclient_rmIrqIf ehrpwm_main_4_bus_epwm_etint_2_2_to_main2mcu_pls_introuter_main_0_bus_in_6_6
Initial value:
= {
.lbase = 2,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_PLS_INTRTR0,
.rbase = 6,
}

◆ ehrpwm_main_4_bus_epwm_tripzint_0_0_to_main2mcu_pls_introuter_main_0_bus_in_12_12

const struct Sciclient_rmIrqIf ehrpwm_main_4_bus_epwm_tripzint_0_0_to_main2mcu_pls_introuter_main_0_bus_in_12_12
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_PLS_INTRTR0,
.rbase = 12,
}

◆ tisci_if_EHRPWM4

const struct Sciclient_rmIrqIf* const tisci_if_EHRPWM4[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf ehrpwm_main_4_bus_epwm_etint_2_2_to_main2mcu_pls_introuter_main_0_bus_in_6_6
Definition: sciclient_irq_rm.c:742
const struct Sciclient_rmIrqIf ehrpwm_main_4_bus_epwm_tripzint_0_0_to_main2mcu_pls_introuter_main_0_bus_in_12_12
Definition: sciclient_irq_rm.c:748

◆ tisci_irq_EHRPWM4

const struct Sciclient_rmIrqNode tisci_irq_EHRPWM4
static
Initial value:
= {
.id = TISCI_DEV_EHRPWM4,
.n_if = 2,
.p_if = &tisci_if_EHRPWM4[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_EHRPWM4[]
Definition: sciclient_irq_rm.c:754

◆ ehrpwm_main_5_bus_epwm_etint_2_2_to_main2mcu_pls_introuter_main_0_bus_in_7_7

const struct Sciclient_rmIrqIf ehrpwm_main_5_bus_epwm_etint_2_2_to_main2mcu_pls_introuter_main_0_bus_in_7_7
Initial value:
= {
.lbase = 2,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_PLS_INTRTR0,
.rbase = 7,
}

◆ ehrpwm_main_5_bus_epwm_tripzint_0_0_to_main2mcu_pls_introuter_main_0_bus_in_13_13

const struct Sciclient_rmIrqIf ehrpwm_main_5_bus_epwm_tripzint_0_0_to_main2mcu_pls_introuter_main_0_bus_in_13_13
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_PLS_INTRTR0,
.rbase = 13,
}

◆ tisci_if_EHRPWM5

const struct Sciclient_rmIrqIf* const tisci_if_EHRPWM5[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf ehrpwm_main_5_bus_epwm_etint_2_2_to_main2mcu_pls_introuter_main_0_bus_in_7_7
Definition: sciclient_irq_rm.c:765
const struct Sciclient_rmIrqIf ehrpwm_main_5_bus_epwm_tripzint_0_0_to_main2mcu_pls_introuter_main_0_bus_in_13_13
Definition: sciclient_irq_rm.c:771

◆ tisci_irq_EHRPWM5

const struct Sciclient_rmIrqNode tisci_irq_EHRPWM5
static
Initial value:
= {
.id = TISCI_DEV_EHRPWM5,
.n_if = 2,
.p_if = &tisci_if_EHRPWM5[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_EHRPWM5[]
Definition: sciclient_irq_rm.c:777

◆ elm_main_0_bus_elm_porocpsinterrupt_lvl_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_7_7

const struct Sciclient_rmIrqIf elm_main_0_bus_elm_porocpsinterrupt_lvl_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_7_7
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 7,
}

◆ tisci_if_ELM0

const struct Sciclient_rmIrqIf* const tisci_if_ELM0[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf elm_main_0_bus_elm_porocpsinterrupt_lvl_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_7_7
Definition: sciclient_irq_rm.c:788

◆ tisci_irq_ELM0

const struct Sciclient_rmIrqNode tisci_irq_ELM0
static
Initial value:
= {
.id = TISCI_DEV_ELM0,
.n_if = 1,
.p_if = &tisci_if_ELM0[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_ELM0[]
Definition: sciclient_irq_rm.c:794

◆ emmc2sd3ss_gs80_main_0_bus_emmcsdss_intr_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_29_29

const struct Sciclient_rmIrqIf emmc2sd3ss_gs80_main_0_bus_emmcsdss_intr_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_29_29
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 29,
}

◆ tisci_if_MMCSD0

const struct Sciclient_rmIrqIf* const tisci_if_MMCSD0[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf emmc2sd3ss_gs80_main_0_bus_emmcsdss_intr_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_29_29
Definition: sciclient_irq_rm.c:804

◆ tisci_irq_MMCSD0

const struct Sciclient_rmIrqNode tisci_irq_MMCSD0
static
Initial value:
= {
.id = TISCI_DEV_MMCSD0,
.n_if = 1,
.p_if = &tisci_if_MMCSD0[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_MMCSD0[]
Definition: sciclient_irq_rm.c:810

◆ emmc4sd3ss_gs80_main_0_bus_emmcsdss_intr_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_28_28

const struct Sciclient_rmIrqIf emmc4sd3ss_gs80_main_0_bus_emmcsdss_intr_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_28_28
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 28,
}

◆ tisci_if_MMCSD1

const struct Sciclient_rmIrqIf* const tisci_if_MMCSD1[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf emmc4sd3ss_gs80_main_0_bus_emmcsdss_intr_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_28_28
Definition: sciclient_irq_rm.c:820

◆ tisci_irq_MMCSD1

const struct Sciclient_rmIrqNode tisci_irq_MMCSD1
static
Initial value:
= {
.id = TISCI_DEV_MMCSD1,
.n_if = 1,
.p_if = &tisci_if_MMCSD1[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_MMCSD1[]
Definition: sciclient_irq_rm.c:826

◆ eqep_main_0_bus_eqep_int_0_0_to_main2mcu_pls_introuter_main_0_bus_in_14_14

const struct Sciclient_rmIrqIf eqep_main_0_bus_eqep_int_0_0_to_main2mcu_pls_introuter_main_0_bus_in_14_14
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_PLS_INTRTR0,
.rbase = 14,
}

◆ tisci_if_EQEP0

const struct Sciclient_rmIrqIf* const tisci_if_EQEP0[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf eqep_main_0_bus_eqep_int_0_0_to_main2mcu_pls_introuter_main_0_bus_in_14_14
Definition: sciclient_irq_rm.c:836

◆ tisci_irq_EQEP0

const struct Sciclient_rmIrqNode tisci_irq_EQEP0
static
Initial value:
= {
.id = TISCI_DEV_EQEP0,
.n_if = 1,
.p_if = &tisci_if_EQEP0[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_EQEP0[]
Definition: sciclient_irq_rm.c:842

◆ eqep_main_1_bus_eqep_int_0_0_to_main2mcu_pls_introuter_main_0_bus_in_15_15

const struct Sciclient_rmIrqIf eqep_main_1_bus_eqep_int_0_0_to_main2mcu_pls_introuter_main_0_bus_in_15_15
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_PLS_INTRTR0,
.rbase = 15,
}

◆ tisci_if_EQEP1

const struct Sciclient_rmIrqIf* const tisci_if_EQEP1[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf eqep_main_1_bus_eqep_int_0_0_to_main2mcu_pls_introuter_main_0_bus_in_15_15
Definition: sciclient_irq_rm.c:852

◆ tisci_irq_EQEP1

const struct Sciclient_rmIrqNode tisci_irq_EQEP1
static
Initial value:
= {
.id = TISCI_DEV_EQEP1,
.n_if = 1,
.p_if = &tisci_if_EQEP1[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_EQEP1[]
Definition: sciclient_irq_rm.c:858

◆ eqep_main_2_bus_eqep_int_0_0_to_main2mcu_pls_introuter_main_0_bus_in_16_16

const struct Sciclient_rmIrqIf eqep_main_2_bus_eqep_int_0_0_to_main2mcu_pls_introuter_main_0_bus_in_16_16
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_PLS_INTRTR0,
.rbase = 16,
}

◆ tisci_if_EQEP2

const struct Sciclient_rmIrqIf* const tisci_if_EQEP2[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf eqep_main_2_bus_eqep_int_0_0_to_main2mcu_pls_introuter_main_0_bus_in_16_16
Definition: sciclient_irq_rm.c:868

◆ tisci_irq_EQEP2

const struct Sciclient_rmIrqNode tisci_irq_EQEP2
static
Initial value:
= {
.id = TISCI_DEV_EQEP2,
.n_if = 1,
.p_if = &tisci_if_EQEP2[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_EQEP2[]
Definition: sciclient_irq_rm.c:874

◆ gpio_144_main_0_bus_gpio_0_95_to_main_gpiomux_introuter_main_0_bus_in_0_95

const struct Sciclient_rmIrqIf gpio_144_main_0_bus_gpio_0_95_to_main_gpiomux_introuter_main_0_bus_in_0_95
Initial value:
= {
.lbase = 0,
.len = 96,
.rid = TISCI_DEV_GPIOMUX_INTRTR0,
.rbase = 0,
}

◆ gpio_144_main_0_bus_gpio_bank_256_261_to_main_gpiomux_introuter_main_0_bus_in_192_197

const struct Sciclient_rmIrqIf gpio_144_main_0_bus_gpio_bank_256_261_to_main_gpiomux_introuter_main_0_bus_in_192_197
Initial value:
= {
.lbase = 256,
.len = 6,
.rid = TISCI_DEV_GPIOMUX_INTRTR0,
.rbase = 192,
}

◆ tisci_if_GPIO0

const struct Sciclient_rmIrqIf* const tisci_if_GPIO0[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf gpio_144_main_0_bus_gpio_0_95_to_main_gpiomux_introuter_main_0_bus_in_0_95
Definition: sciclient_irq_rm.c:884
const struct Sciclient_rmIrqIf gpio_144_main_0_bus_gpio_bank_256_261_to_main_gpiomux_introuter_main_0_bus_in_192_197
Definition: sciclient_irq_rm.c:890

◆ tisci_irq_GPIO0

const struct Sciclient_rmIrqNode tisci_irq_GPIO0
static
Initial value:
= {
.id = TISCI_DEV_GPIO0,
.n_if = 2,
.p_if = &tisci_if_GPIO0[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_GPIO0[]
Definition: sciclient_irq_rm.c:896

◆ gpio_144_main_1_bus_gpio_0_89_to_main_gpiomux_introuter_main_0_bus_in_96_185

const struct Sciclient_rmIrqIf gpio_144_main_1_bus_gpio_0_89_to_main_gpiomux_introuter_main_0_bus_in_96_185
Initial value:
= {
.lbase = 0,
.len = 90,
.rid = TISCI_DEV_GPIOMUX_INTRTR0,
.rbase = 96,
}

◆ gpio_144_main_1_bus_gpio_bank_256_261_to_main_gpiomux_introuter_main_0_bus_in_200_205

const struct Sciclient_rmIrqIf gpio_144_main_1_bus_gpio_bank_256_261_to_main_gpiomux_introuter_main_0_bus_in_200_205
Initial value:
= {
.lbase = 256,
.len = 6,
.rid = TISCI_DEV_GPIOMUX_INTRTR0,
.rbase = 200,
}

◆ tisci_if_GPIO1

const struct Sciclient_rmIrqIf* const tisci_if_GPIO1[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf gpio_144_main_1_bus_gpio_bank_256_261_to_main_gpiomux_introuter_main_0_bus_in_200_205
Definition: sciclient_irq_rm.c:913
const struct Sciclient_rmIrqIf gpio_144_main_1_bus_gpio_0_89_to_main_gpiomux_introuter_main_0_bus_in_96_185
Definition: sciclient_irq_rm.c:907

◆ tisci_irq_GPIO1

const struct Sciclient_rmIrqNode tisci_irq_GPIO1
static
Initial value:
= {
.id = TISCI_DEV_GPIO1,
.n_if = 2,
.p_if = &tisci_if_GPIO1[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_GPIO1[]
Definition: sciclient_irq_rm.c:919

◆ gpio_144_wkup_0_bus_gpio_0_55_to_wkup_gpiomux_introuter_wkup_0_bus_in_0_55

const struct Sciclient_rmIrqIf gpio_144_wkup_0_bus_gpio_0_55_to_wkup_gpiomux_introuter_wkup_0_bus_in_0_55
Initial value:
= {
.lbase = 0,
.len = 56,
.rid = TISCI_DEV_WKUP_GPIOMUX_INTRTR0,
.rbase = 0,
}

◆ gpio_144_wkup_0_bus_gpio_bank_128_131_to_wkup_gpiomux_introuter_wkup_0_bus_in_60_63

const struct Sciclient_rmIrqIf gpio_144_wkup_0_bus_gpio_bank_128_131_to_wkup_gpiomux_introuter_wkup_0_bus_in_60_63
Initial value:
= {
.lbase = 128,
.len = 4,
.rid = TISCI_DEV_WKUP_GPIOMUX_INTRTR0,
.rbase = 60,
}

◆ tisci_if_WKUP_GPIO0

const struct Sciclient_rmIrqIf* const tisci_if_WKUP_GPIO0[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf gpio_144_wkup_0_bus_gpio_0_55_to_wkup_gpiomux_introuter_wkup_0_bus_in_0_55
Definition: sciclient_irq_rm.c:930
const struct Sciclient_rmIrqIf gpio_144_wkup_0_bus_gpio_bank_128_131_to_wkup_gpiomux_introuter_wkup_0_bus_in_60_63
Definition: sciclient_irq_rm.c:936

◆ tisci_irq_WKUP_GPIO0

const struct Sciclient_rmIrqNode tisci_irq_WKUP_GPIO0
static
Initial value:
= {
.id = TISCI_DEV_WKUP_GPIO0,
.n_if = 2,
.p_if = &tisci_if_WKUP_GPIO0[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_WKUP_GPIO0[]
Definition: sciclient_irq_rm.c:942

◆ gpmc_main_0_bus_gpmc_sinterrupt_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_8_8

const struct Sciclient_rmIrqIf gpmc_main_0_bus_gpmc_sinterrupt_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_8_8
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 8,
}

◆ tisci_if_GPMC0

const struct Sciclient_rmIrqIf* const tisci_if_GPMC0[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf gpmc_main_0_bus_gpmc_sinterrupt_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_8_8
Definition: sciclient_irq_rm.c:953

◆ tisci_irq_GPMC0

const struct Sciclient_rmIrqNode tisci_irq_GPMC0
static
Initial value:
= {
.id = TISCI_DEV_GPMC0,
.n_if = 1,
.p_if = &tisci_if_GPMC0[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_GPMC0[]
Definition: sciclient_irq_rm.c:959

◆ icss_g_main_0_bus_pr1_rx_sof_intr_req_284_285_to_main2mcu_pls_introuter_main_0_bus_in_20_21

const struct Sciclient_rmIrqIf icss_g_main_0_bus_pr1_rx_sof_intr_req_284_285_to_main2mcu_pls_introuter_main_0_bus_in_20_21
Initial value:
= {
.lbase = 284,
.len = 2,
.rid = TISCI_DEV_MAIN2MCU_PLS_INTRTR0,
.rbase = 20,
}

◆ icss_g_main_0_bus_pr1_tx_sof_intr_req_302_303_to_main2mcu_pls_introuter_main_0_bus_in_22_23

const struct Sciclient_rmIrqIf icss_g_main_0_bus_pr1_tx_sof_intr_req_302_303_to_main2mcu_pls_introuter_main_0_bus_in_22_23
Initial value:
= {
.lbase = 302,
.len = 2,
.rid = TISCI_DEV_MAIN2MCU_PLS_INTRTR0,
.rbase = 22,
}

◆ icss_g_main_0_bus_pr1_host_intr_req_286_293_to_cmp_event_introuter_main_0_bus_in_8_15

const struct Sciclient_rmIrqIf icss_g_main_0_bus_pr1_host_intr_req_286_293_to_cmp_event_introuter_main_0_bus_in_8_15
Initial value:
= {
.lbase = 286,
.len = 8,
.rid = TISCI_DEV_CMPEVENT_INTRTR0,
.rbase = 8,
}

◆ icss_g_main_0_bus_pr1_iep0_cmp_intr_req_268_283_to_cmp_event_introuter_main_0_bus_in_32_47

const struct Sciclient_rmIrqIf icss_g_main_0_bus_pr1_iep0_cmp_intr_req_268_283_to_cmp_event_introuter_main_0_bus_in_32_47
Initial value:
= {
.lbase = 268,
.len = 16,
.rid = TISCI_DEV_CMPEVENT_INTRTR0,
.rbase = 32,
}

◆ icss_g_main_0_bus_pr1_iep1_cmp_intr_req_256_261_to_cmp_event_introuter_main_0_bus_in_48_53

const struct Sciclient_rmIrqIf icss_g_main_0_bus_pr1_iep1_cmp_intr_req_256_261_to_cmp_event_introuter_main_0_bus_in_48_53
Initial value:
= {
.lbase = 256,
.len = 6,
.rid = TISCI_DEV_CMPEVENT_INTRTR0,
.rbase = 48,
}

◆ icss_g_main_0_bus_pr1_iep1_cmp_intr_req_6_15_to_cmp_event_introuter_main_0_bus_in_54_63

const struct Sciclient_rmIrqIf icss_g_main_0_bus_pr1_iep1_cmp_intr_req_6_15_to_cmp_event_introuter_main_0_bus_in_54_63
Initial value:
= {
.lbase = 6,
.len = 10,
.rid = TISCI_DEV_CMPEVENT_INTRTR0,
.rbase = 54,
}

◆ icss_g_main_0_bus_pr1_edc0_sync0_out_304_304_to_timesync_event_introuter_main_0_bus_in_16_16

const struct Sciclient_rmIrqIf icss_g_main_0_bus_pr1_edc0_sync0_out_304_304_to_timesync_event_introuter_main_0_bus_in_16_16
Initial value:
= {
.lbase = 304,
.len = 1,
.rid = TISCI_DEV_TIMESYNC_INTRTR0,
.rbase = 16,
}

◆ icss_g_main_0_bus_pr1_edc0_sync1_out_305_305_to_timesync_event_introuter_main_0_bus_in_17_17

const struct Sciclient_rmIrqIf icss_g_main_0_bus_pr1_edc0_sync1_out_305_305_to_timesync_event_introuter_main_0_bus_in_17_17
Initial value:
= {
.lbase = 305,
.len = 1,
.rid = TISCI_DEV_TIMESYNC_INTRTR0,
.rbase = 17,
}

◆ icss_g_main_0_bus_pr1_edc1_sync0_out_306_306_to_timesync_event_introuter_main_0_bus_in_18_18

const struct Sciclient_rmIrqIf icss_g_main_0_bus_pr1_edc1_sync0_out_306_306_to_timesync_event_introuter_main_0_bus_in_18_18
Initial value:
= {
.lbase = 306,
.len = 1,
.rid = TISCI_DEV_TIMESYNC_INTRTR0,
.rbase = 18,
}

◆ icss_g_main_0_bus_pr1_edc1_sync1_out_307_307_to_timesync_event_introuter_main_0_bus_in_19_19

const struct Sciclient_rmIrqIf icss_g_main_0_bus_pr1_edc1_sync1_out_307_307_to_timesync_event_introuter_main_0_bus_in_19_19
Initial value:
= {
.lbase = 307,
.len = 1,
.rid = TISCI_DEV_TIMESYNC_INTRTR0,
.rbase = 19,
}

◆ icss_g_main_0_bus_pr1_host_intr_pend_294_301_to_main2mcu_lvl_introuter_main_0_bus_in_32_39

const struct Sciclient_rmIrqIf icss_g_main_0_bus_pr1_host_intr_pend_294_301_to_main2mcu_lvl_introuter_main_0_bus_in_32_39
Initial value:
= {
.lbase = 294,
.len = 8,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 32,
}

◆ tisci_if_PRU_ICSSG0

const struct Sciclient_rmIrqIf* const tisci_if_PRU_ICSSG0[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf icss_g_main_0_bus_pr1_edc1_sync1_out_307_307_to_timesync_event_introuter_main_0_bus_in_19_19
Definition: sciclient_irq_rm.c:1023
const struct Sciclient_rmIrqIf icss_g_main_0_bus_pr1_edc0_sync0_out_304_304_to_timesync_event_introuter_main_0_bus_in_16_16
Definition: sciclient_irq_rm.c:1005
const struct Sciclient_rmIrqIf icss_g_main_0_bus_pr1_host_intr_req_286_293_to_cmp_event_introuter_main_0_bus_in_8_15
Definition: sciclient_irq_rm.c:981
const struct Sciclient_rmIrqIf icss_g_main_0_bus_pr1_tx_sof_intr_req_302_303_to_main2mcu_pls_introuter_main_0_bus_in_22_23
Definition: sciclient_irq_rm.c:975
const struct Sciclient_rmIrqIf icss_g_main_0_bus_pr1_edc0_sync1_out_305_305_to_timesync_event_introuter_main_0_bus_in_17_17
Definition: sciclient_irq_rm.c:1011
const struct Sciclient_rmIrqIf icss_g_main_0_bus_pr1_edc1_sync0_out_306_306_to_timesync_event_introuter_main_0_bus_in_18_18
Definition: sciclient_irq_rm.c:1017
const struct Sciclient_rmIrqIf icss_g_main_0_bus_pr1_iep1_cmp_intr_req_256_261_to_cmp_event_introuter_main_0_bus_in_48_53
Definition: sciclient_irq_rm.c:993
const struct Sciclient_rmIrqIf icss_g_main_0_bus_pr1_iep0_cmp_intr_req_268_283_to_cmp_event_introuter_main_0_bus_in_32_47
Definition: sciclient_irq_rm.c:987
const struct Sciclient_rmIrqIf icss_g_main_0_bus_pr1_iep1_cmp_intr_req_6_15_to_cmp_event_introuter_main_0_bus_in_54_63
Definition: sciclient_irq_rm.c:999
const struct Sciclient_rmIrqIf icss_g_main_0_bus_pr1_rx_sof_intr_req_284_285_to_main2mcu_pls_introuter_main_0_bus_in_20_21
Definition: sciclient_irq_rm.c:969
const struct Sciclient_rmIrqIf icss_g_main_0_bus_pr1_host_intr_pend_294_301_to_main2mcu_lvl_introuter_main_0_bus_in_32_39
Definition: sciclient_irq_rm.c:1029

◆ tisci_irq_PRU_ICSSG0

const struct Sciclient_rmIrqNode tisci_irq_PRU_ICSSG0
static
Initial value:
= {
.id = TISCI_DEV_PRU_ICSSG0,
.n_if = 11,
.p_if = &tisci_if_PRU_ICSSG0[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_PRU_ICSSG0[]
Definition: sciclient_irq_rm.c:1035

◆ icss_g_main_1_bus_pr1_rx_sof_intr_req_284_285_to_main2mcu_pls_introuter_main_0_bus_in_24_25

const struct Sciclient_rmIrqIf icss_g_main_1_bus_pr1_rx_sof_intr_req_284_285_to_main2mcu_pls_introuter_main_0_bus_in_24_25
Initial value:
= {
.lbase = 284,
.len = 2,
.rid = TISCI_DEV_MAIN2MCU_PLS_INTRTR0,
.rbase = 24,
}

◆ icss_g_main_1_bus_pr1_tx_sof_intr_req_302_303_to_main2mcu_pls_introuter_main_0_bus_in_26_27

const struct Sciclient_rmIrqIf icss_g_main_1_bus_pr1_tx_sof_intr_req_302_303_to_main2mcu_pls_introuter_main_0_bus_in_26_27
Initial value:
= {
.lbase = 302,
.len = 2,
.rid = TISCI_DEV_MAIN2MCU_PLS_INTRTR0,
.rbase = 26,
}

◆ icss_g_main_1_bus_pr1_host_intr_req_286_293_to_cmp_event_introuter_main_0_bus_in_16_23

const struct Sciclient_rmIrqIf icss_g_main_1_bus_pr1_host_intr_req_286_293_to_cmp_event_introuter_main_0_bus_in_16_23
Initial value:
= {
.lbase = 286,
.len = 8,
.rid = TISCI_DEV_CMPEVENT_INTRTR0,
.rbase = 16,
}

◆ icss_g_main_1_bus_pr1_iep0_cmp_intr_req_268_283_to_cmp_event_introuter_main_0_bus_in_64_79

const struct Sciclient_rmIrqIf icss_g_main_1_bus_pr1_iep0_cmp_intr_req_268_283_to_cmp_event_introuter_main_0_bus_in_64_79
Initial value:
= {
.lbase = 268,
.len = 16,
.rid = TISCI_DEV_CMPEVENT_INTRTR0,
.rbase = 64,
}

◆ icss_g_main_1_bus_pr1_iep1_cmp_intr_req_256_261_to_cmp_event_introuter_main_0_bus_in_80_85

const struct Sciclient_rmIrqIf icss_g_main_1_bus_pr1_iep1_cmp_intr_req_256_261_to_cmp_event_introuter_main_0_bus_in_80_85
Initial value:
= {
.lbase = 256,
.len = 6,
.rid = TISCI_DEV_CMPEVENT_INTRTR0,
.rbase = 80,
}

◆ icss_g_main_1_bus_pr1_iep1_cmp_intr_req_6_15_to_cmp_event_introuter_main_0_bus_in_86_95

const struct Sciclient_rmIrqIf icss_g_main_1_bus_pr1_iep1_cmp_intr_req_6_15_to_cmp_event_introuter_main_0_bus_in_86_95
Initial value:
= {
.lbase = 6,
.len = 10,
.rid = TISCI_DEV_CMPEVENT_INTRTR0,
.rbase = 86,
}

◆ icss_g_main_1_bus_pr1_edc0_sync0_out_304_304_to_timesync_event_introuter_main_0_bus_in_20_20

const struct Sciclient_rmIrqIf icss_g_main_1_bus_pr1_edc0_sync0_out_304_304_to_timesync_event_introuter_main_0_bus_in_20_20
Initial value:
= {
.lbase = 304,
.len = 1,
.rid = TISCI_DEV_TIMESYNC_INTRTR0,
.rbase = 20,
}

◆ icss_g_main_1_bus_pr1_edc0_sync1_out_305_305_to_timesync_event_introuter_main_0_bus_in_21_21

const struct Sciclient_rmIrqIf icss_g_main_1_bus_pr1_edc0_sync1_out_305_305_to_timesync_event_introuter_main_0_bus_in_21_21
Initial value:
= {
.lbase = 305,
.len = 1,
.rid = TISCI_DEV_TIMESYNC_INTRTR0,
.rbase = 21,
}

◆ icss_g_main_1_bus_pr1_edc1_sync0_out_306_306_to_timesync_event_introuter_main_0_bus_in_22_22

const struct Sciclient_rmIrqIf icss_g_main_1_bus_pr1_edc1_sync0_out_306_306_to_timesync_event_introuter_main_0_bus_in_22_22
Initial value:
= {
.lbase = 306,
.len = 1,
.rid = TISCI_DEV_TIMESYNC_INTRTR0,
.rbase = 22,
}

◆ icss_g_main_1_bus_pr1_edc1_sync1_out_307_307_to_timesync_event_introuter_main_0_bus_in_23_23

const struct Sciclient_rmIrqIf icss_g_main_1_bus_pr1_edc1_sync1_out_307_307_to_timesync_event_introuter_main_0_bus_in_23_23
Initial value:
= {
.lbase = 307,
.len = 1,
.rid = TISCI_DEV_TIMESYNC_INTRTR0,
.rbase = 23,
}

◆ icss_g_main_1_bus_pr1_host_intr_pend_294_301_to_main2mcu_lvl_introuter_main_0_bus_in_40_47

const struct Sciclient_rmIrqIf icss_g_main_1_bus_pr1_host_intr_pend_294_301_to_main2mcu_lvl_introuter_main_0_bus_in_40_47
Initial value:
= {
.lbase = 294,
.len = 8,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 40,
}

◆ tisci_if_PRU_ICSSG1

const struct Sciclient_rmIrqIf* const tisci_if_PRU_ICSSG1[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf icss_g_main_1_bus_pr1_rx_sof_intr_req_284_285_to_main2mcu_pls_introuter_main_0_bus_in_24_25
Definition: sciclient_irq_rm.c:1055
const struct Sciclient_rmIrqIf icss_g_main_1_bus_pr1_iep0_cmp_intr_req_268_283_to_cmp_event_introuter_main_0_bus_in_64_79
Definition: sciclient_irq_rm.c:1073
const struct Sciclient_rmIrqIf icss_g_main_1_bus_pr1_host_intr_req_286_293_to_cmp_event_introuter_main_0_bus_in_16_23
Definition: sciclient_irq_rm.c:1067
const struct Sciclient_rmIrqIf icss_g_main_1_bus_pr1_iep1_cmp_intr_req_256_261_to_cmp_event_introuter_main_0_bus_in_80_85
Definition: sciclient_irq_rm.c:1079
const struct Sciclient_rmIrqIf icss_g_main_1_bus_pr1_edc1_sync0_out_306_306_to_timesync_event_introuter_main_0_bus_in_22_22
Definition: sciclient_irq_rm.c:1103
const struct Sciclient_rmIrqIf icss_g_main_1_bus_pr1_edc1_sync1_out_307_307_to_timesync_event_introuter_main_0_bus_in_23_23
Definition: sciclient_irq_rm.c:1109
const struct Sciclient_rmIrqIf icss_g_main_1_bus_pr1_edc0_sync1_out_305_305_to_timesync_event_introuter_main_0_bus_in_21_21
Definition: sciclient_irq_rm.c:1097
const struct Sciclient_rmIrqIf icss_g_main_1_bus_pr1_iep1_cmp_intr_req_6_15_to_cmp_event_introuter_main_0_bus_in_86_95
Definition: sciclient_irq_rm.c:1085
const struct Sciclient_rmIrqIf icss_g_main_1_bus_pr1_edc0_sync0_out_304_304_to_timesync_event_introuter_main_0_bus_in_20_20
Definition: sciclient_irq_rm.c:1091
const struct Sciclient_rmIrqIf icss_g_main_1_bus_pr1_host_intr_pend_294_301_to_main2mcu_lvl_introuter_main_0_bus_in_40_47
Definition: sciclient_irq_rm.c:1115
const struct Sciclient_rmIrqIf icss_g_main_1_bus_pr1_tx_sof_intr_req_302_303_to_main2mcu_pls_introuter_main_0_bus_in_26_27
Definition: sciclient_irq_rm.c:1061

◆ tisci_irq_PRU_ICSSG1

const struct Sciclient_rmIrqNode tisci_irq_PRU_ICSSG1
static
Initial value:
= {
.id = TISCI_DEV_PRU_ICSSG1,
.n_if = 11,
.p_if = &tisci_if_PRU_ICSSG1[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_PRU_ICSSG1[]
Definition: sciclient_irq_rm.c:1121

◆ icss_g_main_2_bus_pr1_rx_sof_intr_req_284_285_to_main2mcu_pls_introuter_main_0_bus_in_28_29

const struct Sciclient_rmIrqIf icss_g_main_2_bus_pr1_rx_sof_intr_req_284_285_to_main2mcu_pls_introuter_main_0_bus_in_28_29
Initial value:
= {
.lbase = 284,
.len = 2,
.rid = TISCI_DEV_MAIN2MCU_PLS_INTRTR0,
.rbase = 28,
}

◆ icss_g_main_2_bus_pr1_tx_sof_intr_req_302_303_to_main2mcu_pls_introuter_main_0_bus_in_30_31

const struct Sciclient_rmIrqIf icss_g_main_2_bus_pr1_tx_sof_intr_req_302_303_to_main2mcu_pls_introuter_main_0_bus_in_30_31
Initial value:
= {
.lbase = 302,
.len = 2,
.rid = TISCI_DEV_MAIN2MCU_PLS_INTRTR0,
.rbase = 30,
}

◆ icss_g_main_2_bus_pr1_host_intr_req_286_293_to_cmp_event_introuter_main_0_bus_in_24_31

const struct Sciclient_rmIrqIf icss_g_main_2_bus_pr1_host_intr_req_286_293_to_cmp_event_introuter_main_0_bus_in_24_31
Initial value:
= {
.lbase = 286,
.len = 8,
.rid = TISCI_DEV_CMPEVENT_INTRTR0,
.rbase = 24,
}

◆ icss_g_main_2_bus_pr1_iep0_cmp_intr_req_268_283_to_cmp_event_introuter_main_0_bus_in_96_111

const struct Sciclient_rmIrqIf icss_g_main_2_bus_pr1_iep0_cmp_intr_req_268_283_to_cmp_event_introuter_main_0_bus_in_96_111
Initial value:
= {
.lbase = 268,
.len = 16,
.rid = TISCI_DEV_CMPEVENT_INTRTR0,
.rbase = 96,
}

◆ icss_g_main_2_bus_pr1_iep1_cmp_intr_req_256_261_to_cmp_event_introuter_main_0_bus_in_112_117

const struct Sciclient_rmIrqIf icss_g_main_2_bus_pr1_iep1_cmp_intr_req_256_261_to_cmp_event_introuter_main_0_bus_in_112_117
Initial value:
= {
.lbase = 256,
.len = 6,
.rid = TISCI_DEV_CMPEVENT_INTRTR0,
.rbase = 112,
}

◆ icss_g_main_2_bus_pr1_iep1_cmp_intr_req_6_15_to_cmp_event_introuter_main_0_bus_in_118_127

const struct Sciclient_rmIrqIf icss_g_main_2_bus_pr1_iep1_cmp_intr_req_6_15_to_cmp_event_introuter_main_0_bus_in_118_127
Initial value:
= {
.lbase = 6,
.len = 10,
.rid = TISCI_DEV_CMPEVENT_INTRTR0,
.rbase = 118,
}

◆ icss_g_main_2_bus_pr1_edc0_sync0_out_304_304_to_timesync_event_introuter_main_0_bus_in_24_24

const struct Sciclient_rmIrqIf icss_g_main_2_bus_pr1_edc0_sync0_out_304_304_to_timesync_event_introuter_main_0_bus_in_24_24
Initial value:
= {
.lbase = 304,
.len = 1,
.rid = TISCI_DEV_TIMESYNC_INTRTR0,
.rbase = 24,
}

◆ icss_g_main_2_bus_pr1_edc0_sync1_out_305_305_to_timesync_event_introuter_main_0_bus_in_25_25

const struct Sciclient_rmIrqIf icss_g_main_2_bus_pr1_edc0_sync1_out_305_305_to_timesync_event_introuter_main_0_bus_in_25_25
Initial value:
= {
.lbase = 305,
.len = 1,
.rid = TISCI_DEV_TIMESYNC_INTRTR0,
.rbase = 25,
}

◆ icss_g_main_2_bus_pr1_edc1_sync0_out_306_306_to_timesync_event_introuter_main_0_bus_in_26_26

const struct Sciclient_rmIrqIf icss_g_main_2_bus_pr1_edc1_sync0_out_306_306_to_timesync_event_introuter_main_0_bus_in_26_26
Initial value:
= {
.lbase = 306,
.len = 1,
.rid = TISCI_DEV_TIMESYNC_INTRTR0,
.rbase = 26,
}

◆ icss_g_main_2_bus_pr1_edc1_sync1_out_307_307_to_timesync_event_introuter_main_0_bus_in_27_27

const struct Sciclient_rmIrqIf icss_g_main_2_bus_pr1_edc1_sync1_out_307_307_to_timesync_event_introuter_main_0_bus_in_27_27
Initial value:
= {
.lbase = 307,
.len = 1,
.rid = TISCI_DEV_TIMESYNC_INTRTR0,
.rbase = 27,
}

◆ icss_g_main_2_bus_pr1_host_intr_pend_294_301_to_main2mcu_lvl_introuter_main_0_bus_in_48_55

const struct Sciclient_rmIrqIf icss_g_main_2_bus_pr1_host_intr_pend_294_301_to_main2mcu_lvl_introuter_main_0_bus_in_48_55
Initial value:
= {
.lbase = 294,
.len = 8,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 48,
}

◆ tisci_if_PRU_ICSSG2

const struct Sciclient_rmIrqIf* const tisci_if_PRU_ICSSG2[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf icss_g_main_2_bus_pr1_edc0_sync1_out_305_305_to_timesync_event_introuter_main_0_bus_in_25_25
Definition: sciclient_irq_rm.c:1183
const struct Sciclient_rmIrqIf icss_g_main_2_bus_pr1_rx_sof_intr_req_284_285_to_main2mcu_pls_introuter_main_0_bus_in_28_29
Definition: sciclient_irq_rm.c:1141
const struct Sciclient_rmIrqIf icss_g_main_2_bus_pr1_edc1_sync1_out_307_307_to_timesync_event_introuter_main_0_bus_in_27_27
Definition: sciclient_irq_rm.c:1195
const struct Sciclient_rmIrqIf icss_g_main_2_bus_pr1_iep1_cmp_intr_req_6_15_to_cmp_event_introuter_main_0_bus_in_118_127
Definition: sciclient_irq_rm.c:1171
const struct Sciclient_rmIrqIf icss_g_main_2_bus_pr1_iep0_cmp_intr_req_268_283_to_cmp_event_introuter_main_0_bus_in_96_111
Definition: sciclient_irq_rm.c:1159
const struct Sciclient_rmIrqIf icss_g_main_2_bus_pr1_host_intr_pend_294_301_to_main2mcu_lvl_introuter_main_0_bus_in_48_55
Definition: sciclient_irq_rm.c:1201
const struct Sciclient_rmIrqIf icss_g_main_2_bus_pr1_tx_sof_intr_req_302_303_to_main2mcu_pls_introuter_main_0_bus_in_30_31
Definition: sciclient_irq_rm.c:1147
const struct Sciclient_rmIrqIf icss_g_main_2_bus_pr1_edc1_sync0_out_306_306_to_timesync_event_introuter_main_0_bus_in_26_26
Definition: sciclient_irq_rm.c:1189
const struct Sciclient_rmIrqIf icss_g_main_2_bus_pr1_edc0_sync0_out_304_304_to_timesync_event_introuter_main_0_bus_in_24_24
Definition: sciclient_irq_rm.c:1177
const struct Sciclient_rmIrqIf icss_g_main_2_bus_pr1_iep1_cmp_intr_req_256_261_to_cmp_event_introuter_main_0_bus_in_112_117
Definition: sciclient_irq_rm.c:1165
const struct Sciclient_rmIrqIf icss_g_main_2_bus_pr1_host_intr_req_286_293_to_cmp_event_introuter_main_0_bus_in_24_31
Definition: sciclient_irq_rm.c:1153

◆ tisci_irq_PRU_ICSSG2

const struct Sciclient_rmIrqNode tisci_irq_PRU_ICSSG2
static
Initial value:
= {
.id = TISCI_DEV_PRU_ICSSG2,
.n_if = 11,
.p_if = &tisci_if_PRU_ICSSG2[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_PRU_ICSSG2[]
Definition: sciclient_irq_rm.c:1207

◆ k3_boltv2_main_0_bus_gpu_irq_3_3_to_main2mcu_lvl_introuter_main_0_bus_in_56_56

const struct Sciclient_rmIrqIf k3_boltv2_main_0_bus_gpu_irq_3_3_to_main2mcu_lvl_introuter_main_0_bus_in_56_56
Initial value:
= {
.lbase = 3,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 56,
}

◆ k3_boltv2_main_0_bus_exp_intr_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_57_57

const struct Sciclient_rmIrqIf k3_boltv2_main_0_bus_exp_intr_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_57_57
Initial value:
= {
.lbase = 2,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 57,
}

◆ k3_boltv2_main_0_bus_init_err_4_4_to_main2mcu_lvl_introuter_main_0_bus_in_58_58

const struct Sciclient_rmIrqIf k3_boltv2_main_0_bus_init_err_4_4_to_main2mcu_lvl_introuter_main_0_bus_in_58_58
Initial value:
= {
.lbase = 4,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 58,
}

◆ k3_boltv2_main_0_bus_target_err_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_59_59

const struct Sciclient_rmIrqIf k3_boltv2_main_0_bus_target_err_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_59_59
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 59,
}

◆ tisci_if_GPU0

const struct Sciclient_rmIrqIf* const tisci_if_GPU0[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf k3_boltv2_main_0_bus_init_err_4_4_to_main2mcu_lvl_introuter_main_0_bus_in_58_58
Definition: sciclient_irq_rm.c:1239
const struct Sciclient_rmIrqIf k3_boltv2_main_0_bus_exp_intr_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_57_57
Definition: sciclient_irq_rm.c:1233
const struct Sciclient_rmIrqIf k3_boltv2_main_0_bus_target_err_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_59_59
Definition: sciclient_irq_rm.c:1245
const struct Sciclient_rmIrqIf k3_boltv2_main_0_bus_gpu_irq_3_3_to_main2mcu_lvl_introuter_main_0_bus_in_56_56
Definition: sciclient_irq_rm.c:1227

◆ tisci_irq_GPU0

const struct Sciclient_rmIrqNode tisci_irq_GPU0
static
Initial value:
= {
.id = TISCI_DEV_GPU0,
.n_if = 4,
.p_if = &tisci_if_GPU0[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_GPU0[]
Definition: sciclient_irq_rm.c:1251

◆ k3_cc_debug_cell_main_0_bus_aqcmpintr_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_13_13

const struct Sciclient_rmIrqIf k3_cc_debug_cell_main_0_bus_aqcmpintr_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_13_13
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 13,
}

◆ tisci_if_CCDEBUGSS0

const struct Sciclient_rmIrqIf* const tisci_if_CCDEBUGSS0[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf k3_cc_debug_cell_main_0_bus_aqcmpintr_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_13_13
Definition: sciclient_irq_rm.c:1264

◆ tisci_irq_CCDEBUGSS0

const struct Sciclient_rmIrqNode tisci_irq_CCDEBUGSS0
static
Initial value:
= {
.id = TISCI_DEV_CCDEBUGSS0,
.n_if = 1,
.p_if = &tisci_if_CCDEBUGSS0[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_CCDEBUGSS0[]
Definition: sciclient_irq_rm.c:1270

◆ k3_dss_ul_main_0_bus_dispc_intr_req_0_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_2_2

const struct Sciclient_rmIrqIf k3_dss_ul_main_0_bus_dispc_intr_req_0_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_2_2
Initial value:
= {
.lbase = 2,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 2,
}

◆ k3_dss_ul_main_0_bus_dispc_intr_req_1_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_3_3

const struct Sciclient_rmIrqIf k3_dss_ul_main_0_bus_dispc_intr_req_1_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_3_3
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 3,
}

◆ tisci_if_DSS0

const struct Sciclient_rmIrqIf* const tisci_if_DSS0[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf k3_dss_ul_main_0_bus_dispc_intr_req_0_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_2_2
Definition: sciclient_irq_rm.c:1280
const struct Sciclient_rmIrqIf k3_dss_ul_main_0_bus_dispc_intr_req_1_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_3_3
Definition: sciclient_irq_rm.c:1286

◆ tisci_irq_DSS0

const struct Sciclient_rmIrqNode tisci_irq_DSS0
static
Initial value:
= {
.id = TISCI_DEV_DSS0,
.n_if = 2,
.p_if = &tisci_if_DSS0[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_DSS0[]
Definition: sciclient_irq_rm.c:1292

◆ k3_main_debug_cell_main_0_bus_aqcmpintr_level_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_14_14

const struct Sciclient_rmIrqIf k3_main_debug_cell_main_0_bus_aqcmpintr_level_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_14_14
Initial value:
= {
.lbase = 2,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 14,
}

◆ k3_main_debug_cell_main_0_bus_ctm_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_15_15

const struct Sciclient_rmIrqIf k3_main_debug_cell_main_0_bus_ctm_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_15_15
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 15,
}

◆ tisci_if_DEBUGSS0

const struct Sciclient_rmIrqIf* const tisci_if_DEBUGSS0[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf k3_main_debug_cell_main_0_bus_ctm_level_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_15_15
Definition: sciclient_irq_rm.c:1309
const struct Sciclient_rmIrqIf k3_main_debug_cell_main_0_bus_aqcmpintr_level_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_14_14
Definition: sciclient_irq_rm.c:1303

◆ tisci_irq_DEBUGSS0

const struct Sciclient_rmIrqNode tisci_irq_DEBUGSS0
static
Initial value:
= {
.id = TISCI_DEV_DEBUGSS0,
.n_if = 2,
.p_if = &tisci_if_DEBUGSS0[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_DEBUGSS0[]
Definition: sciclient_irq_rm.c:1315

◆ m4_main_cbass_main_0_bus_LPSC_per_common_err_intr_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_172_172

const struct Sciclient_rmIrqIf m4_main_cbass_main_0_bus_LPSC_per_common_err_intr_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_172_172
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 172,
}

◆ tisci_if_CBASS0

const struct Sciclient_rmIrqIf* const tisci_if_CBASS0[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf m4_main_cbass_main_0_bus_LPSC_per_common_err_intr_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_172_172
Definition: sciclient_irq_rm.c:1326

◆ tisci_irq_CBASS0

const struct Sciclient_rmIrqNode tisci_irq_CBASS0
static
Initial value:
= {
.id = TISCI_DEV_CBASS0,
.n_if = 1,
.p_if = &tisci_if_CBASS0[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_CBASS0[]
Definition: sciclient_irq_rm.c:1332

◆ m4_main_dbg_cbass_main_0_bus_LPSC_main_debug_err_intr_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_173_173

const struct Sciclient_rmIrqIf m4_main_dbg_cbass_main_0_bus_LPSC_main_debug_err_intr_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_173_173
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 173,
}

◆ tisci_if_CBASS_DEBUG0

const struct Sciclient_rmIrqIf* const tisci_if_CBASS_DEBUG0[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf m4_main_dbg_cbass_main_0_bus_LPSC_main_debug_err_intr_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_173_173
Definition: sciclient_irq_rm.c:1342

◆ tisci_irq_CBASS_DEBUG0

const struct Sciclient_rmIrqNode tisci_irq_CBASS_DEBUG0
static
Initial value:
= {
.id = TISCI_DEV_CBASS_DEBUG0,
.n_if = 1,
.p_if = &tisci_if_CBASS_DEBUG0[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_CBASS_DEBUG0[]
Definition: sciclient_irq_rm.c:1348

◆ m4_main_fw_cbass_main_0_bus_LPSC_main_infra_err_intr_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_174_174

const struct Sciclient_rmIrqIf m4_main_fw_cbass_main_0_bus_LPSC_main_infra_err_intr_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_174_174
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 174,
}

◆ tisci_if_CBASS_FW0

const struct Sciclient_rmIrqIf* const tisci_if_CBASS_FW0[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf m4_main_fw_cbass_main_0_bus_LPSC_main_infra_err_intr_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_174_174
Definition: sciclient_irq_rm.c:1358

◆ tisci_irq_CBASS_FW0

const struct Sciclient_rmIrqNode tisci_irq_CBASS_FW0
static
Initial value:
= {
.id = TISCI_DEV_CBASS_FW0,
.n_if = 1,
.p_if = &tisci_if_CBASS_FW0[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_CBASS_FW0[]
Definition: sciclient_irq_rm.c:1364

◆ m4_main_infra_cbass_main_0_bus_LPSC_main_infra_err_intr_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_175_175

const struct Sciclient_rmIrqIf m4_main_infra_cbass_main_0_bus_LPSC_main_infra_err_intr_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_175_175
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 175,
}

◆ tisci_if_CBASS_INFRA0

const struct Sciclient_rmIrqIf* const tisci_if_CBASS_INFRA0[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf m4_main_infra_cbass_main_0_bus_LPSC_main_infra_err_intr_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_175_175
Definition: sciclient_irq_rm.c:1374

◆ tisci_irq_CBASS_INFRA0

const struct Sciclient_rmIrqNode tisci_irq_CBASS_INFRA0
static
Initial value:
= {
.id = TISCI_DEV_CBASS_INFRA0,
.n_if = 1,
.p_if = &tisci_if_CBASS_INFRA0[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_CBASS_INFRA0[]
Definition: sciclient_irq_rm.c:1380

◆ main2mcu_lvl_introuter_main_0_bus_outl_0_63_to_mcu_armss0_cpu0_bus_intr_160_223

const struct Sciclient_rmIrqIf main2mcu_lvl_introuter_main_0_bus_outl_0_63_to_mcu_armss0_cpu0_bus_intr_160_223
Initial value:
= {
.lbase = 0,
.len = 64,
.rid = TISCI_DEV_MCU_ARMSS0_CPU0,
.rbase = 160,
}

◆ main2mcu_lvl_introuter_main_0_bus_outl_0_63_to_mcu_armss0_cpu1_bus_intr_160_223

const struct Sciclient_rmIrqIf main2mcu_lvl_introuter_main_0_bus_outl_0_63_to_mcu_armss0_cpu1_bus_intr_160_223
Initial value:
= {
.lbase = 0,
.len = 64,
.rid = TISCI_DEV_MCU_ARMSS0_CPU1,
.rbase = 160,
}

◆ tisci_if_MAIN2MCU_LVL_INTRTR0

const struct Sciclient_rmIrqIf* const tisci_if_MAIN2MCU_LVL_INTRTR0[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf main2mcu_lvl_introuter_main_0_bus_outl_0_63_to_mcu_armss0_cpu1_bus_intr_160_223
Definition: sciclient_irq_rm.c:1396
const struct Sciclient_rmIrqIf main2mcu_lvl_introuter_main_0_bus_outl_0_63_to_mcu_armss0_cpu0_bus_intr_160_223
Definition: sciclient_irq_rm.c:1390

◆ tisci_irq_MAIN2MCU_LVL_INTRTR0

const struct Sciclient_rmIrqNode tisci_irq_MAIN2MCU_LVL_INTRTR0
static
Initial value:
= {
.id = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.n_if = 2,
}
const struct Sciclient_rmIrqIf *const tisci_if_MAIN2MCU_LVL_INTRTR0[]
Definition: sciclient_irq_rm.c:1402

◆ main2mcu_pls_introuter_main_0_bus_outp_0_47_to_mcu_armss0_cpu1_bus_intr_224_271

const struct Sciclient_rmIrqIf main2mcu_pls_introuter_main_0_bus_outp_0_47_to_mcu_armss0_cpu1_bus_intr_224_271
Initial value:
= {
.lbase = 0,
.len = 48,
.rid = TISCI_DEV_MCU_ARMSS0_CPU1,
.rbase = 224,
}

◆ main2mcu_pls_introuter_main_0_bus_outp_0_47_to_mcu_armss0_cpu0_bus_intr_224_271

const struct Sciclient_rmIrqIf main2mcu_pls_introuter_main_0_bus_outp_0_47_to_mcu_armss0_cpu0_bus_intr_224_271
Initial value:
= {
.lbase = 0,
.len = 48,
.rid = TISCI_DEV_MCU_ARMSS0_CPU0,
.rbase = 224,
}

◆ tisci_if_MAIN2MCU_PLS_INTRTR0

const struct Sciclient_rmIrqIf* const tisci_if_MAIN2MCU_PLS_INTRTR0[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf main2mcu_pls_introuter_main_0_bus_outp_0_47_to_mcu_armss0_cpu0_bus_intr_224_271
Definition: sciclient_irq_rm.c:1419
const struct Sciclient_rmIrqIf main2mcu_pls_introuter_main_0_bus_outp_0_47_to_mcu_armss0_cpu1_bus_intr_224_271
Definition: sciclient_irq_rm.c:1413

◆ tisci_irq_MAIN2MCU_PLS_INTRTR0

const struct Sciclient_rmIrqNode tisci_irq_MAIN2MCU_PLS_INTRTR0
static
Initial value:
= {
.id = TISCI_DEV_MAIN2MCU_PLS_INTRTR0,
.n_if = 2,
}
const struct Sciclient_rmIrqIf *const tisci_if_MAIN2MCU_PLS_INTRTR0[]
Definition: sciclient_irq_rm.c:1425

◆ main_ctrl_mmr_main_0_bus_access_err_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_6_6

const struct Sciclient_rmIrqIf main_ctrl_mmr_main_0_bus_access_err_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_6_6
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 6,
}

◆ tisci_if_CTRL_MMR0

const struct Sciclient_rmIrqIf* const tisci_if_CTRL_MMR0[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf main_ctrl_mmr_main_0_bus_access_err_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_6_6
Definition: sciclient_irq_rm.c:1436

◆ tisci_irq_CTRL_MMR0

const struct Sciclient_rmIrqNode tisci_irq_CTRL_MMR0
static
Initial value:
= {
.id = TISCI_DEV_CTRL_MMR0,
.n_if = 1,
.p_if = &tisci_if_CTRL_MMR0[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_CTRL_MMR0[]
Definition: sciclient_irq_rm.c:1442

◆ main_gpiomux_introuter_main_0_bus_outp_20_25_to_icss_g_main_1_bus_pr1_iep0_cap_intr_req_262_267

const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_20_25_to_icss_g_main_1_bus_pr1_iep0_cap_intr_req_262_267
Initial value:
= {
.lbase = 20,
.len = 6,
.rid = TISCI_DEV_PRU_ICSSG1,
.rbase = 262,
}

◆ main_gpiomux_introuter_main_0_bus_outp_26_31_to_icss_g_main_1_bus_pr1_iep1_cap_intr_req_0_5

const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_26_31_to_icss_g_main_1_bus_pr1_iep1_cap_intr_req_0_5
Initial value:
= {
.lbase = 26,
.len = 6,
.rid = TISCI_DEV_PRU_ICSSG1,
.rbase = 0,
}

◆ main_gpiomux_introuter_main_0_bus_outp_24_31_to_icss_g_main_1_bus_pr1_slv_intr_88_95

const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_24_31_to_icss_g_main_1_bus_pr1_slv_intr_88_95
Initial value:
= {
.lbase = 24,
.len = 8,
.rid = TISCI_DEV_PRU_ICSSG1,
.rbase = 88,
}

◆ main_gpiomux_introuter_main_0_bus_outp_20_25_to_icss_g_main_0_bus_pr1_iep0_cap_intr_req_262_267

const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_20_25_to_icss_g_main_0_bus_pr1_iep0_cap_intr_req_262_267
Initial value:
= {
.lbase = 20,
.len = 6,
.rid = TISCI_DEV_PRU_ICSSG0,
.rbase = 262,
}

◆ main_gpiomux_introuter_main_0_bus_outp_26_31_to_icss_g_main_0_bus_pr1_iep1_cap_intr_req_0_5

const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_26_31_to_icss_g_main_0_bus_pr1_iep1_cap_intr_req_0_5
Initial value:
= {
.lbase = 26,
.len = 6,
.rid = TISCI_DEV_PRU_ICSSG0,
.rbase = 0,
}

◆ main_gpiomux_introuter_main_0_bus_outp_24_31_to_icss_g_main_0_bus_pr1_slv_intr_88_95

const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_24_31_to_icss_g_main_0_bus_pr1_slv_intr_88_95
Initial value:
= {
.lbase = 24,
.len = 8,
.rid = TISCI_DEV_PRU_ICSSG0,
.rbase = 88,
}

◆ main_gpiomux_introuter_main_0_bus_outp_0_31_to_gic500ss_main_0_bus_spi_392_423

const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_0_31_to_gic500ss_main_0_bus_spi_392_423
Initial value:
= {
.lbase = 0,
.len = 32,
.rid = TISCI_DEV_GIC0,
.rbase = 392,
}

◆ main_gpiomux_introuter_main_0_bus_outp_20_25_to_icss_g_main_2_bus_pr1_iep0_cap_intr_req_262_267

const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_20_25_to_icss_g_main_2_bus_pr1_iep0_cap_intr_req_262_267
Initial value:
= {
.lbase = 20,
.len = 6,
.rid = TISCI_DEV_PRU_ICSSG2,
.rbase = 262,
}

◆ main_gpiomux_introuter_main_0_bus_outp_26_31_to_icss_g_main_2_bus_pr1_iep1_cap_intr_req_0_5

const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_26_31_to_icss_g_main_2_bus_pr1_iep1_cap_intr_req_0_5
Initial value:
= {
.lbase = 26,
.len = 6,
.rid = TISCI_DEV_PRU_ICSSG2,
.rbase = 0,
}

◆ main_gpiomux_introuter_main_0_bus_outp_24_31_to_icss_g_main_2_bus_pr1_slv_intr_88_95

const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_24_31_to_icss_g_main_2_bus_pr1_slv_intr_88_95
Initial value:
= {
.lbase = 24,
.len = 8,
.rid = TISCI_DEV_PRU_ICSSG2,
.rbase = 88,
}

◆ main_gpiomux_introuter_main_0_bus_outp_0_7_to_esm_main_main_0_bus_esm_pls_event0_512_519

const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_0_7_to_esm_main_main_0_bus_esm_pls_event0_512_519
Initial value:
= {
.lbase = 0,
.len = 8,
.rid = TISCI_DEV_ESM0,
.rbase = 512,
}

◆ main_gpiomux_introuter_main_0_bus_outp_0_7_to_esm_main_main_0_bus_esm_pls_event1_520_527

const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_0_7_to_esm_main_main_0_bus_esm_pls_event1_520_527
Initial value:
= {
.lbase = 0,
.len = 8,
.rid = TISCI_DEV_ESM0,
.rbase = 520,
}

◆ main_gpiomux_introuter_main_0_bus_outp_0_7_to_esm_main_main_0_bus_esm_pls_event2_248_255

const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_0_7_to_esm_main_main_0_bus_esm_pls_event2_248_255
Initial value:
= {
.lbase = 0,
.len = 8,
.rid = TISCI_DEV_ESM0,
.rbase = 248,
}

◆ tisci_if_GPIOMUX_INTRTR0

const struct Sciclient_rmIrqIf* const tisci_if_GPIOMUX_INTRTR0[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_0_7_to_esm_main_main_0_bus_esm_pls_event2_248_255
Definition: sciclient_irq_rm.c:1524
const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_24_31_to_icss_g_main_2_bus_pr1_slv_intr_88_95
Definition: sciclient_irq_rm.c:1506
const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_0_31_to_gic500ss_main_0_bus_spi_392_423
Definition: sciclient_irq_rm.c:1488
const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_24_31_to_icss_g_main_1_bus_pr1_slv_intr_88_95
Definition: sciclient_irq_rm.c:1464
const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_20_25_to_icss_g_main_2_bus_pr1_iep0_cap_intr_req_262_267
Definition: sciclient_irq_rm.c:1494
const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_26_31_to_icss_g_main_2_bus_pr1_iep1_cap_intr_req_0_5
Definition: sciclient_irq_rm.c:1500
const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_20_25_to_icss_g_main_0_bus_pr1_iep0_cap_intr_req_262_267
Definition: sciclient_irq_rm.c:1470
const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_0_7_to_esm_main_main_0_bus_esm_pls_event0_512_519
Definition: sciclient_irq_rm.c:1512
const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_24_31_to_icss_g_main_0_bus_pr1_slv_intr_88_95
Definition: sciclient_irq_rm.c:1482
const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_0_7_to_esm_main_main_0_bus_esm_pls_event1_520_527
Definition: sciclient_irq_rm.c:1518
const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_26_31_to_icss_g_main_1_bus_pr1_iep1_cap_intr_req_0_5
Definition: sciclient_irq_rm.c:1458
const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_20_25_to_icss_g_main_1_bus_pr1_iep0_cap_intr_req_262_267
Definition: sciclient_irq_rm.c:1452
const struct Sciclient_rmIrqIf main_gpiomux_introuter_main_0_bus_outp_26_31_to_icss_g_main_0_bus_pr1_iep1_cap_intr_req_0_5
Definition: sciclient_irq_rm.c:1476

◆ tisci_irq_GPIOMUX_INTRTR0

const struct Sciclient_rmIrqNode tisci_irq_GPIOMUX_INTRTR0
static
Initial value:
= {
.id = TISCI_DEV_GPIOMUX_INTRTR0,
.n_if = 13,
}
const struct Sciclient_rmIrqIf *const tisci_if_GPIOMUX_INTRTR0[]
Definition: sciclient_irq_rm.c:1530

◆ mcasp_main_0_bus_xmit_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_16_16

const struct Sciclient_rmIrqIf mcasp_main_0_bus_xmit_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_16_16
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 16,
}

◆ mcasp_main_0_bus_rec_intr_pend_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_17_17

const struct Sciclient_rmIrqIf mcasp_main_0_bus_rec_intr_pend_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_17_17
Initial value:
= {
.lbase = 2,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 17,
}

◆ tisci_if_MCASP0

const struct Sciclient_rmIrqIf* const tisci_if_MCASP0[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf mcasp_main_0_bus_xmit_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_16_16
Definition: sciclient_irq_rm.c:1552
const struct Sciclient_rmIrqIf mcasp_main_0_bus_rec_intr_pend_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_17_17
Definition: sciclient_irq_rm.c:1558

◆ tisci_irq_MCASP0

const struct Sciclient_rmIrqNode tisci_irq_MCASP0
static
Initial value:
= {
.id = TISCI_DEV_MCASP0,
.n_if = 2,
.p_if = &tisci_if_MCASP0[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_MCASP0[]
Definition: sciclient_irq_rm.c:1564

◆ mcasp_main_1_bus_xmit_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_18_18

const struct Sciclient_rmIrqIf mcasp_main_1_bus_xmit_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_18_18
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 18,
}

◆ mcasp_main_1_bus_rec_intr_pend_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_19_19

const struct Sciclient_rmIrqIf mcasp_main_1_bus_rec_intr_pend_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_19_19
Initial value:
= {
.lbase = 2,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 19,
}

◆ tisci_if_MCASP1

const struct Sciclient_rmIrqIf* const tisci_if_MCASP1[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf mcasp_main_1_bus_rec_intr_pend_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_19_19
Definition: sciclient_irq_rm.c:1581
const struct Sciclient_rmIrqIf mcasp_main_1_bus_xmit_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_18_18
Definition: sciclient_irq_rm.c:1575

◆ tisci_irq_MCASP1

const struct Sciclient_rmIrqNode tisci_irq_MCASP1
static
Initial value:
= {
.id = TISCI_DEV_MCASP1,
.n_if = 2,
.p_if = &tisci_if_MCASP1[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_MCASP1[]
Definition: sciclient_irq_rm.c:1587

◆ mcasp_main_2_bus_xmit_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_20_20

const struct Sciclient_rmIrqIf mcasp_main_2_bus_xmit_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_20_20
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 20,
}

◆ mcasp_main_2_bus_rec_intr_pend_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_21_21

const struct Sciclient_rmIrqIf mcasp_main_2_bus_rec_intr_pend_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_21_21
Initial value:
= {
.lbase = 2,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 21,
}

◆ tisci_if_MCASP2

const struct Sciclient_rmIrqIf* const tisci_if_MCASP2[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf mcasp_main_2_bus_rec_intr_pend_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_21_21
Definition: sciclient_irq_rm.c:1604
const struct Sciclient_rmIrqIf mcasp_main_2_bus_xmit_intr_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_20_20
Definition: sciclient_irq_rm.c:1598

◆ tisci_irq_MCASP2

const struct Sciclient_rmIrqNode tisci_irq_MCASP2
static
Initial value:
= {
.id = TISCI_DEV_MCASP2,
.n_if = 2,
.p_if = &tisci_if_MCASP2[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_MCASP2[]
Definition: sciclient_irq_rm.c:1610

◆ mshsi2c_main_0_bus_pointrpend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_100_100

const struct Sciclient_rmIrqIf mshsi2c_main_0_bus_pointrpend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_100_100
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 100,
}

◆ tisci_if_I2C0

const struct Sciclient_rmIrqIf* const tisci_if_I2C0[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf mshsi2c_main_0_bus_pointrpend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_100_100
Definition: sciclient_irq_rm.c:1621

◆ tisci_irq_I2C0

const struct Sciclient_rmIrqNode tisci_irq_I2C0
static
Initial value:
= {
.id = TISCI_DEV_I2C0,
.n_if = 1,
.p_if = &tisci_if_I2C0[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_I2C0[]
Definition: sciclient_irq_rm.c:1627

◆ mshsi2c_main_1_bus_pointrpend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_101_101

const struct Sciclient_rmIrqIf mshsi2c_main_1_bus_pointrpend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_101_101
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 101,
}

◆ tisci_if_I2C1

const struct Sciclient_rmIrqIf* const tisci_if_I2C1[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf mshsi2c_main_1_bus_pointrpend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_101_101
Definition: sciclient_irq_rm.c:1637

◆ tisci_irq_I2C1

const struct Sciclient_rmIrqNode tisci_irq_I2C1
static
Initial value:
= {
.id = TISCI_DEV_I2C1,
.n_if = 1,
.p_if = &tisci_if_I2C1[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_I2C1[]
Definition: sciclient_irq_rm.c:1643

◆ mshsi2c_main_2_bus_pointrpend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_102_102

const struct Sciclient_rmIrqIf mshsi2c_main_2_bus_pointrpend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_102_102
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 102,
}

◆ tisci_if_I2C2

const struct Sciclient_rmIrqIf* const tisci_if_I2C2[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf mshsi2c_main_2_bus_pointrpend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_102_102
Definition: sciclient_irq_rm.c:1653

◆ tisci_irq_I2C2

const struct Sciclient_rmIrqNode tisci_irq_I2C2
static
Initial value:
= {
.id = TISCI_DEV_I2C2,
.n_if = 1,
.p_if = &tisci_if_I2C2[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_I2C2[]
Definition: sciclient_irq_rm.c:1659

◆ mshsi2c_main_3_bus_pointrpend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_103_103

const struct Sciclient_rmIrqIf mshsi2c_main_3_bus_pointrpend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_103_103
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 103,
}

◆ tisci_if_I2C3

const struct Sciclient_rmIrqIf* const tisci_if_I2C3[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf mshsi2c_main_3_bus_pointrpend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_103_103
Definition: sciclient_irq_rm.c:1669

◆ tisci_irq_I2C3

const struct Sciclient_rmIrqNode tisci_irq_I2C3
static
Initial value:
= {
.id = TISCI_DEV_I2C3,
.n_if = 1,
.p_if = &tisci_if_I2C3[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_I2C3[]
Definition: sciclient_irq_rm.c:1675

◆ navss256l_main_0_bus_cpts0_comp_9_9_to_cmp_event_introuter_main_0_bus_in_4_4

const struct Sciclient_rmIrqIf navss256l_main_0_bus_cpts0_comp_9_9_to_cmp_event_introuter_main_0_bus_in_4_4
Initial value:
= {
.lbase = 9,
.len = 1,
.rid = TISCI_DEV_CMPEVENT_INTRTR0,
.rbase = 4,
}

◆ navss256l_main_0_bus_cpts0_genf0_10_10_to_timesync_event_introuter_main_0_bus_in_4_4

const struct Sciclient_rmIrqIf navss256l_main_0_bus_cpts0_genf0_10_10_to_timesync_event_introuter_main_0_bus_in_4_4
Initial value:
= {
.lbase = 10,
.len = 1,
.rid = TISCI_DEV_TIMESYNC_INTRTR0,
.rbase = 4,
}

◆ navss256l_main_0_bus_cpts0_genf1_11_11_to_timesync_event_introuter_main_0_bus_in_5_5

const struct Sciclient_rmIrqIf navss256l_main_0_bus_cpts0_genf1_11_11_to_timesync_event_introuter_main_0_bus_in_5_5
Initial value:
= {
.lbase = 11,
.len = 1,
.rid = TISCI_DEV_TIMESYNC_INTRTR0,
.rbase = 5,
}

◆ navss256l_main_0_bus_cpts0_genf2_12_12_to_timesync_event_introuter_main_0_bus_in_6_6

const struct Sciclient_rmIrqIf navss256l_main_0_bus_cpts0_genf2_12_12_to_timesync_event_introuter_main_0_bus_in_6_6
Initial value:
= {
.lbase = 12,
.len = 1,
.rid = TISCI_DEV_TIMESYNC_INTRTR0,
.rbase = 6,
}

◆ navss256l_main_0_bus_cpts0_genf3_13_13_to_timesync_event_introuter_main_0_bus_in_7_7

const struct Sciclient_rmIrqIf navss256l_main_0_bus_cpts0_genf3_13_13_to_timesync_event_introuter_main_0_bus_in_7_7
Initial value:
= {
.lbase = 13,
.len = 1,
.rid = TISCI_DEV_TIMESYNC_INTRTR0,
.rbase = 7,
}

◆ navss256l_main_0_bus_cpts0_genf4_14_14_to_timesync_event_introuter_main_0_bus_in_8_8

const struct Sciclient_rmIrqIf navss256l_main_0_bus_cpts0_genf4_14_14_to_timesync_event_introuter_main_0_bus_in_8_8
Initial value:
= {
.lbase = 14,
.len = 1,
.rid = TISCI_DEV_TIMESYNC_INTRTR0,
.rbase = 8,
}

◆ navss256l_main_0_bus_cpts0_genf5_15_15_to_timesync_event_introuter_main_0_bus_in_9_9

const struct Sciclient_rmIrqIf navss256l_main_0_bus_cpts0_genf5_15_15_to_timesync_event_introuter_main_0_bus_in_9_9
Initial value:
= {
.lbase = 15,
.len = 1,
.rid = TISCI_DEV_TIMESYNC_INTRTR0,
.rbase = 9,
}

◆ navss256l_main_0_bus_cpts0_sync_16_16_to_timesync_event_introuter_main_0_bus_in_30_30

const struct Sciclient_rmIrqIf navss256l_main_0_bus_cpts0_sync_16_16_to_timesync_event_introuter_main_0_bus_in_30_30
Initial value:
= {
.lbase = 16,
.len = 1,
.rid = TISCI_DEV_TIMESYNC_INTRTR0,
.rbase = 30,
}

◆ tisci_if_NAVSS0

const struct Sciclient_rmIrqIf* const tisci_if_NAVSS0[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf navss256l_main_0_bus_cpts0_genf1_11_11_to_timesync_event_introuter_main_0_bus_in_5_5
Definition: sciclient_irq_rm.c:1697
const struct Sciclient_rmIrqIf navss256l_main_0_bus_cpts0_comp_9_9_to_cmp_event_introuter_main_0_bus_in_4_4
Definition: sciclient_irq_rm.c:1685
const struct Sciclient_rmIrqIf navss256l_main_0_bus_cpts0_genf4_14_14_to_timesync_event_introuter_main_0_bus_in_8_8
Definition: sciclient_irq_rm.c:1715
const struct Sciclient_rmIrqIf navss256l_main_0_bus_cpts0_genf0_10_10_to_timesync_event_introuter_main_0_bus_in_4_4
Definition: sciclient_irq_rm.c:1691
const struct Sciclient_rmIrqIf navss256l_main_0_bus_cpts0_genf2_12_12_to_timesync_event_introuter_main_0_bus_in_6_6
Definition: sciclient_irq_rm.c:1703
const struct Sciclient_rmIrqIf navss256l_main_0_bus_cpts0_genf3_13_13_to_timesync_event_introuter_main_0_bus_in_7_7
Definition: sciclient_irq_rm.c:1709
const struct Sciclient_rmIrqIf navss256l_main_0_bus_cpts0_genf5_15_15_to_timesync_event_introuter_main_0_bus_in_9_9
Definition: sciclient_irq_rm.c:1721
const struct Sciclient_rmIrqIf navss256l_main_0_bus_cpts0_sync_16_16_to_timesync_event_introuter_main_0_bus_in_30_30
Definition: sciclient_irq_rm.c:1727

◆ tisci_irq_NAVSS0

const struct Sciclient_rmIrqNode tisci_irq_NAVSS0
static
Initial value:
= {
.id = TISCI_DEV_NAVSS0,
.n_if = 8,
.p_if = &tisci_if_NAVSS0[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_NAVSS0[]
Definition: sciclient_irq_rm.c:1733

◆ pcie_g3x2_main_0_bus_pcie_cpts_comp_19_19_to_cmp_event_introuter_main_0_bus_in_5_5

const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie_cpts_comp_19_19_to_cmp_event_introuter_main_0_bus_in_5_5
Initial value:
= {
.lbase = 19,
.len = 1,
.rid = TISCI_DEV_CMPEVENT_INTRTR0,
.rbase = 5,
}

◆ pcie_g3x2_main_0_bus_pcie_cpts_genf0_20_20_to_timesync_event_introuter_main_0_bus_in_10_10

const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie_cpts_genf0_20_20_to_timesync_event_introuter_main_0_bus_in_10_10
Initial value:
= {
.lbase = 20,
.len = 1,
.rid = TISCI_DEV_TIMESYNC_INTRTR0,
.rbase = 10,
}

◆ pcie_g3x2_main_0_bus_pcie_cpts_hw1_push_17_17_to_timesync_event_introuter_main_0_bus_in_14_14

const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie_cpts_hw1_push_17_17_to_timesync_event_introuter_main_0_bus_in_14_14
Initial value:
= {
.lbase = 17,
.len = 1,
.rid = TISCI_DEV_TIMESYNC_INTRTR0,
.rbase = 14,
}

◆ pcie_g3x2_main_0_bus_pcie_cpts_sync_21_21_to_timesync_event_introuter_main_0_bus_in_28_28

const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie_cpts_sync_21_21_to_timesync_event_introuter_main_0_bus_in_28_28
Initial value:
= {
.lbase = 21,
.len = 1,
.rid = TISCI_DEV_TIMESYNC_INTRTR0,
.rbase = 28,
}

◆ pcie_g3x2_main_0_bus_pcie0_pend_13_13_to_main2mcu_lvl_introuter_main_0_bus_in_64_64

const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie0_pend_13_13_to_main2mcu_lvl_introuter_main_0_bus_in_64_64
Initial value:
= {
.lbase = 13,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 64,
}

◆ pcie_g3x2_main_0_bus_pcie1_pend_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_65_65

const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie1_pend_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_65_65
Initial value:
= {
.lbase = 2,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 65,
}

◆ pcie_g3x2_main_0_bus_pcie2_pend_7_7_to_main2mcu_lvl_introuter_main_0_bus_in_66_66

const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie2_pend_7_7_to_main2mcu_lvl_introuter_main_0_bus_in_66_66
Initial value:
= {
.lbase = 7,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 66,
}

◆ pcie_g3x2_main_0_bus_pcie3_pend_4_4_to_main2mcu_lvl_introuter_main_0_bus_in_67_67

const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie3_pend_4_4_to_main2mcu_lvl_introuter_main_0_bus_in_67_67
Initial value:
= {
.lbase = 4,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 67,
}

◆ pcie_g3x2_main_0_bus_pcie4_pend_5_5_to_main2mcu_lvl_introuter_main_0_bus_in_68_68

const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie4_pend_5_5_to_main2mcu_lvl_introuter_main_0_bus_in_68_68
Initial value:
= {
.lbase = 5,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 68,
}

◆ pcie_g3x2_main_0_bus_pcie5_pend_3_3_to_main2mcu_lvl_introuter_main_0_bus_in_69_69

const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie5_pend_3_3_to_main2mcu_lvl_introuter_main_0_bus_in_69_69
Initial value:
= {
.lbase = 3,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 69,
}

◆ pcie_g3x2_main_0_bus_pcie6_pend_11_11_to_main2mcu_lvl_introuter_main_0_bus_in_70_70

const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie6_pend_11_11_to_main2mcu_lvl_introuter_main_0_bus_in_70_70
Initial value:
= {
.lbase = 11,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 70,
}

◆ pcie_g3x2_main_0_bus_pcie7_pend_8_8_to_main2mcu_lvl_introuter_main_0_bus_in_71_71

const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie7_pend_8_8_to_main2mcu_lvl_introuter_main_0_bus_in_71_71
Initial value:
= {
.lbase = 8,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 71,
}

◆ pcie_g3x2_main_0_bus_pcie8_pend_9_9_to_main2mcu_lvl_introuter_main_0_bus_in_72_72

const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie8_pend_9_9_to_main2mcu_lvl_introuter_main_0_bus_in_72_72
Initial value:
= {
.lbase = 9,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 72,
}

◆ pcie_g3x2_main_0_bus_pcie9_pend_16_16_to_main2mcu_lvl_introuter_main_0_bus_in_73_73

const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie9_pend_16_16_to_main2mcu_lvl_introuter_main_0_bus_in_73_73
Initial value:
= {
.lbase = 16,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 73,
}

◆ pcie_g3x2_main_0_bus_pcie10_pend_15_15_to_main2mcu_lvl_introuter_main_0_bus_in_74_74

const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie10_pend_15_15_to_main2mcu_lvl_introuter_main_0_bus_in_74_74
Initial value:
= {
.lbase = 15,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 74,
}

◆ pcie_g3x2_main_0_bus_pcie11_pend_14_14_to_main2mcu_lvl_introuter_main_0_bus_in_75_75

const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie11_pend_14_14_to_main2mcu_lvl_introuter_main_0_bus_in_75_75
Initial value:
= {
.lbase = 14,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 75,
}

◆ pcie_g3x2_main_0_bus_pcie12_pend_6_6_to_main2mcu_lvl_introuter_main_0_bus_in_76_76

const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie12_pend_6_6_to_main2mcu_lvl_introuter_main_0_bus_in_76_76
Initial value:
= {
.lbase = 6,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 76,
}

◆ pcie_g3x2_main_0_bus_pcie13_pend_10_10_to_main2mcu_lvl_introuter_main_0_bus_in_77_77

const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie13_pend_10_10_to_main2mcu_lvl_introuter_main_0_bus_in_77_77
Initial value:
= {
.lbase = 10,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 77,
}

◆ pcie_g3x2_main_0_bus_pcie14_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_78_78

const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie14_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_78_78
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 78,
}

◆ pcie_g3x2_main_0_bus_pcie_cpts_pend_12_12_to_main2mcu_lvl_introuter_main_0_bus_in_79_79

const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie_cpts_pend_12_12_to_main2mcu_lvl_introuter_main_0_bus_in_79_79
Initial value:
= {
.lbase = 12,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 79,
}

◆ tisci_if_PCIE0

const struct Sciclient_rmIrqIf* const tisci_if_PCIE0[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie_cpts_pend_12_12_to_main2mcu_lvl_introuter_main_0_bus_in_79_79
Definition: sciclient_irq_rm.c:1864
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie_cpts_hw1_push_17_17_to_timesync_event_introuter_main_0_bus_in_14_14
Definition: sciclient_irq_rm.c:1762
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie_cpts_comp_19_19_to_cmp_event_introuter_main_0_bus_in_5_5
Definition: sciclient_irq_rm.c:1750
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie0_pend_13_13_to_main2mcu_lvl_introuter_main_0_bus_in_64_64
Definition: sciclient_irq_rm.c:1774
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie1_pend_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_65_65
Definition: sciclient_irq_rm.c:1780
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie6_pend_11_11_to_main2mcu_lvl_introuter_main_0_bus_in_70_70
Definition: sciclient_irq_rm.c:1810
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie4_pend_5_5_to_main2mcu_lvl_introuter_main_0_bus_in_68_68
Definition: sciclient_irq_rm.c:1798
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie2_pend_7_7_to_main2mcu_lvl_introuter_main_0_bus_in_66_66
Definition: sciclient_irq_rm.c:1786
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie10_pend_15_15_to_main2mcu_lvl_introuter_main_0_bus_in_74_74
Definition: sciclient_irq_rm.c:1834
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie_cpts_genf0_20_20_to_timesync_event_introuter_main_0_bus_in_10_10
Definition: sciclient_irq_rm.c:1756
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie13_pend_10_10_to_main2mcu_lvl_introuter_main_0_bus_in_77_77
Definition: sciclient_irq_rm.c:1852
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie5_pend_3_3_to_main2mcu_lvl_introuter_main_0_bus_in_69_69
Definition: sciclient_irq_rm.c:1804
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie3_pend_4_4_to_main2mcu_lvl_introuter_main_0_bus_in_67_67
Definition: sciclient_irq_rm.c:1792
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie8_pend_9_9_to_main2mcu_lvl_introuter_main_0_bus_in_72_72
Definition: sciclient_irq_rm.c:1822
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie14_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_78_78
Definition: sciclient_irq_rm.c:1858
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie7_pend_8_8_to_main2mcu_lvl_introuter_main_0_bus_in_71_71
Definition: sciclient_irq_rm.c:1816
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie_cpts_sync_21_21_to_timesync_event_introuter_main_0_bus_in_28_28
Definition: sciclient_irq_rm.c:1768
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie11_pend_14_14_to_main2mcu_lvl_introuter_main_0_bus_in_75_75
Definition: sciclient_irq_rm.c:1840
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie12_pend_6_6_to_main2mcu_lvl_introuter_main_0_bus_in_76_76
Definition: sciclient_irq_rm.c:1846
const struct Sciclient_rmIrqIf pcie_g3x2_main_0_bus_pcie9_pend_16_16_to_main2mcu_lvl_introuter_main_0_bus_in_73_73
Definition: sciclient_irq_rm.c:1828

◆ tisci_irq_PCIE0

const struct Sciclient_rmIrqNode tisci_irq_PCIE0
static
Initial value:
= {
.id = TISCI_DEV_PCIE0,
.n_if = 20,
.p_if = &tisci_if_PCIE0[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_PCIE0[]
Definition: sciclient_irq_rm.c:1870

◆ pcie_g3x2_main_1_bus_pcie_cpts_comp_19_19_to_cmp_event_introuter_main_0_bus_in_6_6

const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie_cpts_comp_19_19_to_cmp_event_introuter_main_0_bus_in_6_6
Initial value:
= {
.lbase = 19,
.len = 1,
.rid = TISCI_DEV_CMPEVENT_INTRTR0,
.rbase = 6,
}

◆ pcie_g3x2_main_1_bus_pcie_cpts_genf0_20_20_to_timesync_event_introuter_main_0_bus_in_11_11

const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie_cpts_genf0_20_20_to_timesync_event_introuter_main_0_bus_in_11_11
Initial value:
= {
.lbase = 20,
.len = 1,
.rid = TISCI_DEV_TIMESYNC_INTRTR0,
.rbase = 11,
}

◆ pcie_g3x2_main_1_bus_pcie_cpts_hw1_push_17_17_to_timesync_event_introuter_main_0_bus_in_15_15

const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie_cpts_hw1_push_17_17_to_timesync_event_introuter_main_0_bus_in_15_15
Initial value:
= {
.lbase = 17,
.len = 1,
.rid = TISCI_DEV_TIMESYNC_INTRTR0,
.rbase = 15,
}

◆ pcie_g3x2_main_1_bus_pcie_cpts_sync_21_21_to_timesync_event_introuter_main_0_bus_in_29_29

const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie_cpts_sync_21_21_to_timesync_event_introuter_main_0_bus_in_29_29
Initial value:
= {
.lbase = 21,
.len = 1,
.rid = TISCI_DEV_TIMESYNC_INTRTR0,
.rbase = 29,
}

◆ pcie_g3x2_main_1_bus_pcie0_pend_13_13_to_main2mcu_lvl_introuter_main_0_bus_in_80_80

const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie0_pend_13_13_to_main2mcu_lvl_introuter_main_0_bus_in_80_80
Initial value:
= {
.lbase = 13,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 80,
}

◆ pcie_g3x2_main_1_bus_pcie1_pend_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_81_81

const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie1_pend_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_81_81
Initial value:
= {
.lbase = 2,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 81,
}

◆ pcie_g3x2_main_1_bus_pcie2_pend_7_7_to_main2mcu_lvl_introuter_main_0_bus_in_82_82

const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie2_pend_7_7_to_main2mcu_lvl_introuter_main_0_bus_in_82_82
Initial value:
= {
.lbase = 7,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 82,
}

◆ pcie_g3x2_main_1_bus_pcie3_pend_4_4_to_main2mcu_lvl_introuter_main_0_bus_in_83_83

const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie3_pend_4_4_to_main2mcu_lvl_introuter_main_0_bus_in_83_83
Initial value:
= {
.lbase = 4,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 83,
}

◆ pcie_g3x2_main_1_bus_pcie4_pend_5_5_to_main2mcu_lvl_introuter_main_0_bus_in_84_84

const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie4_pend_5_5_to_main2mcu_lvl_introuter_main_0_bus_in_84_84
Initial value:
= {
.lbase = 5,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 84,
}

◆ pcie_g3x2_main_1_bus_pcie5_pend_3_3_to_main2mcu_lvl_introuter_main_0_bus_in_85_85

const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie5_pend_3_3_to_main2mcu_lvl_introuter_main_0_bus_in_85_85
Initial value:
= {
.lbase = 3,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 85,
}

◆ pcie_g3x2_main_1_bus_pcie6_pend_11_11_to_main2mcu_lvl_introuter_main_0_bus_in_86_86

const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie6_pend_11_11_to_main2mcu_lvl_introuter_main_0_bus_in_86_86
Initial value:
= {
.lbase = 11,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 86,
}

◆ pcie_g3x2_main_1_bus_pcie7_pend_8_8_to_main2mcu_lvl_introuter_main_0_bus_in_87_87

const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie7_pend_8_8_to_main2mcu_lvl_introuter_main_0_bus_in_87_87
Initial value:
= {
.lbase = 8,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 87,
}

◆ pcie_g3x2_main_1_bus_pcie8_pend_9_9_to_main2mcu_lvl_introuter_main_0_bus_in_88_88

const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie8_pend_9_9_to_main2mcu_lvl_introuter_main_0_bus_in_88_88
Initial value:
= {
.lbase = 9,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 88,
}

◆ pcie_g3x2_main_1_bus_pcie9_pend_16_16_to_main2mcu_lvl_introuter_main_0_bus_in_89_89

const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie9_pend_16_16_to_main2mcu_lvl_introuter_main_0_bus_in_89_89
Initial value:
= {
.lbase = 16,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 89,
}

◆ pcie_g3x2_main_1_bus_pcie10_pend_15_15_to_main2mcu_lvl_introuter_main_0_bus_in_90_90

const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie10_pend_15_15_to_main2mcu_lvl_introuter_main_0_bus_in_90_90
Initial value:
= {
.lbase = 15,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 90,
}

◆ pcie_g3x2_main_1_bus_pcie11_pend_14_14_to_main2mcu_lvl_introuter_main_0_bus_in_91_91

const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie11_pend_14_14_to_main2mcu_lvl_introuter_main_0_bus_in_91_91
Initial value:
= {
.lbase = 14,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 91,
}

◆ pcie_g3x2_main_1_bus_pcie12_pend_6_6_to_main2mcu_lvl_introuter_main_0_bus_in_92_92

const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie12_pend_6_6_to_main2mcu_lvl_introuter_main_0_bus_in_92_92
Initial value:
= {
.lbase = 6,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 92,
}

◆ pcie_g3x2_main_1_bus_pcie13_pend_10_10_to_main2mcu_lvl_introuter_main_0_bus_in_93_93

const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie13_pend_10_10_to_main2mcu_lvl_introuter_main_0_bus_in_93_93
Initial value:
= {
.lbase = 10,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 93,
}

◆ pcie_g3x2_main_1_bus_pcie14_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_94_94

const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie14_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_94_94
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 94,
}

◆ pcie_g3x2_main_1_bus_pcie_cpts_pend_12_12_to_main2mcu_lvl_introuter_main_0_bus_in_95_95

const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie_cpts_pend_12_12_to_main2mcu_lvl_introuter_main_0_bus_in_95_95
Initial value:
= {
.lbase = 12,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 95,
}

◆ tisci_if_PCIE1

const struct Sciclient_rmIrqIf* const tisci_if_PCIE1[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie_cpts_pend_12_12_to_main2mcu_lvl_introuter_main_0_bus_in_95_95
Definition: sciclient_irq_rm.c:2013
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie4_pend_5_5_to_main2mcu_lvl_introuter_main_0_bus_in_84_84
Definition: sciclient_irq_rm.c:1947
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie_cpts_genf0_20_20_to_timesync_event_introuter_main_0_bus_in_11_11
Definition: sciclient_irq_rm.c:1905
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie7_pend_8_8_to_main2mcu_lvl_introuter_main_0_bus_in_87_87
Definition: sciclient_irq_rm.c:1965
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie2_pend_7_7_to_main2mcu_lvl_introuter_main_0_bus_in_82_82
Definition: sciclient_irq_rm.c:1935
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie1_pend_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_81_81
Definition: sciclient_irq_rm.c:1929
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie5_pend_3_3_to_main2mcu_lvl_introuter_main_0_bus_in_85_85
Definition: sciclient_irq_rm.c:1953
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie6_pend_11_11_to_main2mcu_lvl_introuter_main_0_bus_in_86_86
Definition: sciclient_irq_rm.c:1959
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie11_pend_14_14_to_main2mcu_lvl_introuter_main_0_bus_in_91_91
Definition: sciclient_irq_rm.c:1989
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie12_pend_6_6_to_main2mcu_lvl_introuter_main_0_bus_in_92_92
Definition: sciclient_irq_rm.c:1995
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie8_pend_9_9_to_main2mcu_lvl_introuter_main_0_bus_in_88_88
Definition: sciclient_irq_rm.c:1971
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie_cpts_sync_21_21_to_timesync_event_introuter_main_0_bus_in_29_29
Definition: sciclient_irq_rm.c:1917
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie14_pend_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_94_94
Definition: sciclient_irq_rm.c:2007
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie_cpts_hw1_push_17_17_to_timesync_event_introuter_main_0_bus_in_15_15
Definition: sciclient_irq_rm.c:1911
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie_cpts_comp_19_19_to_cmp_event_introuter_main_0_bus_in_6_6
Definition: sciclient_irq_rm.c:1899
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie10_pend_15_15_to_main2mcu_lvl_introuter_main_0_bus_in_90_90
Definition: sciclient_irq_rm.c:1983
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie13_pend_10_10_to_main2mcu_lvl_introuter_main_0_bus_in_93_93
Definition: sciclient_irq_rm.c:2001
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie0_pend_13_13_to_main2mcu_lvl_introuter_main_0_bus_in_80_80
Definition: sciclient_irq_rm.c:1923
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie3_pend_4_4_to_main2mcu_lvl_introuter_main_0_bus_in_83_83
Definition: sciclient_irq_rm.c:1941
const struct Sciclient_rmIrqIf pcie_g3x2_main_1_bus_pcie9_pend_16_16_to_main2mcu_lvl_introuter_main_0_bus_in_89_89
Definition: sciclient_irq_rm.c:1977

◆ tisci_irq_PCIE1

const struct Sciclient_rmIrqNode tisci_irq_PCIE1
static
Initial value:
= {
.id = TISCI_DEV_PCIE1,
.n_if = 20,
.p_if = &tisci_if_PCIE1[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_PCIE1[]
Definition: sciclient_irq_rm.c:2019

◆ sa2_ul_main_0_bus_sa_ul_trng_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_4_4

const struct Sciclient_rmIrqIf sa2_ul_main_0_bus_sa_ul_trng_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_4_4
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 4,
}

◆ sa2_ul_main_0_bus_sa_ul_pka_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_5_5

const struct Sciclient_rmIrqIf sa2_ul_main_0_bus_sa_ul_pka_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_5_5
Initial value:
= {
.lbase = 2,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 5,
}

◆ tisci_if_SA2_UL0

const struct Sciclient_rmIrqIf* const tisci_if_SA2_UL0[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf sa2_ul_main_0_bus_sa_ul_pka_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_5_5
Definition: sciclient_irq_rm.c:2054
const struct Sciclient_rmIrqIf sa2_ul_main_0_bus_sa_ul_trng_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_4_4
Definition: sciclient_irq_rm.c:2048

◆ tisci_irq_SA2_UL0

const struct Sciclient_rmIrqNode tisci_irq_SA2_UL0
static
Initial value:
= {
.id = TISCI_DEV_SA2_UL0,
.n_if = 2,
.p_if = &tisci_if_SA2_UL0[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_SA2_UL0[]
Definition: sciclient_irq_rm.c:2060

◆ spi_main_0_bus_intr_spi_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_96_96

const struct Sciclient_rmIrqIf spi_main_0_bus_intr_spi_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_96_96
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 96,
}

◆ tisci_if_MCSPI0

const struct Sciclient_rmIrqIf* const tisci_if_MCSPI0[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf spi_main_0_bus_intr_spi_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_96_96
Definition: sciclient_irq_rm.c:2071

◆ tisci_irq_MCSPI0

const struct Sciclient_rmIrqNode tisci_irq_MCSPI0
static
Initial value:
= {
.id = TISCI_DEV_MCSPI0,
.n_if = 1,
.p_if = &tisci_if_MCSPI0[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_MCSPI0[]
Definition: sciclient_irq_rm.c:2077

◆ spi_main_1_bus_intr_spi_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_97_97

const struct Sciclient_rmIrqIf spi_main_1_bus_intr_spi_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_97_97
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 97,
}

◆ tisci_if_MCSPI1

const struct Sciclient_rmIrqIf* const tisci_if_MCSPI1[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf spi_main_1_bus_intr_spi_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_97_97
Definition: sciclient_irq_rm.c:2087

◆ tisci_irq_MCSPI1

const struct Sciclient_rmIrqNode tisci_irq_MCSPI1
static
Initial value:
= {
.id = TISCI_DEV_MCSPI1,
.n_if = 1,
.p_if = &tisci_if_MCSPI1[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_MCSPI1[]
Definition: sciclient_irq_rm.c:2093

◆ spi_main_2_bus_intr_spi_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_98_98

const struct Sciclient_rmIrqIf spi_main_2_bus_intr_spi_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_98_98
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 98,
}

◆ tisci_if_MCSPI2

const struct Sciclient_rmIrqIf* const tisci_if_MCSPI2[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf spi_main_2_bus_intr_spi_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_98_98
Definition: sciclient_irq_rm.c:2103

◆ tisci_irq_MCSPI2

const struct Sciclient_rmIrqNode tisci_irq_MCSPI2
static
Initial value:
= {
.id = TISCI_DEV_MCSPI2,
.n_if = 1,
.p_if = &tisci_if_MCSPI2[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_MCSPI2[]
Definition: sciclient_irq_rm.c:2109

◆ spi_main_3_bus_intr_spi_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_99_99

const struct Sciclient_rmIrqIf spi_main_3_bus_intr_spi_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_99_99
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 99,
}

◆ tisci_if_MCSPI3

const struct Sciclient_rmIrqIf* const tisci_if_MCSPI3[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf spi_main_3_bus_intr_spi_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_99_99
Definition: sciclient_irq_rm.c:2119

◆ tisci_irq_MCSPI3

const struct Sciclient_rmIrqNode tisci_irq_MCSPI3
static
Initial value:
= {
.id = TISCI_DEV_MCSPI3,
.n_if = 1,
.p_if = &tisci_if_MCSPI3[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_MCSPI3[]
Definition: sciclient_irq_rm.c:2125

◆ timesync_event_introuter_main_0_bus_outl_32_39_to_pdma_main1_main_0_bus_levent_in_0_7

const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_32_39_to_pdma_main1_main_0_bus_levent_in_0_7
Initial value:
= {
.lbase = 32,
.len = 8,
.rid = TISCI_DEV_PDMA1,
.rbase = 0,
}

◆ timesync_event_introuter_main_0_bus_outl_20_20_to_pcie_g3x2_main_0_bus_pcie_cpts_hw2_push_18_18

const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_20_20_to_pcie_g3x2_main_0_bus_pcie_cpts_hw2_push_18_18
Initial value:
= {
.lbase = 20,
.len = 1,
.rid = TISCI_DEV_PCIE0,
.rbase = 18,
}

◆ timesync_event_introuter_main_0_bus_outl_21_21_to_pcie_g3x2_main_1_bus_pcie_cpts_hw2_push_18_18

const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_21_21_to_pcie_g3x2_main_1_bus_pcie_cpts_hw2_push_18_18
Initial value:
= {
.lbase = 21,
.len = 1,
.rid = TISCI_DEV_PCIE1,
.rbase = 18,
}

◆ timesync_event_introuter_main_0_bus_outl_8_8_to_icss_g_main_0_bus_pr1_edc0_latch0_in_308_308

const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_8_8_to_icss_g_main_0_bus_pr1_edc0_latch0_in_308_308
Initial value:
= {
.lbase = 8,
.len = 1,
.rid = TISCI_DEV_PRU_ICSSG0,
.rbase = 308,
}

◆ timesync_event_introuter_main_0_bus_outl_9_9_to_icss_g_main_0_bus_pr1_edc0_latch1_in_309_309

const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_9_9_to_icss_g_main_0_bus_pr1_edc0_latch1_in_309_309
Initial value:
= {
.lbase = 9,
.len = 1,
.rid = TISCI_DEV_PRU_ICSSG0,
.rbase = 309,
}

◆ timesync_event_introuter_main_0_bus_outl_10_10_to_icss_g_main_0_bus_pr1_edc1_latch0_in_310_310

const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_10_10_to_icss_g_main_0_bus_pr1_edc1_latch0_in_310_310
Initial value:
= {
.lbase = 10,
.len = 1,
.rid = TISCI_DEV_PRU_ICSSG0,
.rbase = 310,
}

◆ timesync_event_introuter_main_0_bus_outl_11_11_to_icss_g_main_0_bus_pr1_edc1_latch1_in_311_311

const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_11_11_to_icss_g_main_0_bus_pr1_edc1_latch1_in_311_311
Initial value:
= {
.lbase = 11,
.len = 1,
.rid = TISCI_DEV_PRU_ICSSG0,
.rbase = 311,
}

◆ timesync_event_introuter_main_0_bus_outl_12_12_to_icss_g_main_1_bus_pr1_edc0_latch0_in_308_308

const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_12_12_to_icss_g_main_1_bus_pr1_edc0_latch0_in_308_308
Initial value:
= {
.lbase = 12,
.len = 1,
.rid = TISCI_DEV_PRU_ICSSG1,
.rbase = 308,
}

◆ timesync_event_introuter_main_0_bus_outl_13_13_to_icss_g_main_1_bus_pr1_edc0_latch1_in_309_309

const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_13_13_to_icss_g_main_1_bus_pr1_edc0_latch1_in_309_309
Initial value:
= {
.lbase = 13,
.len = 1,
.rid = TISCI_DEV_PRU_ICSSG1,
.rbase = 309,
}

◆ timesync_event_introuter_main_0_bus_outl_14_14_to_icss_g_main_1_bus_pr1_edc1_latch0_in_310_310

const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_14_14_to_icss_g_main_1_bus_pr1_edc1_latch0_in_310_310
Initial value:
= {
.lbase = 14,
.len = 1,
.rid = TISCI_DEV_PRU_ICSSG1,
.rbase = 310,
}

◆ timesync_event_introuter_main_0_bus_outl_15_15_to_icss_g_main_1_bus_pr1_edc1_latch1_in_311_311

const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_15_15_to_icss_g_main_1_bus_pr1_edc1_latch1_in_311_311
Initial value:
= {
.lbase = 15,
.len = 1,
.rid = TISCI_DEV_PRU_ICSSG1,
.rbase = 311,
}

◆ timesync_event_introuter_main_0_bus_outl_16_16_to_icss_g_main_2_bus_pr1_edc0_latch0_in_308_308

const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_16_16_to_icss_g_main_2_bus_pr1_edc0_latch0_in_308_308
Initial value:
= {
.lbase = 16,
.len = 1,
.rid = TISCI_DEV_PRU_ICSSG2,
.rbase = 308,
}

◆ timesync_event_introuter_main_0_bus_outl_17_17_to_icss_g_main_2_bus_pr1_edc0_latch1_in_309_309

const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_17_17_to_icss_g_main_2_bus_pr1_edc0_latch1_in_309_309
Initial value:
= {
.lbase = 17,
.len = 1,
.rid = TISCI_DEV_PRU_ICSSG2,
.rbase = 309,
}

◆ timesync_event_introuter_main_0_bus_outl_18_18_to_icss_g_main_2_bus_pr1_edc1_latch0_in_310_310

const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_18_18_to_icss_g_main_2_bus_pr1_edc1_latch0_in_310_310
Initial value:
= {
.lbase = 18,
.len = 1,
.rid = TISCI_DEV_PRU_ICSSG2,
.rbase = 310,
}

◆ timesync_event_introuter_main_0_bus_outl_19_19_to_icss_g_main_2_bus_pr1_edc1_latch1_in_311_311

const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_19_19_to_icss_g_main_2_bus_pr1_edc1_latch1_in_311_311
Initial value:
= {
.lbase = 19,
.len = 1,
.rid = TISCI_DEV_PRU_ICSSG2,
.rbase = 311,
}

◆ timesync_event_introuter_main_0_bus_outl_24_24_to_cpsw_2guss_mcu_0_bus_cpts_hw3_push_0_0

const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_24_24_to_cpsw_2guss_mcu_0_bus_cpts_hw3_push_0_0
Initial value:
= {
.lbase = 24,
.len = 1,
.rid = TISCI_DEV_MCU_CPSW0,
.rbase = 0,
}

◆ timesync_event_introuter_main_0_bus_outl_25_25_to_cpsw_2guss_mcu_0_bus_cpts_hw4_push_2_2

const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_25_25_to_cpsw_2guss_mcu_0_bus_cpts_hw4_push_2_2
Initial value:
= {
.lbase = 25,
.len = 1,
.rid = TISCI_DEV_MCU_CPSW0,
.rbase = 2,
}

◆ timesync_event_introuter_main_0_bus_outl_0_0_to_navss256l_main_0_bus_cpts0_hw1_push_0_0

const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_0_0_to_navss256l_main_0_bus_cpts0_hw1_push_0_0
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_NAVSS0,
.rbase = 0,
}

◆ timesync_event_introuter_main_0_bus_outl_1_1_to_navss256l_main_0_bus_cpts0_hw2_push_2_2

const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_1_1_to_navss256l_main_0_bus_cpts0_hw2_push_2_2
Initial value:
= {
.lbase = 1,
.len = 1,
.rid = TISCI_DEV_NAVSS0,
.rbase = 2,
}

◆ timesync_event_introuter_main_0_bus_outl_2_2_to_navss256l_main_0_bus_cpts0_hw3_push_3_3

const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_2_2_to_navss256l_main_0_bus_cpts0_hw3_push_3_3
Initial value:
= {
.lbase = 2,
.len = 1,
.rid = TISCI_DEV_NAVSS0,
.rbase = 3,
}

◆ timesync_event_introuter_main_0_bus_outl_3_3_to_navss256l_main_0_bus_cpts0_hw4_push_4_4

const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_3_3_to_navss256l_main_0_bus_cpts0_hw4_push_4_4
Initial value:
= {
.lbase = 3,
.len = 1,
.rid = TISCI_DEV_NAVSS0,
.rbase = 4,
}

◆ timesync_event_introuter_main_0_bus_outl_4_4_to_navss256l_main_0_bus_cpts0_hw5_push_5_5

const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_4_4_to_navss256l_main_0_bus_cpts0_hw5_push_5_5
Initial value:
= {
.lbase = 4,
.len = 1,
.rid = TISCI_DEV_NAVSS0,
.rbase = 5,
}

◆ timesync_event_introuter_main_0_bus_outl_5_5_to_navss256l_main_0_bus_cpts0_hw6_push_6_6

const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_5_5_to_navss256l_main_0_bus_cpts0_hw6_push_6_6
Initial value:
= {
.lbase = 5,
.len = 1,
.rid = TISCI_DEV_NAVSS0,
.rbase = 6,
}

◆ timesync_event_introuter_main_0_bus_outl_6_6_to_navss256l_main_0_bus_cpts0_hw7_push_7_7

const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_6_6_to_navss256l_main_0_bus_cpts0_hw7_push_7_7
Initial value:
= {
.lbase = 6,
.len = 1,
.rid = TISCI_DEV_NAVSS0,
.rbase = 7,
}

◆ timesync_event_introuter_main_0_bus_outl_7_7_to_navss256l_main_0_bus_cpts0_hw8_push_8_8

const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_7_7_to_navss256l_main_0_bus_cpts0_hw8_push_8_8
Initial value:
= {
.lbase = 7,
.len = 1,
.rid = TISCI_DEV_NAVSS0,
.rbase = 8,
}

◆ tisci_if_TIMESYNC_INTRTR0

const struct Sciclient_rmIrqIf* const tisci_if_TIMESYNC_INTRTR0[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_3_3_to_navss256l_main_0_bus_cpts0_hw4_push_4_4
Definition: sciclient_irq_rm.c:2255
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_17_17_to_icss_g_main_2_bus_pr1_edc0_latch1_in_309_309
Definition: sciclient_irq_rm.c:2207
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_5_5_to_navss256l_main_0_bus_cpts0_hw6_push_6_6
Definition: sciclient_irq_rm.c:2267
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_0_0_to_navss256l_main_0_bus_cpts0_hw1_push_0_0
Definition: sciclient_irq_rm.c:2237
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_18_18_to_icss_g_main_2_bus_pr1_edc1_latch0_in_310_310
Definition: sciclient_irq_rm.c:2213
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_19_19_to_icss_g_main_2_bus_pr1_edc1_latch1_in_311_311
Definition: sciclient_irq_rm.c:2219
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_20_20_to_pcie_g3x2_main_0_bus_pcie_cpts_hw2_push_18_18
Definition: sciclient_irq_rm.c:2141
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_32_39_to_pdma_main1_main_0_bus_levent_in_0_7
Definition: sciclient_irq_rm.c:2135
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_12_12_to_icss_g_main_1_bus_pr1_edc0_latch0_in_308_308
Definition: sciclient_irq_rm.c:2177
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_24_24_to_cpsw_2guss_mcu_0_bus_cpts_hw3_push_0_0
Definition: sciclient_irq_rm.c:2225
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_15_15_to_icss_g_main_1_bus_pr1_edc1_latch1_in_311_311
Definition: sciclient_irq_rm.c:2195
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_10_10_to_icss_g_main_0_bus_pr1_edc1_latch0_in_310_310
Definition: sciclient_irq_rm.c:2165
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_6_6_to_navss256l_main_0_bus_cpts0_hw7_push_7_7
Definition: sciclient_irq_rm.c:2273
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_25_25_to_cpsw_2guss_mcu_0_bus_cpts_hw4_push_2_2
Definition: sciclient_irq_rm.c:2231
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_2_2_to_navss256l_main_0_bus_cpts0_hw3_push_3_3
Definition: sciclient_irq_rm.c:2249
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_1_1_to_navss256l_main_0_bus_cpts0_hw2_push_2_2
Definition: sciclient_irq_rm.c:2243
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_14_14_to_icss_g_main_1_bus_pr1_edc1_latch0_in_310_310
Definition: sciclient_irq_rm.c:2189
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_7_7_to_navss256l_main_0_bus_cpts0_hw8_push_8_8
Definition: sciclient_irq_rm.c:2279
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_21_21_to_pcie_g3x2_main_1_bus_pcie_cpts_hw2_push_18_18
Definition: sciclient_irq_rm.c:2147
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_4_4_to_navss256l_main_0_bus_cpts0_hw5_push_5_5
Definition: sciclient_irq_rm.c:2261
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_11_11_to_icss_g_main_0_bus_pr1_edc1_latch1_in_311_311
Definition: sciclient_irq_rm.c:2171
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_9_9_to_icss_g_main_0_bus_pr1_edc0_latch1_in_309_309
Definition: sciclient_irq_rm.c:2159
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_16_16_to_icss_g_main_2_bus_pr1_edc0_latch0_in_308_308
Definition: sciclient_irq_rm.c:2201
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_13_13_to_icss_g_main_1_bus_pr1_edc0_latch1_in_309_309
Definition: sciclient_irq_rm.c:2183
const struct Sciclient_rmIrqIf timesync_event_introuter_main_0_bus_outl_8_8_to_icss_g_main_0_bus_pr1_edc0_latch0_in_308_308
Definition: sciclient_irq_rm.c:2153

◆ tisci_irq_TIMESYNC_INTRTR0

const struct Sciclient_rmIrqNode tisci_irq_TIMESYNC_INTRTR0
static
Initial value:
= {
.id = TISCI_DEV_TIMESYNC_INTRTR0,
.n_if = 25,
}
const struct Sciclient_rmIrqIf *const tisci_if_TIMESYNC_INTRTR0[]
Definition: sciclient_irq_rm.c:2285

◆ usart_main_0_bus_usart_irq_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_104_104

const struct Sciclient_rmIrqIf usart_main_0_bus_usart_irq_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_104_104
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 104,
}

◆ tisci_if_UART0

const struct Sciclient_rmIrqIf* const tisci_if_UART0[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf usart_main_0_bus_usart_irq_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_104_104
Definition: sciclient_irq_rm.c:2319

◆ tisci_irq_UART0

const struct Sciclient_rmIrqNode tisci_irq_UART0
static
Initial value:
= {
.id = TISCI_DEV_UART0,
.n_if = 1,
.p_if = &tisci_if_UART0[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_UART0[]
Definition: sciclient_irq_rm.c:2325

◆ usart_main_1_bus_usart_irq_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_105_105

const struct Sciclient_rmIrqIf usart_main_1_bus_usart_irq_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_105_105
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 105,
}

◆ tisci_if_UART1

const struct Sciclient_rmIrqIf* const tisci_if_UART1[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf usart_main_1_bus_usart_irq_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_105_105
Definition: sciclient_irq_rm.c:2335

◆ tisci_irq_UART1

const struct Sciclient_rmIrqNode tisci_irq_UART1
static
Initial value:
= {
.id = TISCI_DEV_UART1,
.n_if = 1,
.p_if = &tisci_if_UART1[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_UART1[]
Definition: sciclient_irq_rm.c:2341

◆ usart_main_2_bus_usart_irq_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_106_106

const struct Sciclient_rmIrqIf usart_main_2_bus_usart_irq_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_106_106
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 106,
}

◆ tisci_if_UART2

const struct Sciclient_rmIrqIf* const tisci_if_UART2[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf usart_main_2_bus_usart_irq_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_106_106
Definition: sciclient_irq_rm.c:2351

◆ tisci_irq_UART2

const struct Sciclient_rmIrqNode tisci_irq_UART2
static
Initial value:
= {
.id = TISCI_DEV_UART2,
.n_if = 1,
.p_if = &tisci_if_UART2[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_UART2[]
Definition: sciclient_irq_rm.c:2357

◆ usb3ss2p0_gs80_main_0_bus_otg_lvl_14_14_to_main2mcu_lvl_introuter_main_0_bus_in_128_128

const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_otg_lvl_14_14_to_main2mcu_lvl_introuter_main_0_bus_in_128_128
Initial value:
= {
.lbase = 14,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 128,
}

◆ usb3ss2p0_gs80_main_0_bus_misc_lvl_17_17_to_main2mcu_lvl_introuter_main_0_bus_in_129_129

const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_misc_lvl_17_17_to_main2mcu_lvl_introuter_main_0_bus_in_129_129
Initial value:
= {
.lbase = 17,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 129,
}

◆ usb3ss2p0_gs80_main_0_bus_bc_lvl_18_18_to_main2mcu_lvl_introuter_main_0_bus_in_130_130

const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_bc_lvl_18_18_to_main2mcu_lvl_introuter_main_0_bus_in_130_130
Initial value:
= {
.lbase = 18,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 130,
}

◆ usb3ss2p0_gs80_main_0_bus_pme_gen_lvl_16_16_to_main2mcu_lvl_introuter_main_0_bus_in_131_131

const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_pme_gen_lvl_16_16_to_main2mcu_lvl_introuter_main_0_bus_in_131_131
Initial value:
= {
.lbase = 16,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 131,
}

◆ usb3ss2p0_gs80_main_0_bus_i00_lvl_19_19_to_main2mcu_lvl_introuter_main_0_bus_in_132_132

const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i00_lvl_19_19_to_main2mcu_lvl_introuter_main_0_bus_in_132_132
Initial value:
= {
.lbase = 19,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 132,
}

◆ usb3ss2p0_gs80_main_0_bus_i01_lvl_8_8_to_main2mcu_lvl_introuter_main_0_bus_in_133_133

const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i01_lvl_8_8_to_main2mcu_lvl_introuter_main_0_bus_in_133_133
Initial value:
= {
.lbase = 8,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 133,
}

◆ usb3ss2p0_gs80_main_0_bus_i02_lvl_7_7_to_main2mcu_lvl_introuter_main_0_bus_in_134_134

const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i02_lvl_7_7_to_main2mcu_lvl_introuter_main_0_bus_in_134_134
Initial value:
= {
.lbase = 7,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 134,
}

◆ usb3ss2p0_gs80_main_0_bus_i03_lvl_13_13_to_main2mcu_lvl_introuter_main_0_bus_in_135_135

const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i03_lvl_13_13_to_main2mcu_lvl_introuter_main_0_bus_in_135_135
Initial value:
= {
.lbase = 13,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 135,
}

◆ usb3ss2p0_gs80_main_0_bus_i04_lvl_3_3_to_main2mcu_lvl_introuter_main_0_bus_in_136_136

const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i04_lvl_3_3_to_main2mcu_lvl_introuter_main_0_bus_in_136_136
Initial value:
= {
.lbase = 3,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 136,
}

◆ usb3ss2p0_gs80_main_0_bus_i05_lvl_12_12_to_main2mcu_lvl_introuter_main_0_bus_in_137_137

const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i05_lvl_12_12_to_main2mcu_lvl_introuter_main_0_bus_in_137_137
Initial value:
= {
.lbase = 12,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 137,
}

◆ usb3ss2p0_gs80_main_0_bus_i06_lvl_4_4_to_main2mcu_lvl_introuter_main_0_bus_in_138_138

const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i06_lvl_4_4_to_main2mcu_lvl_introuter_main_0_bus_in_138_138
Initial value:
= {
.lbase = 4,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 138,
}

◆ usb3ss2p0_gs80_main_0_bus_i07_lvl_6_6_to_main2mcu_lvl_introuter_main_0_bus_in_139_139

const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i07_lvl_6_6_to_main2mcu_lvl_introuter_main_0_bus_in_139_139
Initial value:
= {
.lbase = 6,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 139,
}

◆ usb3ss2p0_gs80_main_0_bus_i08_lvl_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_140_140

const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i08_lvl_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_140_140
Initial value:
= {
.lbase = 2,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 140,
}

◆ usb3ss2p0_gs80_main_0_bus_i09_lvl_11_11_to_main2mcu_lvl_introuter_main_0_bus_in_141_141

const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i09_lvl_11_11_to_main2mcu_lvl_introuter_main_0_bus_in_141_141
Initial value:
= {
.lbase = 11,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 141,
}

◆ usb3ss2p0_gs80_main_0_bus_i10_lvl_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_142_142

const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i10_lvl_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_142_142
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 142,
}

◆ usb3ss2p0_gs80_main_0_bus_i11_lvl_20_20_to_main2mcu_lvl_introuter_main_0_bus_in_143_143

const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i11_lvl_20_20_to_main2mcu_lvl_introuter_main_0_bus_in_143_143
Initial value:
= {
.lbase = 20,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 143,
}

◆ usb3ss2p0_gs80_main_0_bus_i12_lvl_9_9_to_main2mcu_lvl_introuter_main_0_bus_in_144_144

const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i12_lvl_9_9_to_main2mcu_lvl_introuter_main_0_bus_in_144_144
Initial value:
= {
.lbase = 9,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 144,
}

◆ usb3ss2p0_gs80_main_0_bus_i13_lvl_15_15_to_main2mcu_lvl_introuter_main_0_bus_in_145_145

const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i13_lvl_15_15_to_main2mcu_lvl_introuter_main_0_bus_in_145_145
Initial value:
= {
.lbase = 15,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 145,
}

◆ usb3ss2p0_gs80_main_0_bus_i14_lvl_5_5_to_main2mcu_lvl_introuter_main_0_bus_in_146_146

const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i14_lvl_5_5_to_main2mcu_lvl_introuter_main_0_bus_in_146_146
Initial value:
= {
.lbase = 5,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 146,
}

◆ usb3ss2p0_gs80_main_0_bus_i15_lvl_10_10_to_main2mcu_lvl_introuter_main_0_bus_in_147_147

const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i15_lvl_10_10_to_main2mcu_lvl_introuter_main_0_bus_in_147_147
Initial value:
= {
.lbase = 10,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 147,
}

◆ tisci_if_USB3SS0

const struct Sciclient_rmIrqIf* const tisci_if_USB3SS0[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i00_lvl_19_19_to_main2mcu_lvl_introuter_main_0_bus_in_132_132
Definition: sciclient_irq_rm.c:2391
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i02_lvl_7_7_to_main2mcu_lvl_introuter_main_0_bus_in_134_134
Definition: sciclient_irq_rm.c:2403
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_pme_gen_lvl_16_16_to_main2mcu_lvl_introuter_main_0_bus_in_131_131
Definition: sciclient_irq_rm.c:2385
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i12_lvl_9_9_to_main2mcu_lvl_introuter_main_0_bus_in_144_144
Definition: sciclient_irq_rm.c:2463
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i06_lvl_4_4_to_main2mcu_lvl_introuter_main_0_bus_in_138_138
Definition: sciclient_irq_rm.c:2427
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i05_lvl_12_12_to_main2mcu_lvl_introuter_main_0_bus_in_137_137
Definition: sciclient_irq_rm.c:2421
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i09_lvl_11_11_to_main2mcu_lvl_introuter_main_0_bus_in_141_141
Definition: sciclient_irq_rm.c:2445
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_otg_lvl_14_14_to_main2mcu_lvl_introuter_main_0_bus_in_128_128
Definition: sciclient_irq_rm.c:2367
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i11_lvl_20_20_to_main2mcu_lvl_introuter_main_0_bus_in_143_143
Definition: sciclient_irq_rm.c:2457
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i10_lvl_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_142_142
Definition: sciclient_irq_rm.c:2451
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i01_lvl_8_8_to_main2mcu_lvl_introuter_main_0_bus_in_133_133
Definition: sciclient_irq_rm.c:2397
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_misc_lvl_17_17_to_main2mcu_lvl_introuter_main_0_bus_in_129_129
Definition: sciclient_irq_rm.c:2373
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i15_lvl_10_10_to_main2mcu_lvl_introuter_main_0_bus_in_147_147
Definition: sciclient_irq_rm.c:2481
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i08_lvl_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_140_140
Definition: sciclient_irq_rm.c:2439
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i03_lvl_13_13_to_main2mcu_lvl_introuter_main_0_bus_in_135_135
Definition: sciclient_irq_rm.c:2409
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i04_lvl_3_3_to_main2mcu_lvl_introuter_main_0_bus_in_136_136
Definition: sciclient_irq_rm.c:2415
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_bc_lvl_18_18_to_main2mcu_lvl_introuter_main_0_bus_in_130_130
Definition: sciclient_irq_rm.c:2379
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i13_lvl_15_15_to_main2mcu_lvl_introuter_main_0_bus_in_145_145
Definition: sciclient_irq_rm.c:2469
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i14_lvl_5_5_to_main2mcu_lvl_introuter_main_0_bus_in_146_146
Definition: sciclient_irq_rm.c:2475
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_0_bus_i07_lvl_6_6_to_main2mcu_lvl_introuter_main_0_bus_in_139_139
Definition: sciclient_irq_rm.c:2433

◆ tisci_irq_USB3SS0

const struct Sciclient_rmIrqNode tisci_irq_USB3SS0
static
Initial value:
= {
.id = TISCI_DEV_USB3SS0,
.n_if = 20,
.p_if = &tisci_if_USB3SS0[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_USB3SS0[]
Definition: sciclient_irq_rm.c:2487

◆ usb3ss2p0_gs80_main_1_bus_otg_lvl_14_14_to_main2mcu_lvl_introuter_main_0_bus_in_148_148

const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_otg_lvl_14_14_to_main2mcu_lvl_introuter_main_0_bus_in_148_148
Initial value:
= {
.lbase = 14,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 148,
}

◆ usb3ss2p0_gs80_main_1_bus_misc_lvl_17_17_to_main2mcu_lvl_introuter_main_0_bus_in_149_149

const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_misc_lvl_17_17_to_main2mcu_lvl_introuter_main_0_bus_in_149_149
Initial value:
= {
.lbase = 17,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 149,
}

◆ usb3ss2p0_gs80_main_1_bus_bc_lvl_18_18_to_main2mcu_lvl_introuter_main_0_bus_in_150_150

const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_bc_lvl_18_18_to_main2mcu_lvl_introuter_main_0_bus_in_150_150
Initial value:
= {
.lbase = 18,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 150,
}

◆ usb3ss2p0_gs80_main_1_bus_pme_gen_lvl_16_16_to_main2mcu_lvl_introuter_main_0_bus_in_151_151

const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_pme_gen_lvl_16_16_to_main2mcu_lvl_introuter_main_0_bus_in_151_151
Initial value:
= {
.lbase = 16,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 151,
}

◆ usb3ss2p0_gs80_main_1_bus_i00_lvl_19_19_to_main2mcu_lvl_introuter_main_0_bus_in_152_152

const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i00_lvl_19_19_to_main2mcu_lvl_introuter_main_0_bus_in_152_152
Initial value:
= {
.lbase = 19,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 152,
}

◆ usb3ss2p0_gs80_main_1_bus_i01_lvl_8_8_to_main2mcu_lvl_introuter_main_0_bus_in_153_153

const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i01_lvl_8_8_to_main2mcu_lvl_introuter_main_0_bus_in_153_153
Initial value:
= {
.lbase = 8,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 153,
}

◆ usb3ss2p0_gs80_main_1_bus_i02_lvl_7_7_to_main2mcu_lvl_introuter_main_0_bus_in_154_154

const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i02_lvl_7_7_to_main2mcu_lvl_introuter_main_0_bus_in_154_154
Initial value:
= {
.lbase = 7,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 154,
}

◆ usb3ss2p0_gs80_main_1_bus_i03_lvl_13_13_to_main2mcu_lvl_introuter_main_0_bus_in_155_155

const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i03_lvl_13_13_to_main2mcu_lvl_introuter_main_0_bus_in_155_155
Initial value:
= {
.lbase = 13,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 155,
}

◆ usb3ss2p0_gs80_main_1_bus_i04_lvl_3_3_to_main2mcu_lvl_introuter_main_0_bus_in_156_156

const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i04_lvl_3_3_to_main2mcu_lvl_introuter_main_0_bus_in_156_156
Initial value:
= {
.lbase = 3,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 156,
}

◆ usb3ss2p0_gs80_main_1_bus_i05_lvl_12_12_to_main2mcu_lvl_introuter_main_0_bus_in_157_157

const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i05_lvl_12_12_to_main2mcu_lvl_introuter_main_0_bus_in_157_157
Initial value:
= {
.lbase = 12,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 157,
}

◆ usb3ss2p0_gs80_main_1_bus_i06_lvl_4_4_to_main2mcu_lvl_introuter_main_0_bus_in_158_158

const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i06_lvl_4_4_to_main2mcu_lvl_introuter_main_0_bus_in_158_158
Initial value:
= {
.lbase = 4,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 158,
}

◆ usb3ss2p0_gs80_main_1_bus_i07_lvl_6_6_to_main2mcu_lvl_introuter_main_0_bus_in_159_159

const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i07_lvl_6_6_to_main2mcu_lvl_introuter_main_0_bus_in_159_159
Initial value:
= {
.lbase = 6,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 159,
}

◆ usb3ss2p0_gs80_main_1_bus_i08_lvl_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_160_160

const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i08_lvl_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_160_160
Initial value:
= {
.lbase = 2,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 160,
}

◆ usb3ss2p0_gs80_main_1_bus_i09_lvl_11_11_to_main2mcu_lvl_introuter_main_0_bus_in_161_161

const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i09_lvl_11_11_to_main2mcu_lvl_introuter_main_0_bus_in_161_161
Initial value:
= {
.lbase = 11,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 161,
}

◆ usb3ss2p0_gs80_main_1_bus_i10_lvl_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_162_162

const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i10_lvl_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_162_162
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 162,
}

◆ usb3ss2p0_gs80_main_1_bus_i11_lvl_20_20_to_main2mcu_lvl_introuter_main_0_bus_in_163_163

const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i11_lvl_20_20_to_main2mcu_lvl_introuter_main_0_bus_in_163_163
Initial value:
= {
.lbase = 20,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 163,
}

◆ usb3ss2p0_gs80_main_1_bus_i12_lvl_9_9_to_main2mcu_lvl_introuter_main_0_bus_in_164_164

const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i12_lvl_9_9_to_main2mcu_lvl_introuter_main_0_bus_in_164_164
Initial value:
= {
.lbase = 9,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 164,
}

◆ usb3ss2p0_gs80_main_1_bus_i13_lvl_15_15_to_main2mcu_lvl_introuter_main_0_bus_in_165_165

const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i13_lvl_15_15_to_main2mcu_lvl_introuter_main_0_bus_in_165_165
Initial value:
= {
.lbase = 15,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 165,
}

◆ usb3ss2p0_gs80_main_1_bus_i14_lvl_5_5_to_main2mcu_lvl_introuter_main_0_bus_in_166_166

const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i14_lvl_5_5_to_main2mcu_lvl_introuter_main_0_bus_in_166_166
Initial value:
= {
.lbase = 5,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 166,
}

◆ usb3ss2p0_gs80_main_1_bus_i15_lvl_10_10_to_main2mcu_lvl_introuter_main_0_bus_in_167_167

const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i15_lvl_10_10_to_main2mcu_lvl_introuter_main_0_bus_in_167_167
Initial value:
= {
.lbase = 10,
.len = 1,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 167,
}

◆ tisci_if_USB3SS1

const struct Sciclient_rmIrqIf* const tisci_if_USB3SS1[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_misc_lvl_17_17_to_main2mcu_lvl_introuter_main_0_bus_in_149_149
Definition: sciclient_irq_rm.c:2522
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i02_lvl_7_7_to_main2mcu_lvl_introuter_main_0_bus_in_154_154
Definition: sciclient_irq_rm.c:2552
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i03_lvl_13_13_to_main2mcu_lvl_introuter_main_0_bus_in_155_155
Definition: sciclient_irq_rm.c:2558
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i10_lvl_0_0_to_main2mcu_lvl_introuter_main_0_bus_in_162_162
Definition: sciclient_irq_rm.c:2600
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i07_lvl_6_6_to_main2mcu_lvl_introuter_main_0_bus_in_159_159
Definition: sciclient_irq_rm.c:2582
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i14_lvl_5_5_to_main2mcu_lvl_introuter_main_0_bus_in_166_166
Definition: sciclient_irq_rm.c:2624
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i11_lvl_20_20_to_main2mcu_lvl_introuter_main_0_bus_in_163_163
Definition: sciclient_irq_rm.c:2606
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i13_lvl_15_15_to_main2mcu_lvl_introuter_main_0_bus_in_165_165
Definition: sciclient_irq_rm.c:2618
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i00_lvl_19_19_to_main2mcu_lvl_introuter_main_0_bus_in_152_152
Definition: sciclient_irq_rm.c:2540
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i05_lvl_12_12_to_main2mcu_lvl_introuter_main_0_bus_in_157_157
Definition: sciclient_irq_rm.c:2570
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_pme_gen_lvl_16_16_to_main2mcu_lvl_introuter_main_0_bus_in_151_151
Definition: sciclient_irq_rm.c:2534
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i06_lvl_4_4_to_main2mcu_lvl_introuter_main_0_bus_in_158_158
Definition: sciclient_irq_rm.c:2576
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i12_lvl_9_9_to_main2mcu_lvl_introuter_main_0_bus_in_164_164
Definition: sciclient_irq_rm.c:2612
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i15_lvl_10_10_to_main2mcu_lvl_introuter_main_0_bus_in_167_167
Definition: sciclient_irq_rm.c:2630
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_otg_lvl_14_14_to_main2mcu_lvl_introuter_main_0_bus_in_148_148
Definition: sciclient_irq_rm.c:2516
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i08_lvl_2_2_to_main2mcu_lvl_introuter_main_0_bus_in_160_160
Definition: sciclient_irq_rm.c:2588
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_bc_lvl_18_18_to_main2mcu_lvl_introuter_main_0_bus_in_150_150
Definition: sciclient_irq_rm.c:2528
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i09_lvl_11_11_to_main2mcu_lvl_introuter_main_0_bus_in_161_161
Definition: sciclient_irq_rm.c:2594
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i04_lvl_3_3_to_main2mcu_lvl_introuter_main_0_bus_in_156_156
Definition: sciclient_irq_rm.c:2564
const struct Sciclient_rmIrqIf usb3ss2p0_gs80_main_1_bus_i01_lvl_8_8_to_main2mcu_lvl_introuter_main_0_bus_in_153_153
Definition: sciclient_irq_rm.c:2546

◆ tisci_irq_USB3SS1

const struct Sciclient_rmIrqNode tisci_irq_USB3SS1
static
Initial value:
= {
.id = TISCI_DEV_USB3SS1,
.n_if = 20,
.p_if = &tisci_if_USB3SS1[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_USB3SS1[]
Definition: sciclient_irq_rm.c:2636

◆ wkup_gpiomux_introuter_wkup_0_bus_outp_0_15_to_mcu_armss0_cpu0_bus_intr_124_139

const struct Sciclient_rmIrqIf wkup_gpiomux_introuter_wkup_0_bus_outp_0_15_to_mcu_armss0_cpu0_bus_intr_124_139
Initial value:
= {
.lbase = 0,
.len = 16,
.rid = TISCI_DEV_MCU_ARMSS0_CPU0,
.rbase = 124,
}

◆ wkup_gpiomux_introuter_wkup_0_bus_outp_0_15_to_mcu_armss0_cpu1_bus_intr_124_139

const struct Sciclient_rmIrqIf wkup_gpiomux_introuter_wkup_0_bus_outp_0_15_to_mcu_armss0_cpu1_bus_intr_124_139
Initial value:
= {
.lbase = 0,
.len = 16,
.rid = TISCI_DEV_MCU_ARMSS0_CPU1,
.rbase = 124,
}

◆ wkup_gpiomux_introuter_wkup_0_bus_outp_0_15_to_gic500ss_main_0_bus_spi_712_727

const struct Sciclient_rmIrqIf wkup_gpiomux_introuter_wkup_0_bus_outp_0_15_to_gic500ss_main_0_bus_spi_712_727
Initial value:
= {
.lbase = 0,
.len = 16,
.rid = TISCI_DEV_GIC0,
.rbase = 712,
}

◆ wkup_gpiomux_introuter_wkup_0_bus_outp_0_11_to_dmsc_wkup_0_bus_int_8_19

const struct Sciclient_rmIrqIf wkup_gpiomux_introuter_wkup_0_bus_outp_0_11_to_dmsc_wkup_0_bus_int_8_19
Initial value:
= {
.lbase = 0,
.len = 12,
.rid = TISCI_DEV_WKUP_DMSC0,
.rbase = 8,
}

◆ wkup_gpiomux_introuter_wkup_0_bus_outp_8_15_to_esm_wkup_wkup_0_bus_esm_pls_event0_256_263

const struct Sciclient_rmIrqIf wkup_gpiomux_introuter_wkup_0_bus_outp_8_15_to_esm_wkup_wkup_0_bus_esm_pls_event0_256_263
Initial value:
= {
.lbase = 8,
.len = 8,
.rid = TISCI_DEV_WKUP_ESM0,
.rbase = 256,
}

◆ wkup_gpiomux_introuter_wkup_0_bus_outp_8_15_to_esm_wkup_wkup_0_bus_esm_pls_event1_264_271

const struct Sciclient_rmIrqIf wkup_gpiomux_introuter_wkup_0_bus_outp_8_15_to_esm_wkup_wkup_0_bus_esm_pls_event1_264_271
Initial value:
= {
.lbase = 8,
.len = 8,
.rid = TISCI_DEV_WKUP_ESM0,
.rbase = 264,
}

◆ wkup_gpiomux_introuter_wkup_0_bus_outp_8_15_to_esm_wkup_wkup_0_bus_esm_pls_event2_88_95

const struct Sciclient_rmIrqIf wkup_gpiomux_introuter_wkup_0_bus_outp_8_15_to_esm_wkup_wkup_0_bus_esm_pls_event2_88_95
Initial value:
= {
.lbase = 8,
.len = 8,
.rid = TISCI_DEV_WKUP_ESM0,
.rbase = 88,
}

◆ tisci_if_WKUP_GPIOMUX_INTRTR0

const struct Sciclient_rmIrqIf* const tisci_if_WKUP_GPIOMUX_INTRTR0[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf wkup_gpiomux_introuter_wkup_0_bus_outp_0_11_to_dmsc_wkup_0_bus_int_8_19
Definition: sciclient_irq_rm.c:2683
const struct Sciclient_rmIrqIf wkup_gpiomux_introuter_wkup_0_bus_outp_0_15_to_mcu_armss0_cpu0_bus_intr_124_139
Definition: sciclient_irq_rm.c:2665
const struct Sciclient_rmIrqIf wkup_gpiomux_introuter_wkup_0_bus_outp_8_15_to_esm_wkup_wkup_0_bus_esm_pls_event2_88_95
Definition: sciclient_irq_rm.c:2701
const struct Sciclient_rmIrqIf wkup_gpiomux_introuter_wkup_0_bus_outp_0_15_to_mcu_armss0_cpu1_bus_intr_124_139
Definition: sciclient_irq_rm.c:2671
const struct Sciclient_rmIrqIf wkup_gpiomux_introuter_wkup_0_bus_outp_8_15_to_esm_wkup_wkup_0_bus_esm_pls_event1_264_271
Definition: sciclient_irq_rm.c:2695
const struct Sciclient_rmIrqIf wkup_gpiomux_introuter_wkup_0_bus_outp_8_15_to_esm_wkup_wkup_0_bus_esm_pls_event0_256_263
Definition: sciclient_irq_rm.c:2689
const struct Sciclient_rmIrqIf wkup_gpiomux_introuter_wkup_0_bus_outp_0_15_to_gic500ss_main_0_bus_spi_712_727
Definition: sciclient_irq_rm.c:2677

◆ tisci_irq_WKUP_GPIOMUX_INTRTR0

const struct Sciclient_rmIrqNode tisci_irq_WKUP_GPIOMUX_INTRTR0
static
Initial value:
= {
.id = TISCI_DEV_WKUP_GPIOMUX_INTRTR0,
.n_if = 7,
}
const struct Sciclient_rmIrqIf *const tisci_if_WKUP_GPIOMUX_INTRTR0[]
Definition: sciclient_irq_rm.c:2707

◆ navss0_cpts0_event_pend_intr_0_0_to_navss0_intr_router_0_in_intr_391_391

const struct Sciclient_rmIrqIf navss0_cpts0_event_pend_intr_0_0_to_navss0_intr_router_0_in_intr_391_391
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_NAVSS0_INTR_ROUTER_0,
.rbase = 391,
}

◆ tisci_if_navss0_cpts0

const struct Sciclient_rmIrqIf* const tisci_if_navss0_cpts0[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf navss0_cpts0_event_pend_intr_0_0_to_navss0_intr_router_0_in_intr_391_391
Definition: sciclient_irq_rm.c:2723

◆ tisci_irq_navss0_cpts0

const struct Sciclient_rmIrqNode tisci_irq_navss0_cpts0
static
Initial value:
= {
.id = TISCI_DEV_NAVSS0_CPTS0,
.n_if = 1,
.p_if = &tisci_if_navss0_cpts0[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_navss0_cpts0[]
Definition: sciclient_irq_rm.c:2729

◆ navss0_mailbox0_cluster0_pend_intr_0_3_to_navss0_intr_router_0_in_intr_436_439

const struct Sciclient_rmIrqIf navss0_mailbox0_cluster0_pend_intr_0_3_to_navss0_intr_router_0_in_intr_436_439
Initial value:
= {
.lbase = 0,
.len = 4,
.rid = TISCI_DEV_NAVSS0_INTR_ROUTER_0,
.rbase = 436,
}

◆ tisci_if_navss0_mailbox0_cluster0

const struct Sciclient_rmIrqIf* const tisci_if_navss0_mailbox0_cluster0[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf navss0_mailbox0_cluster0_pend_intr_0_3_to_navss0_intr_router_0_in_intr_436_439
Definition: sciclient_irq_rm.c:2739

◆ tisci_irq_navss0_mailbox0_cluster0

const struct Sciclient_rmIrqNode tisci_irq_navss0_mailbox0_cluster0
static
Initial value:
= {
.id = TISCI_DEV_NAVSS0_MAILBOX0_CLUSTER0,
.n_if = 1,
}
const struct Sciclient_rmIrqIf *const tisci_if_navss0_mailbox0_cluster0[]
Definition: sciclient_irq_rm.c:2745

◆ navss0_mailbox0_cluster1_pend_intr_0_3_to_navss0_intr_router_0_in_intr_432_435

const struct Sciclient_rmIrqIf navss0_mailbox0_cluster1_pend_intr_0_3_to_navss0_intr_router_0_in_intr_432_435
Initial value:
= {
.lbase = 0,
.len = 4,
.rid = TISCI_DEV_NAVSS0_INTR_ROUTER_0,
.rbase = 432,
}

◆ tisci_if_navss0_mailbox0_cluster1

const struct Sciclient_rmIrqIf* const tisci_if_navss0_mailbox0_cluster1[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf navss0_mailbox0_cluster1_pend_intr_0_3_to_navss0_intr_router_0_in_intr_432_435
Definition: sciclient_irq_rm.c:2755

◆ tisci_irq_navss0_mailbox0_cluster1

const struct Sciclient_rmIrqNode tisci_irq_navss0_mailbox0_cluster1
static
Initial value:
= {
.id = TISCI_DEV_NAVSS0_MAILBOX0_CLUSTER1,
.n_if = 1,
}
const struct Sciclient_rmIrqIf *const tisci_if_navss0_mailbox0_cluster1[]
Definition: sciclient_irq_rm.c:2761

◆ navss0_mailbox0_cluster2_pend_intr_0_3_to_navss0_intr_router_0_in_intr_428_431

const struct Sciclient_rmIrqIf navss0_mailbox0_cluster2_pend_intr_0_3_to_navss0_intr_router_0_in_intr_428_431
Initial value:
= {
.lbase = 0,
.len = 4,
.rid = TISCI_DEV_NAVSS0_INTR_ROUTER_0,
.rbase = 428,
}

◆ tisci_if_navss0_mailbox0_cluster2

const struct Sciclient_rmIrqIf* const tisci_if_navss0_mailbox0_cluster2[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf navss0_mailbox0_cluster2_pend_intr_0_3_to_navss0_intr_router_0_in_intr_428_431
Definition: sciclient_irq_rm.c:2771

◆ tisci_irq_navss0_mailbox0_cluster2

const struct Sciclient_rmIrqNode tisci_irq_navss0_mailbox0_cluster2
static
Initial value:
= {
.id = TISCI_DEV_NAVSS0_MAILBOX0_CLUSTER2,
.n_if = 1,
}
const struct Sciclient_rmIrqIf *const tisci_if_navss0_mailbox0_cluster2[]
Definition: sciclient_irq_rm.c:2777

◆ navss0_mailbox0_cluster3_pend_intr_0_3_to_navss0_intr_router_0_in_intr_424_427

const struct Sciclient_rmIrqIf navss0_mailbox0_cluster3_pend_intr_0_3_to_navss0_intr_router_0_in_intr_424_427
Initial value:
= {
.lbase = 0,
.len = 4,
.rid = TISCI_DEV_NAVSS0_INTR_ROUTER_0,
.rbase = 424,
}

◆ tisci_if_navss0_mailbox0_cluster3

const struct Sciclient_rmIrqIf* const tisci_if_navss0_mailbox0_cluster3[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf navss0_mailbox0_cluster3_pend_intr_0_3_to_navss0_intr_router_0_in_intr_424_427
Definition: sciclient_irq_rm.c:2787

◆ tisci_irq_navss0_mailbox0_cluster3

const struct Sciclient_rmIrqNode tisci_irq_navss0_mailbox0_cluster3
static
Initial value:
= {
.id = TISCI_DEV_NAVSS0_MAILBOX0_CLUSTER3,
.n_if = 1,
}
const struct Sciclient_rmIrqIf *const tisci_if_navss0_mailbox0_cluster3[]
Definition: sciclient_irq_rm.c:2793

◆ navss0_mailbox0_cluster4_pend_intr_0_3_to_navss0_intr_router_0_in_intr_420_423

const struct Sciclient_rmIrqIf navss0_mailbox0_cluster4_pend_intr_0_3_to_navss0_intr_router_0_in_intr_420_423
Initial value:
= {
.lbase = 0,
.len = 4,
.rid = TISCI_DEV_NAVSS0_INTR_ROUTER_0,
.rbase = 420,
}

◆ tisci_if_navss0_mailbox0_cluster4

const struct Sciclient_rmIrqIf* const tisci_if_navss0_mailbox0_cluster4[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf navss0_mailbox0_cluster4_pend_intr_0_3_to_navss0_intr_router_0_in_intr_420_423
Definition: sciclient_irq_rm.c:2803

◆ tisci_irq_navss0_mailbox0_cluster4

const struct Sciclient_rmIrqNode tisci_irq_navss0_mailbox0_cluster4
static
Initial value:
= {
.id = TISCI_DEV_NAVSS0_MAILBOX0_CLUSTER4,
.n_if = 1,
}
const struct Sciclient_rmIrqIf *const tisci_if_navss0_mailbox0_cluster4[]
Definition: sciclient_irq_rm.c:2809

◆ navss0_mailbox0_cluster5_pend_intr_0_3_to_navss0_intr_router_0_in_intr_416_419

const struct Sciclient_rmIrqIf navss0_mailbox0_cluster5_pend_intr_0_3_to_navss0_intr_router_0_in_intr_416_419
Initial value:
= {
.lbase = 0,
.len = 4,
.rid = TISCI_DEV_NAVSS0_INTR_ROUTER_0,
.rbase = 416,
}

◆ tisci_if_navss0_mailbox0_cluster5

const struct Sciclient_rmIrqIf* const tisci_if_navss0_mailbox0_cluster5[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf navss0_mailbox0_cluster5_pend_intr_0_3_to_navss0_intr_router_0_in_intr_416_419
Definition: sciclient_irq_rm.c:2819

◆ tisci_irq_navss0_mailbox0_cluster5

const struct Sciclient_rmIrqNode tisci_irq_navss0_mailbox0_cluster5
static
Initial value:
= {
.id = TISCI_DEV_NAVSS0_MAILBOX0_CLUSTER5,
.n_if = 1,
}
const struct Sciclient_rmIrqIf *const tisci_if_navss0_mailbox0_cluster5[]
Definition: sciclient_irq_rm.c:2825

◆ navss0_mailbox0_cluster6_pend_intr_0_3_to_navss0_intr_router_0_in_intr_412_415

const struct Sciclient_rmIrqIf navss0_mailbox0_cluster6_pend_intr_0_3_to_navss0_intr_router_0_in_intr_412_415
Initial value:
= {
.lbase = 0,
.len = 4,
.rid = TISCI_DEV_NAVSS0_INTR_ROUTER_0,
.rbase = 412,
}

◆ tisci_if_navss0_mailbox0_cluster6

const struct Sciclient_rmIrqIf* const tisci_if_navss0_mailbox0_cluster6[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf navss0_mailbox0_cluster6_pend_intr_0_3_to_navss0_intr_router_0_in_intr_412_415
Definition: sciclient_irq_rm.c:2835

◆ tisci_irq_navss0_mailbox0_cluster6

const struct Sciclient_rmIrqNode tisci_irq_navss0_mailbox0_cluster6
static
Initial value:
= {
.id = TISCI_DEV_NAVSS0_MAILBOX0_CLUSTER6,
.n_if = 1,
}
const struct Sciclient_rmIrqIf *const tisci_if_navss0_mailbox0_cluster6[]
Definition: sciclient_irq_rm.c:2841

◆ navss0_mailbox0_cluster7_pend_intr_0_3_to_navss0_intr_router_0_in_intr_408_411

const struct Sciclient_rmIrqIf navss0_mailbox0_cluster7_pend_intr_0_3_to_navss0_intr_router_0_in_intr_408_411
Initial value:
= {
.lbase = 0,
.len = 4,
.rid = TISCI_DEV_NAVSS0_INTR_ROUTER_0,
.rbase = 408,
}

◆ tisci_if_navss0_mailbox0_cluster7

const struct Sciclient_rmIrqIf* const tisci_if_navss0_mailbox0_cluster7[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf navss0_mailbox0_cluster7_pend_intr_0_3_to_navss0_intr_router_0_in_intr_408_411
Definition: sciclient_irq_rm.c:2851

◆ tisci_irq_navss0_mailbox0_cluster7

const struct Sciclient_rmIrqNode tisci_irq_navss0_mailbox0_cluster7
static
Initial value:
= {
.id = TISCI_DEV_NAVSS0_MAILBOX0_CLUSTER7,
.n_if = 1,
}
const struct Sciclient_rmIrqIf *const tisci_if_navss0_mailbox0_cluster7[]
Definition: sciclient_irq_rm.c:2857

◆ navss0_mailbox0_cluster8_pend_intr_0_3_to_navss0_intr_router_0_in_intr_404_407

const struct Sciclient_rmIrqIf navss0_mailbox0_cluster8_pend_intr_0_3_to_navss0_intr_router_0_in_intr_404_407
Initial value:
= {
.lbase = 0,
.len = 4,
.rid = TISCI_DEV_NAVSS0_INTR_ROUTER_0,
.rbase = 404,
}

◆ tisci_if_navss0_mailbox0_cluster8

const struct Sciclient_rmIrqIf* const tisci_if_navss0_mailbox0_cluster8[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf navss0_mailbox0_cluster8_pend_intr_0_3_to_navss0_intr_router_0_in_intr_404_407
Definition: sciclient_irq_rm.c:2867

◆ tisci_irq_navss0_mailbox0_cluster8

const struct Sciclient_rmIrqNode tisci_irq_navss0_mailbox0_cluster8
static
Initial value:
= {
.id = TISCI_DEV_NAVSS0_MAILBOX0_CLUSTER8,
.n_if = 1,
}
const struct Sciclient_rmIrqIf *const tisci_if_navss0_mailbox0_cluster8[]
Definition: sciclient_irq_rm.c:2873

◆ navss0_mailbox0_cluster9_pend_intr_0_3_to_navss0_intr_router_0_in_intr_400_403

const struct Sciclient_rmIrqIf navss0_mailbox0_cluster9_pend_intr_0_3_to_navss0_intr_router_0_in_intr_400_403
Initial value:
= {
.lbase = 0,
.len = 4,
.rid = TISCI_DEV_NAVSS0_INTR_ROUTER_0,
.rbase = 400,
}

◆ tisci_if_navss0_mailbox0_cluster9

const struct Sciclient_rmIrqIf* const tisci_if_navss0_mailbox0_cluster9[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf navss0_mailbox0_cluster9_pend_intr_0_3_to_navss0_intr_router_0_in_intr_400_403
Definition: sciclient_irq_rm.c:2883

◆ tisci_irq_navss0_mailbox0_cluster9

const struct Sciclient_rmIrqNode tisci_irq_navss0_mailbox0_cluster9
static
Initial value:
= {
.id = TISCI_DEV_NAVSS0_MAILBOX0_CLUSTER9,
.n_if = 1,
}
const struct Sciclient_rmIrqIf *const tisci_if_navss0_mailbox0_cluster9[]
Definition: sciclient_irq_rm.c:2889

◆ navss0_mailbox0_cluster10_pend_intr_0_3_to_navss0_intr_router_0_in_intr_396_399

const struct Sciclient_rmIrqIf navss0_mailbox0_cluster10_pend_intr_0_3_to_navss0_intr_router_0_in_intr_396_399
Initial value:
= {
.lbase = 0,
.len = 4,
.rid = TISCI_DEV_NAVSS0_INTR_ROUTER_0,
.rbase = 396,
}

◆ tisci_if_navss0_mailbox0_cluster10

const struct Sciclient_rmIrqIf* const tisci_if_navss0_mailbox0_cluster10[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf navss0_mailbox0_cluster10_pend_intr_0_3_to_navss0_intr_router_0_in_intr_396_399
Definition: sciclient_irq_rm.c:2899

◆ tisci_irq_navss0_mailbox0_cluster10

const struct Sciclient_rmIrqNode tisci_irq_navss0_mailbox0_cluster10
static
Initial value:
= {
.id = TISCI_DEV_NAVSS0_MAILBOX0_CLUSTER10,
.n_if = 1,
}
const struct Sciclient_rmIrqIf *const tisci_if_navss0_mailbox0_cluster10[]
Definition: sciclient_irq_rm.c:2905

◆ navss0_mailbox0_cluster11_pend_intr_0_3_to_navss0_intr_router_0_in_intr_392_395

const struct Sciclient_rmIrqIf navss0_mailbox0_cluster11_pend_intr_0_3_to_navss0_intr_router_0_in_intr_392_395
Initial value:
= {
.lbase = 0,
.len = 4,
.rid = TISCI_DEV_NAVSS0_INTR_ROUTER_0,
.rbase = 392,
}

◆ tisci_if_navss0_mailbox0_cluster11

const struct Sciclient_rmIrqIf* const tisci_if_navss0_mailbox0_cluster11[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf navss0_mailbox0_cluster11_pend_intr_0_3_to_navss0_intr_router_0_in_intr_392_395
Definition: sciclient_irq_rm.c:2915

◆ tisci_irq_navss0_mailbox0_cluster11

const struct Sciclient_rmIrqNode tisci_irq_navss0_mailbox0_cluster11
static
Initial value:
= {
.id = TISCI_DEV_NAVSS0_MAILBOX0_CLUSTER11,
.n_if = 1,
}
const struct Sciclient_rmIrqIf *const tisci_if_navss0_mailbox0_cluster11[]
Definition: sciclient_irq_rm.c:2921

◆ navss0_mcrc0_dma_event_intr_0_3_to_navss0_intr_router_0_in_intr_384_387

const struct Sciclient_rmIrqIf navss0_mcrc0_dma_event_intr_0_3_to_navss0_intr_router_0_in_intr_384_387
Initial value:
= {
.lbase = 0,
.len = 4,
.rid = TISCI_DEV_NAVSS0_INTR_ROUTER_0,
.rbase = 384,
}

◆ navss0_mcrc0_int_mcrc_intr_8_8_to_navss0_intr_router_0_in_intr_388_388

const struct Sciclient_rmIrqIf navss0_mcrc0_int_mcrc_intr_8_8_to_navss0_intr_router_0_in_intr_388_388
Initial value:
= {
.lbase = 8,
.len = 1,
.rid = TISCI_DEV_NAVSS0_INTR_ROUTER_0,
.rbase = 388,
}

◆ navss0_mcrc0_dma_event_intr_0_3_to_navss0_udmass_inta0_intaggr_levt_pend_0_3

const struct Sciclient_rmIrqIf navss0_mcrc0_dma_event_intr_0_3_to_navss0_udmass_inta0_intaggr_levt_pend_0_3
Initial value:
= {
.lbase = 0,
.len = 4,
.rid = TISCI_DEV_NAVSS0_UDMASS_INTA0,
.rbase = 0,
}

◆ tisci_if_navss0_mcrc0

const struct Sciclient_rmIrqIf* const tisci_if_navss0_mcrc0[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf navss0_mcrc0_dma_event_intr_0_3_to_navss0_udmass_inta0_intaggr_levt_pend_0_3
Definition: sciclient_irq_rm.c:2943
const struct Sciclient_rmIrqIf navss0_mcrc0_int_mcrc_intr_8_8_to_navss0_intr_router_0_in_intr_388_388
Definition: sciclient_irq_rm.c:2937
const struct Sciclient_rmIrqIf navss0_mcrc0_dma_event_intr_0_3_to_navss0_intr_router_0_in_intr_384_387
Definition: sciclient_irq_rm.c:2931

◆ tisci_irq_navss0_mcrc0

const struct Sciclient_rmIrqNode tisci_irq_navss0_mcrc0
static
Initial value:
= {
.id = TISCI_DEV_NAVSS0_MCRC0,
.n_if = 3,
.p_if = &tisci_if_navss0_mcrc0[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_navss0_mcrc0[]
Definition: sciclient_irq_rm.c:2949

◆ navss0_pvu0_pend_intr_0_0_to_navss0_intr_router_0_in_intr_390_390

const struct Sciclient_rmIrqIf navss0_pvu0_pend_intr_0_0_to_navss0_intr_router_0_in_intr_390_390
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_NAVSS0_INTR_ROUTER_0,
.rbase = 390,
}

◆ tisci_if_navss0_pvu0

const struct Sciclient_rmIrqIf* const tisci_if_navss0_pvu0[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf navss0_pvu0_pend_intr_0_0_to_navss0_intr_router_0_in_intr_390_390
Definition: sciclient_irq_rm.c:2961

◆ tisci_irq_navss0_pvu0

const struct Sciclient_rmIrqNode tisci_irq_navss0_pvu0
static
Initial value:
= {
.id = TISCI_DEV_NAVSS0_PVU0,
.n_if = 1,
.p_if = &tisci_if_navss0_pvu0[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_navss0_pvu0[]
Definition: sciclient_irq_rm.c:2967

◆ navss0_pvu1_pend_intr_0_0_to_navss0_intr_router_0_in_intr_389_389

const struct Sciclient_rmIrqIf navss0_pvu1_pend_intr_0_0_to_navss0_intr_router_0_in_intr_389_389
Initial value:
= {
.lbase = 0,
.len = 1,
.rid = TISCI_DEV_NAVSS0_INTR_ROUTER_0,
.rbase = 389,
}

◆ tisci_if_navss0_pvu1

const struct Sciclient_rmIrqIf* const tisci_if_navss0_pvu1[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf navss0_pvu1_pend_intr_0_0_to_navss0_intr_router_0_in_intr_389_389
Definition: sciclient_irq_rm.c:2977

◆ tisci_irq_navss0_pvu1

const struct Sciclient_rmIrqNode tisci_irq_navss0_pvu1
static
Initial value:
= {
.id = TISCI_DEV_NAVSS0_PVU1,
.n_if = 1,
.p_if = &tisci_if_navss0_pvu1[0],
}
const struct Sciclient_rmIrqIf *const tisci_if_navss0_pvu1[]
Definition: sciclient_irq_rm.c:2983

◆ navss0_udmass_inta0_intaggr_vintr_pend_0_255_to_navss0_intr_router_0_in_intr_0_255

const struct Sciclient_rmIrqIf navss0_udmass_inta0_intaggr_vintr_pend_0_255_to_navss0_intr_router_0_in_intr_0_255
Initial value:
= {
.lbase = 0,
.len = 256,
.rid = TISCI_DEV_NAVSS0_INTR_ROUTER_0,
.rbase = 0,
}

◆ tisci_if_navss0_udmass_inta0

const struct Sciclient_rmIrqIf* const tisci_if_navss0_udmass_inta0[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf navss0_udmass_inta0_intaggr_vintr_pend_0_255_to_navss0_intr_router_0_in_intr_0_255
Definition: sciclient_irq_rm.c:2993

◆ tisci_irq_navss0_udmass_inta0

const struct Sciclient_rmIrqNode tisci_irq_navss0_udmass_inta0
static
Initial value:
= {
.id = TISCI_DEV_NAVSS0_UDMASS_INTA0,
.n_if = 1,
}
const struct Sciclient_rmIrqIf *const tisci_if_navss0_udmass_inta0[]
Definition: sciclient_irq_rm.c:2999

◆ navss0_modss_inta0_intaggr_vintr_pend_0_63_to_navss0_intr_router_0_in_intr_320_383

const struct Sciclient_rmIrqIf navss0_modss_inta0_intaggr_vintr_pend_0_63_to_navss0_intr_router_0_in_intr_320_383
Initial value:
= {
.lbase = 0,
.len = 64,
.rid = TISCI_DEV_NAVSS0_INTR_ROUTER_0,
.rbase = 320,
}

◆ tisci_if_navss0_modss_inta0

const struct Sciclient_rmIrqIf* const tisci_if_navss0_modss_inta0[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf navss0_modss_inta0_intaggr_vintr_pend_0_63_to_navss0_intr_router_0_in_intr_320_383
Definition: sciclient_irq_rm.c:3009

◆ tisci_irq_navss0_modss_inta0

const struct Sciclient_rmIrqNode tisci_irq_navss0_modss_inta0
static
Initial value:
= {
.id = TISCI_DEV_NAVSS0_MODSS_INTA0,
.n_if = 1,
}
const struct Sciclient_rmIrqIf *const tisci_if_navss0_modss_inta0[]
Definition: sciclient_irq_rm.c:3015

◆ navss0_modss_inta1_intaggr_vintr_pend_0_63_to_navss0_intr_router_0_in_intr_256_319

const struct Sciclient_rmIrqIf navss0_modss_inta1_intaggr_vintr_pend_0_63_to_navss0_intr_router_0_in_intr_256_319
Initial value:
= {
.lbase = 0,
.len = 64,
.rid = TISCI_DEV_NAVSS0_INTR_ROUTER_0,
.rbase = 256,
}

◆ tisci_if_navss0_modss_inta1

const struct Sciclient_rmIrqIf* const tisci_if_navss0_modss_inta1[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf navss0_modss_inta1_intaggr_vintr_pend_0_63_to_navss0_intr_router_0_in_intr_256_319
Definition: sciclient_irq_rm.c:3025

◆ tisci_irq_navss0_modss_inta1

const struct Sciclient_rmIrqNode tisci_irq_navss0_modss_inta1
static
Initial value:
= {
.id = TISCI_DEV_NAVSS0_MODSS_INTA1,
.n_if = 1,
}
const struct Sciclient_rmIrqIf *const tisci_if_navss0_modss_inta1[]
Definition: sciclient_irq_rm.c:3031

◆ navss0_intr_router_0_outl_intr_136_143_to_icss_g_main_1_bus_pr1_slv_intr_46_53

const struct Sciclient_rmIrqIf navss0_intr_router_0_outl_intr_136_143_to_icss_g_main_1_bus_pr1_slv_intr_46_53
Initial value:
= {
.lbase = 136,
.len = 8,
.rid = TISCI_DEV_PRU_ICSSG1,
.rbase = 46,
}

◆ navss0_intr_router_0_outl_intr_128_135_to_icss_g_main_0_bus_pr1_slv_intr_46_53

const struct Sciclient_rmIrqIf navss0_intr_router_0_outl_intr_128_135_to_icss_g_main_0_bus_pr1_slv_intr_46_53
Initial value:
= {
.lbase = 128,
.len = 8,
.rid = TISCI_DEV_PRU_ICSSG0,
.rbase = 46,
}

◆ navss0_intr_router_0_outl_intr_0_63_to_gic500ss_main_0_bus_spi_64_127

const struct Sciclient_rmIrqIf navss0_intr_router_0_outl_intr_0_63_to_gic500ss_main_0_bus_spi_64_127
Initial value:
= {
.lbase = 0,
.len = 64,
.rid = TISCI_DEV_GIC0,
.rbase = 64,
}

◆ navss0_intr_router_0_outl_intr_64_119_to_gic500ss_main_0_bus_spi_448_503

const struct Sciclient_rmIrqIf navss0_intr_router_0_outl_intr_64_119_to_gic500ss_main_0_bus_spi_448_503
Initial value:
= {
.lbase = 64,
.len = 56,
.rid = TISCI_DEV_GIC0,
.rbase = 448,
}

◆ navss0_intr_router_0_outl_intr_144_151_to_icss_g_main_2_bus_pr1_slv_intr_46_53

const struct Sciclient_rmIrqIf navss0_intr_router_0_outl_intr_144_151_to_icss_g_main_2_bus_pr1_slv_intr_46_53
Initial value:
= {
.lbase = 144,
.len = 8,
.rid = TISCI_DEV_PRU_ICSSG2,
.rbase = 46,
}

◆ navss0_intr_router_0_outl_intr_120_127_to_main2mcu_lvl_introuter_main_0_bus_in_184_191

const struct Sciclient_rmIrqIf navss0_intr_router_0_outl_intr_120_127_to_main2mcu_lvl_introuter_main_0_bus_in_184_191
Initial value:
= {
.lbase = 120,
.len = 8,
.rid = TISCI_DEV_MAIN2MCU_LVL_INTRTR0,
.rbase = 184,
}

◆ tisci_if_navss0_intr_router_0

const struct Sciclient_rmIrqIf* const tisci_if_navss0_intr_router_0[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf navss0_intr_router_0_outl_intr_64_119_to_gic500ss_main_0_bus_spi_448_503
Definition: sciclient_irq_rm.c:3059
const struct Sciclient_rmIrqIf navss0_intr_router_0_outl_intr_128_135_to_icss_g_main_0_bus_pr1_slv_intr_46_53
Definition: sciclient_irq_rm.c:3047
const struct Sciclient_rmIrqIf navss0_intr_router_0_outl_intr_120_127_to_main2mcu_lvl_introuter_main_0_bus_in_184_191
Definition: sciclient_irq_rm.c:3071
const struct Sciclient_rmIrqIf navss0_intr_router_0_outl_intr_144_151_to_icss_g_main_2_bus_pr1_slv_intr_46_53
Definition: sciclient_irq_rm.c:3065
const struct Sciclient_rmIrqIf navss0_intr_router_0_outl_intr_136_143_to_icss_g_main_1_bus_pr1_slv_intr_46_53
Definition: sciclient_irq_rm.c:3041
const struct Sciclient_rmIrqIf navss0_intr_router_0_outl_intr_0_63_to_gic500ss_main_0_bus_spi_64_127
Definition: sciclient_irq_rm.c:3053

◆ tisci_irq_navss0_intr_router_0

const struct Sciclient_rmIrqNode tisci_irq_navss0_intr_router_0
static
Initial value:
= {
.id = TISCI_DEV_NAVSS0_INTR_ROUTER_0,
.n_if = 6,
}
const struct Sciclient_rmIrqIf *const tisci_if_navss0_intr_router_0[]
Definition: sciclient_irq_rm.c:3077

◆ mcu_navss0_intr_aggr_0_intaggr_vintr_pend_0_255_to_mcu_navss0_intr_router_0_in_intr_0_255

const struct Sciclient_rmIrqIf mcu_navss0_intr_aggr_0_intaggr_vintr_pend_0_255_to_mcu_navss0_intr_router_0_in_intr_0_255
Initial value:
= {
.lbase = 0,
.len = 256,
.rid = TISCI_DEV_MCU_NAVSS0_INTR_ROUTER_0,
.rbase = 0,
}

◆ tisci_if_mcu_navss0_intr_aggr_0

const struct Sciclient_rmIrqIf* const tisci_if_mcu_navss0_intr_aggr_0[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf mcu_navss0_intr_aggr_0_intaggr_vintr_pend_0_255_to_mcu_navss0_intr_router_0_in_intr_0_255
Definition: sciclient_irq_rm.c:3092

◆ tisci_irq_mcu_navss0_intr_aggr_0

const struct Sciclient_rmIrqNode tisci_irq_mcu_navss0_intr_aggr_0
static
Initial value:
= {
.id = TISCI_DEV_MCU_NAVSS0_INTR_AGGR_0,
.n_if = 1,
}
const struct Sciclient_rmIrqIf *const tisci_if_mcu_navss0_intr_aggr_0[]
Definition: sciclient_irq_rm.c:3098

◆ mcu_navss0_intr_router_0_outl_intr_0_31_to_mcu_armss0_cpu0_bus_intr_64_95

const struct Sciclient_rmIrqIf mcu_navss0_intr_router_0_outl_intr_0_31_to_mcu_armss0_cpu0_bus_intr_64_95
Initial value:
= {
.lbase = 0,
.len = 32,
.rid = TISCI_DEV_MCU_ARMSS0_CPU0,
.rbase = 64,
}

◆ mcu_navss0_intr_router_0_outl_intr_32_63_to_mcu_armss0_cpu1_bus_intr_64_95

const struct Sciclient_rmIrqIf mcu_navss0_intr_router_0_outl_intr_32_63_to_mcu_armss0_cpu1_bus_intr_64_95
Initial value:
= {
.lbase = 32,
.len = 32,
.rid = TISCI_DEV_MCU_ARMSS0_CPU1,
.rbase = 64,
}

◆ tisci_if_mcu_navss0_intr_router_0

const struct Sciclient_rmIrqIf* const tisci_if_mcu_navss0_intr_router_0[]
Initial value:
= {
}
const struct Sciclient_rmIrqIf mcu_navss0_intr_router_0_outl_intr_32_63_to_mcu_armss0_cpu1_bus_intr_64_95
Definition: sciclient_irq_rm.c:3114
const struct Sciclient_rmIrqIf mcu_navss0_intr_router_0_outl_intr_0_31_to_mcu_armss0_cpu0_bus_intr_64_95
Definition: sciclient_irq_rm.c:3108

◆ tisci_irq_mcu_navss0_intr_router_0

const struct Sciclient_rmIrqNode tisci_irq_mcu_navss0_intr_router_0
static
Initial value:
= {
.id = TISCI_DEV_MCU_NAVSS0_INTR_ROUTER_0,
.n_if = 2,
}
const struct Sciclient_rmIrqIf *const tisci_if_mcu_navss0_intr_router_0[]
Definition: sciclient_irq_rm.c:3120

◆ gRmIrqTree

const struct Sciclient_rmIrqNode* const gRmIrqTree[]

◆ gRmIrqTreeCount

const uint32_t gRmIrqTreeCount = sizeof(gRmIrqTree)/sizeof(gRmIrqTree[0])