58 #define IPC_VRING_BUFFER_SIZE (0x200000) 61 #define IPC_MPU1_0 (0) 62 #define IPC_MCU1_0 (1) 63 #define IPC_MCU1_1 (2) 64 #define IPC_MAX_PROCS (3) 66 #define IPC_MAILBOX_CLUSTER_CNT (12U) 67 #define IPC_MAILBOX_USER_CNT (4U) 68 #define MAIN_NAVSS_MAILBOX_INPUTINTR_MAX (440U) 69 #define MAIN_NAVSS_MAILBOX_OUTPUTINTR_MAX (512U) 71 #define IPC_MCU_NAVSS0_INTR0_CFG_BASE (CSL_NAVSS0_INTR0_INTR_ROUTER_CFG_BASE) 74 #define NAVSS512_MPU1_0_OUTPUT_OFFSET (112) 75 #define NAVSS512_MCU1R5F0_OUTPUT_OFFSET (120) 76 #define NAVSS512_MCU1R5F1_OUTPUT_OFFSET (121) 78 #define MAIN2MCU0_INTR_ROUTER_INPUT_BASE (184) 79 #define MAIN2MCU1_INTR_ROUTER_INPUT_BASE (186) 81 #define MAIN2MCU0_INTR_ROUTER_OUTPUT_BASE (0) 82 #define MAIN2MCU1_INTR_ROUTER_OUTPUT_BASE (1) 108 #ifdef IPC_SUPPORT_SCICLIENT 109 int32_t Ipc_sciclientIrqRelease(uint16_t remoteId, uint32_t clusterId,
110 uint32_t userId, uint32_t intNumber);
111 int32_t Ipc_sciclientIrqSet(uint16_t remoteId, uint32_t clusterId,
112 uint32_t userId, uint32_t intNumber);
115 uint16_t *rangeNumP);
Mailbox interrupt router configuration.
Definition: ipc_types.h:113
int32_t Ipc_main2mcu_intRouter(Ipc_MbConfig *cfg)
int32_t Ipc_getIntNumRange(uint32_t coreIndex, uint16_t *rangeStartP, uint16_t *rangeNumP)