6.1.14. AM335x to AM437x Hardware Migration Guide¶

6.1.14.3.1.1. ARM Core¶

AM335x is based on the ARM Cortex-A8 processor. AM437x is based on the ARM Cortex-A9 processor. The table below shows a comparison between these two devices.

Note: Please refer to the AM335x and AM437x Datasheets for the latest OPP values.

6.1.14.3.1.2. Neon Co-processor¶

The Neon co-processor is the same between the two devices.

6.1.14.3.1.3. Graphics Engine¶

The SGX530 3D Graphics Engine is the same between both devices.

6.1.14.3.1.4. System DMA¶

AM437x has a new DMA event mapping corresponding to the supported peripherals on this device. Additionally, AM335x has 32 events in the cross bar and AM437x has 64.

6.1.14.3.1.5. On-Chip Memory¶

AM335x has 64KB of general purpose on-chip memory controller (OCMC) RAM. AM437x has 256KB of general purpose on-chip memory controller (OCMC) RAM.

6.1.14.3.2.1. General Purpose Memory Controller¶

Both AM335x and AM437x support 7 chip selects.

6.1.14.3.2.2. External Memory Interface¶

AM335x supports a single 16-bit LPDDR (mDDR)/DDR2/DDR3 SDRAM Interface, with up to:

• LPDDR 200-MHz Clock (400-MHz Data Rate)
• DDR2 266-MHz Clock (532-MHz Data Rate)
• DDR3 400-MHz Clock (800-MHz Data Rate)
• DDR3L 400-MHz Clock (800-MHz Data Rate)

One x32 device or two x16 devices and 1 GB (total) of address space are supported.

AM437x supports a single 32-bit LPDDR2(discrete or non-POP)/DDR3L/DDR3 SDRAM Interface, with up to:

• LPDDR2: 266-MHz Clock (LPDDR2-533 Data Rate)
• DDR3: 400-MHz Clock ( DDR3-800 Data Rate)
• DDR3L: 400-MHz Clock (DDR3L-800 Data Rate)

One x32 device, two x16 devices, or four 8x devices and 2 GB (total) of address space are supported.

6.1.14.3.2.3. EMIF Tool¶

The DDR configuration between AM437x and AM335x is different and please refer to the following guide

6.1.14.3.3.1. Operating Performance Points¶

Note: Please refer to the AM335x and AM437x Datasheets for the latest OPP values.

6.1.14.3.3.2. Voltage Rails¶

The following table compares the power supplies for AM335x and AM437x:

Table: AM335x Voltage Rails

* Note: These voltage rails are not available in the 13x13 package.

Table: AM437x Voltage Rails

* Note: Please refer to the AM437x Datasheet for the latest values.

6.1.14.3.3.3. Input Clocks¶

Table: AM335x Input Clocks

Table: AM437x Input Clocks

6.1.14.3.3.4. PLLs¶

AM335x has the following PLLs, driven by a crystal (CLK_M_OSC):

• Core PLL - for SGX, EMAC, L3S, L3F, L4F, L4_PER, L4_WKUP, PRU-ICSS IEP, Debugss
• Peripheral (Per) PLL - for USB PHY, PRU-ICSS UART, MMC/SD, SPI, I2C, UART
• MPU PLL - for MPU Subsystem (includes Cortex A-8)
• Display PLL - for LCD Pixel Clock
• DDR PLL - for EMIF

AM437x has the following PLLs, driven by a crystal (CLK_M_OSC):

• Core PLL - for SGX, L3S, L3F, L4F, L4F_PER, PRU_ICSS_IEP, Debugss, GEMAC, PRU_ICSS OCP
• Peripheral (Per) PLL - for PRU_ICSS_UART, MMC/SD, SPI, UART, I2C
• MPU PLL - for MPU Subsystem (includes Cortex A-9)
• Display PLL - for LCD Pixel Clock
• DDR PLL - for EMIF

6.1.14.3.3.5. Power Management Feature Comparison¶

* On 13x13 mm package option, VDD_CORE and VDD_MPU are merged.

6.1.14.3.3.6. Bootmodes¶

6.1.14.3.4.1. LCDC vs DSS¶

The below image provides a brief summary of the differences between LCDC and DSS. Please refer to the TRM for more information.

• The following page contains more information LCDC
• The following page contains more information on DSS

6.1.14.3.4.2. DSS FIFO Underflow¶

# Set Output Resolution
optargs=video=HDMI-A-1:800x600

# A9 limiter = 700MBPS
a9_limiter=mw.l 0x44005208 0x10; md 0x44005208 0x1; mw.l 0x4400520C 0x3; md 0x4400520C 0x1; mw.l 0x44005210 0x0; md 0x44005210 1

# EMIF COS
# mw.l 0x4C000108 0x80000000;
emif_cos=mw.l 0x4C000120 0x80000405; md 0x4C000120 1; mw.l 0x4C000104 0x80000094; md 0x4C000104 1; md 0x4C000108 1; mw.l 0x4C000100 0x80000009; md 0x4C000100 1; mw.l 0x4C000124 0x000FFFFF; md 0x4C000124 1

# DSS MREQ Prio
mreq_prio=mw.l 0x44E10670 0x44444477; md 0x44E10670 1; mw.l 0x44E10674 0x00444400; md 0x44E10674 1

uenvcmd= run a9_limiter; run emif_cos; run mreq_prio;

diff --git a/drivers/video/fbdev/omap2/omapfb/dss/apply.c b/drivers/video/fbdev/omap2/omapfb/dss/apply.c
index 2481f4871f..46b68b21df 100644
--- a/drivers/video/fbdev/omap2/omapfb/dss/apply.c
+++ b/drivers/video/fbdev/omap2/omapfb/dss/apply.c
@@ -1039,6 +1039,10 @@ static void dss_ovl_setup_fifo(struct omap_overlay *ovl)

        if (!op->enabled && !op->enabling)
                return;
+       if (dss_has_feature(FEAT_FIFO_SZ_LIMITATION)) {
+               use_fifo_merge = true;
+               dispc_enable_fifomerge(use_fifo_merge);
+       }

        dispc_ovl_compute_fifo_thresholds(ovl->id, &fifo_low, &fifo_high,
                        use_fifo_merge, ovl_manual_update(ovl));
diff --git a/drivers/video/fbdev/omap2/omapfb/dss/dispc.c b/drivers/video/fbdev/omap2/omapfb/dss/dispc.c
index a06d9c2576..e6292a856c 100644
--- a/drivers/video/fbdev/omap2/omapfb/dss/dispc.c
+++ b/drivers/video/fbdev/omap2/omapfb/dss/dispc.c
@@ -1329,7 +1329,7 @@ void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
                *fifo_low = 0;
                *fifo_high = burst_size;
        } else {
-               *fifo_low = ovl_fifo_size - burst_size;
+               *fifo_low = total_fifo_size - burst_size;
                *fifo_high = total_fifo_size - buf_unit;
        }
 }
diff --git a/drivers/video/fbdev/omap2/omapfb/dss/dss_features.c b/drivers/video/fbdev/omap2/omapfb/dss/dss_features.c
index e8d428bc47..6cffe132dc 100644
--- a/drivers/video/fbdev/omap2/omapfb/dss/dss_features.c
+++ b/drivers/video/fbdev/omap2/omapfb/dss/dss_features.c
@@ -521,6 +521,7 @@ static const enum dss_feat_id am43xx_dss_feat_list[] = {
        FEAT_FIR_COEF_V,
        FEAT_ALPHA_FIXED_ZORDER,
        FEAT_FIFO_MERGE,
+       FEAT_FIFO_SZ_LIMITATION,
 };

 static const enum dss_feat_id omap3630_dss_feat_list[] = {
diff --git a/drivers/video/fbdev/omap2/omapfb/dss/dss_features.h b/drivers/video/fbdev/omap2/omapfb/dss/dss_features.h
index 3d67d39f19..433d925662 100644
--- a/drivers/video/fbdev/omap2/omapfb/dss/dss_features.h
+++ b/drivers/video/fbdev/omap2/omapfb/dss/dss_features.h
@@ -62,6 +62,9 @@ enum dss_feat_id {
        FEAT_BURST_2D,
        FEAT_DSI_PHY_DCC,
        FEAT_MFLAG,
+       /* When DSS has to be used with all FIFO's merged */
+    +   /* due to bandwidth constraints */
+    +   FEAT_FIFO_SZ_LIMITATION,
 };

 /* DSS register field id */

6.1.14.3.5.1. MMC/SD¶

The MMC/SD modules are binary compatible between the two devices. Except, the CLK32 debounce clock is created by dividing the 96-MHz (48-MHz in AM437x) clock in the PRCM by two and then dividing the resulting 48-MHz (24-MHz in AM437x) clock by a fixed 732.4219 in the Control Module to get a 32-kHz clock.

* Note the supported data width is subject to pinmux constraints.

6.1.14.3.5.2. USB¶

The AM335x has 2 MUSB controllers that have a USB port capable of host and OTG operations and have an integrated PHY that supports HS, FS and LS. The AM437x contains two USB 2.0 dual-role-device (DRD) subsystems, either of which can be configured as an xHCI Host (HS, FS, LS supported) or as a Device (HS and FS supported).

6.1.14.3.5.3. I2C¶

The I2C ports are binary compatible between the two devices. Both devices support 3 general I2C ports. The ports only support 100/400Kbps operation. No high speed mode is supported.

6.1.14.3.5.4. UART¶

On AM335x and AM437x, only UART1 supports full modem control. All 6 UARTs support a maximum baud rate of 3.6864 Mbps.

The UART interface clock (CLK) is sourced from CORE_CLKOUTM4 / 2 in AM335x and AM437x (max 100-MHz) except for UART0 on AM437x that is sourced from M_OSC_CLK in AM437x (max 26-MHz).

6.1.14.3.5.5. Real-Time Clock (RTC)¶

The RTC module is identical between the two devices, except for the interface clock source – AM335x uses CORE_CLKOUTM4/2, providing a max frequency of 100 MHz. AM437x uses CLK_M_OSC, providing a max frequency of 26 MHz.

6.1.14.3.5.6. Ethernet¶

There are small differences between the AM335x and AM437x Ethernet module.

The AM437x module adds support for multi core split processing, connecting the Core 0 interrupt to the MPU subsystem and the Core 2 interrupt to the PRU-ICSS. On AM335x, the Core 0 interrupt was connected to both the MPU subsystem and the PRU-ICSS. Core 1 and Core 2 interrupts were unconnected.

In AM437x, the cpts_rft_clk (IEEE 1588v2 clock) adds DISP_PLL_CLK as a third source option.

6.1.14.3.5.7. McSPI¶

AM335x includes 2 McSPI ports, each with two chip select signals. All McSPI have 4 DMA requests to EDMA.

AM437x includes 5 McSPI ports. McSPI[0-2] support 4 chip select signals and 8 DMA requests to the eDMA. McSPI[3-4] only support 2 CS signals and 4 DMA requests to the eDMA.

6.1.14.3.5.8. PWM Subsystem (PWMSS)¶

The PWM Subsystem contains PWM, eCAP, and eQEP submodules. AM335x has 3 PWMSS instances. AM437x has 6 PWMSS instances, but eCAP3-5 and eQEP3-5 are not used.

The PWMSS synchronization of the PWM and eCAP submodules is also different between AM335x and AM437x.

6.1.14.3.5.9. PRU-ICSS - Programmable Real-time Unit Subsystem and Industrial Communications Subsystem¶

AM335x has one PRU-ICSS and AM437x has two PRU-ICSS. The PRU-ICSS on AM437x is backwards compatible with the subsystem on AM335x. The table below summarizes the differences between the PRU-ICSS instances on each device.

6.1.14.3.6.1. GPTimer¶

AM335x has 7 General Purpose Timers. One GPTimer (DMTIMER1) is specialized for accurate 1mS OS Ticks. Only 4 GPTimers (DMTIMER4 - DMTIMER7) are extended to SoC pins.

AM437x has 12 General Purpose Timers. One GPTimer (DMTIMER1) is specialized for accurate 1mS OS Ticks. Only 6 GPTimers (DMTIMER0, DMTIMER1, DMTIMER4 - DMTIMER7) are extended to SoC pins. AM437x also adds support for timer cascading, providing a 64-bit timer option. With this feature, DMTIMER2-3 provide a 64-bit internal timer and DMTIMER4-5 provide a 64-bit timer with output capability.

6.1.14.3.6.2. WDTimer¶

AM335x and AM437x both have one watchdog timer.

Additionally, the interface clock source is different between the two devices. AM335x uses CORE_CLKOUTM4/2, providing a max frequency of 100 MHz. AM437x uses CLK_M_OSC, providing a max frequency of 26 MHz.

6.1.14.3.7.1. GPIOs¶

AM335x has 4 banks of GPIOs, each with 32 dedicated IO pins. With the 4 GPIO modules, AM335x allows for a maximum of 128 GPIO pins. Supports a single DMA request for GPIO[0:2].

AM437x has 6 banks of GPIOs, each with 32 dedicated IO pins. With the 6 GPIO modules, AM437x allows for a maximum of 192 GPIO pins. Supports a single DMA request for each GPIO module.