4.1.8. How to enable display sharing between remote core and Linux

4.1.8.1. Introduction

The AM62P SoC supports display sharing where multiple processing cores can simultaneously utilize display resources as desrcibed in DSS driver documentation

The DSS partitioning scheme can be tailored based on the end-use case requirement and the display sharing properties can be set accordingly as demonstrated in below examples :

4.1.8.2. Examples

4.1.8.2.1. Linux owning one video plane

Resource	Linux	Remote Core
Register space	Common1	Common
Video port	VP1 (shared)	VP1 (owned)
Video Pipeline	Vid	Vidl
Zorder	0	1

For this scenario where Linux owns one video pipeline and remote core controls rest of the display resources, user can update the display hardware device tree node as shown below :

&dss0 {
        ti,dss-shared-mode;
        ti,dss-shared-mode-vp = "vp1";
        ti,dss-shared-mode-vp-owned = <0>;
        ti,dss-shared-mode-common = "common1";
        ti,dss-shared-mode-planes = "vid";
        ti,dss-shared-mode-plane-zorder = <0>;
        interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
};

This scheme is useful for scenario where both Linux and remote core want to display over same peripheral using different video planes.

Note

Here it is assumed that remote core is running firmware which honors above display partitioning scheme by programming video port using a separate register region i.e. “common” and using separate video pipeline i.e. vidl.

Note

There is an out of box example available which uses this configuration to demonstrate display sharing between Linux and RTOS using display supported RTOS firmware and Linux devicetree overlay file k3-am62p5-sk-dss-shared-mode.dtbo

For more details please refer Display Cluster User Guide

4.1.8.2.2. Linux owning one full pipeline

Resource	Linux	Remote Core
Register space	Common1	Common
Video port	VP1 (Owned)	VP2 (Owned)
Video Pipeline	Vid	Vidl
Zorder	0	1

For this scenario where Linux owns one full display pipeline involving a video port, overlay manager and a video pipeline with remote core also controlling full display pipeline with albeit using a separate video port, below device tree node configuration can be used :

&dss0 {
        ti,dss-shared-mode;
        ti,dss-shared-mode-vp = "vp1";
        ti,dss-shared-mode-vp-owned = <1>;
        ti,dss-shared-mode-common = "common1";
        ti,dss-shared-mode-planes = "vid";
        ti,dss-shared-mode-plane-zorder = <0>;
        interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
};

Note

Here it is assumed that remote core is running a custom firmware which honors above display partitioning scheme by programming a separate video port using a separate register region i.e. “common” and using separate video pipeline i.e. vidl.