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AM263x MCU+ SDK
09.02.00
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Go to the documentation of this file.
39 #ifndef SDL_MSS_CR5_SOC_H_
40 #define SDL_MSS_CR5_SOC_H_
46 #include <sdl/include/am263x/sdlr_soc_baseaddress.h>
47 #include <sdl/include/am263x/sdlr_mss_ctrl.h>
56 #define SDL_ECC_BUS_SAFETY_MSS_BUS_CFG (uint32_t)SDL_MSS_CTRL_U_BASE
58 #define SDL_MSS_CTRL_R5SS0_CORE0_AHB_BASE (0x000000A0U)
59 #define SDL_MSS_CTRL_R5SS1_CORE0_AHB_BASE (0x000000A4U)
60 #define SDL_MSS_CTRL_R5SS0_CORE1_AHB_BASE (0x000000B0U)
61 #define SDL_MSS_CTRL_R5SS1_CORE1_AHB_BASE (0x000000B4U)
62 #define SDL_MSS_CTRL_R5SS0_CORE0_AHB_END (SDL_MSS_CTRL_R5SS0_CORE0_AHB_BASE + SDL_MSS_CTRL_R5SS0_CORE0_AHB_SIZE)
63 #define SDL_MSS_CTRL_R5SS1_CORE0_AHB_END (SDL_MSS_CTRL_R5SS1_CORE0_AHB_BASE + SDL_MSS_CTRL_R5SS1_CORE0_AHB_SIZE)
64 #define SDL_MSS_CTRL_R5SS0_CORE1_AHB_END (SDL_MSS_CTRL_R5SS0_CORE1_AHB_BASE + SDL_MSS_CTRL_R5SS0_CORE1_AHB_SIZE)
65 #define SDL_MSS_CTRL_R5SS1_CORE1_AHB_END (SDL_MSS_CTRL_R5SS1_CORE1_AHB_BASE + SDL_MSS_CTRL_R5SS1_CORE1_AHB_SIZE)
67 #define SDL_R5SS0_CORE0_TCMA_U_SIZE (0x000000020)
68 #define SDL_R5SS0_CORE0_TCMB_U_SIZE (0x000000020)
69 #define SDL_MSS_CR5A_TCM_U_BASE (SDL_R5SS0_CORE0_TCMA_U_BASE )
70 #define SDL_MSS_CR5B_TCM_U_BASE (SDL_R5SS0_CORE0_TCMB_U_BASE )
71 #define SDL_MSS_CR5A_TCM_U_END (SDL_R5SS0_CORE0_TCMA_U_BASE + SDL_R5SS0_CORE0_TCMA_U_SIZE)
72 #define SDL_MSS_CR5B_TCM_U_END (SDL_R5SS0_CORE0_TCMB_U_BASE + SDL_R5SS0_CORE0_TCMB_U_SIZE)
73 #define SDL_MBOX_SRAM_U_BASE_END (SDL_MBOX_SRAM_U_BASE+100U)
74 #define SDL_MMC0_U_BASE_END (SDL_MMC0_U_BASE+0X1FFCU-DWORD)
75 #define SDL_GPMC0_CFG_U_BASE_END (SDL_GPMC0_CFG_U_BASE+0X3FCU-DWORD)
76 #define SDL_CORE_VBUSP_START (0x50800000U)
77 #define SDL_CORE_VBUSP_START_END (SDL_CORE_VBUSP_START+0X1FFCU)
78 #define SDL_PERI_VBUSP_START (0x50200000)
79 #define SDL_PERI_VBUSP_START_END (SDL_PERI_VBUSP_START+0X7FFFFCU)
80 #define SDL_MPU_L2OCRAM_BANK0 (0x40020000U)
81 #define SDL_MPU_L2OCRAM_BANK0_END (0x40020FFFU-DWORD)
82 #define SDL_MPU_L2OCRAM_BANK1 (0x40040000U)
83 #define SDL_MPU_L2OCRAM_BANK1_END (0x40040FFFU-DWORD)
84 #define SDL_MPU_L2OCRAM_BANK2 (0x40060000U)
85 #define SDL_MPU_L2OCRAM_BANK2_END (0x40060FFFU-DWORD)
86 #define SDL_MPU_L2OCRAM_BANK3 (0x40080000U)
87 #define SDL_MPU_L2OCRAM_BANK3_END (0x40080FFFU-DWORD)
88 #define SDL_MSS_QSPI_U_BASE (SDL_QSPI0_U_BASE)
89 #define SDL_MSS_QSPI_U_SIZE (0x000001D8U)
90 #define SDL_MSS_QSPI_U_END (SDL_MSS_QSPI_U_BASE + SDL_MSS_QSPI_U_SIZE)
91 #define SDL_MSS_MCRC_U_BASE (SDL_MCRC0_U_BASE)
92 #define SDL_MSS_MCRC_U_SIZE (0x000001E4U)
93 #define SDL_MSS_MCRC_U_END (SDL_MSS_MCRC_U_BASE + SDL_MSS_MCRC_U_SIZE)
94 #define SDL_MSS_STM_STIM_U_BASE (SDL_STM_STIM_U_BASE)
95 #define SDL_MSS_STM_STIM_U_SIZE (0x00FFFFFFU)
96 #define SDL_MSS_STM_STIM_U_END (SDL_MSS_STM_STIM_U_BASE + SDL_MSS_STM_STIM_U_SIZE)
99 #define SDL_ECC_BUS_SAFETY_MSS_MBOX 0U
100 #define SDL_ECC_BUS_SAFETY_MSS_TPTC_A0_RD 1U
101 #define SDL_ECC_BUS_SAFETY_MSS_TPTC_A1_RD 2U
102 #define SDL_ECC_BUS_SAFETY_MSS_CR5A_AXI_RD 3U
103 #define SDL_ECC_BUS_SAFETY_MSS_CR5B_AXI_RD 4U
104 #define SDL_ECC_BUS_SAFETY_MSS_CR5C_AXI_RD 5U
105 #define SDL_ECC_BUS_SAFETY_MSS_CR5D_AXI_RD 6U
106 #define SDL_ECC_BUS_SAFETY_MSS_CR5A_AXI_S 7U
107 #define SDL_ECC_BUS_SAFETY_MSS_CR5B_AXI_S 8U
108 #define SDL_ECC_BUS_SAFETY_MSS_CR5C_AXI_S 9U
109 #define SDL_ECC_BUS_SAFETY_MSS_CR5D_AXI_S 10U
110 #define SDL_ECC_BUS_SAFETY_MSS_TPTC_A0_WR 11U
111 #define SDL_ECC_BUS_SAFETY_MSS_TPTC_A1_WR 12U
112 #define SDL_ECC_BUS_SAFETY_MSS_TPTC_B0_WR 13U
113 #define SDL_ECC_BUS_SAFETY_MSS_CR5A_AHB 14U
114 #define SDL_ECC_BUS_SAFETY_MSS_CR5B_AHB 15U
115 #define SDL_ECC_BUS_SAFETY_MSS_CR5C_AHB 16U
116 #define SDL_ECC_BUS_SAFETY_MSS_CR5D_AHB 17U
117 #define SDL_ECC_BUS_SAFETY_MSS_CR5A_AXI_WR 18U
118 #define SDL_ECC_BUS_SAFETY_MSS_CR5B_AXI_WR 19U
119 #define SDL_ECC_BUS_SAFETY_MSS_CR5C_AXI_WR 20U
120 #define SDL_ECC_BUS_SAFETY_MSS_CR5D_AXI_WR 21U
121 #define SDL_ECC_BUS_SAFETY_MSS_MAIN_VBUSP 22U
122 #define SDL_ECC_BUS_SAFETY_MSS_PERI_VBUSP 23U
123 #define SDL_ECC_BUS_SAFETY_MSS_QSPI 24U
124 #define SDL_ECC_BUS_SAFETY_MSS_CPSW 25U
125 #define SDL_ECC_BUS_SAFETY_MSS_MCRC 26U
126 #define SDL_ECC_BUS_SAFETY_MSS_L2_A 27U
127 #define SDL_ECC_BUS_SAFETY_MSS_L2_B 28U
128 #define SDL_ECC_BUS_SAFETY_MSS_L2_C 29U
129 #define SDL_ECC_BUS_SAFETY_MSS_L2_D 30U
130 #define SDL_ECC_BUS_SAFETY_MSS_SCRP 31U
131 #define SDL_ECC_BUS_SAFETY_MSS_DAP 32U
132 #define SDL_ECC_BUS_SAFETY_MSS_MMC 33U
133 #define SDL_ECC_BUS_SAFETY_MSS_GPMC 34U
134 #define SDL_ECC_BUS_SAFETY_MSS_SCRP0 35U
135 #define SDL_ECC_BUS_SAFETY_MSS_SCRP1 36U
136 #define SDL_ECC_BUS_SAFETY_ICSSM_PDSP0 37U
137 #define SDL_ECC_BUS_SAFETY_ICSSM_PDSP1 38U
138 #define SDL_ECC_BUS_SAFETY_ICSSM_S 39U
139 #define SDL_ECC_BUS_SAFETY_DAP 40U
140 #define SDL_ECC_BUS_SAFETY_MSS_STM_STIM 41U