AM263x MCU+ SDK  09.02.00
rti/v0/rti.h
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1 /*
2  * Copyright (C) 2022 Texas Instruments Incorporated
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  *
8  * Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  *
11  * Redistributions in binary form must reproduce the above copyright
12  * notice, this list of conditions and the following disclaimer in the
13  * documentation and/or other materials provided with the
14  * distribution.
15  *
16  * Neither the name of Texas Instruments Incorporated nor the names of
17  * its contributors may be used to endorse or promote products derived
18  * from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  */
32 
48 #ifndef RTI_H_
49 #define RTI_H_
50 
51 /* ========================================================================== */
52 /* Include Files */
53 /* ========================================================================== */
54 
55 #include <stdint.h>
56 #include <drivers/hw_include/cslr_rti.h>
57 
58 #ifdef __cplusplus
59 extern "C" {
60 #endif
61 
62 /* ========================================================================== */
63 /* Macros & Typedefs */
64 /* ========================================================================== */
65 
77 #define RTI_GC_STALL_MODE_ON (CSL_RTI_RTIGCTRL_COS_STOPPED)
78 
79 #define RTI_GC_STALL_MODE_OFF (CSL_RTI_RTIGCTRL_COS_RUNNING)
80 
91 #define RTI_TMR_CNT_BLK_INDEX_0 (0U)
92 
93 #define RTI_TMR_CNT_BLK_INDEX_1 (1U)
94 
95 #define RTI_TMR_CNT_BLK_INDEX_MAX (RTI_TMR_CNT_BLK_INDEX_1)
96 
107 #define RTI_TMR_CMP_BLK_INDEX_0 (0U)
108 
109 #define RTI_TMR_CMP_BLK_INDEX_1 (1U)
110 
111 #define RTI_TMR_CMP_BLK_INDEX_2 (2U)
112 
113 #define RTI_TMR_CMP_BLK_INDEX_3 (3U)
114 
115 #define RTI_TMR_CMP_BLK_INDEX_MAX (RTI_TMR_CMP_BLK_INDEX_3)
116 
125 #define RTI_TMR_MIN_PRESCALER_VAL (1U)
126 
127 #define RTI_TMR_MAX_PRESACLER_VAL (0xFFFFFFFFU)
128 
137 #define RTI_TMR_INT_INT0_FLAG (CSL_RTI_RTISETINT_SETINT0_MASK)
138 
139 #define RTI_TMR_INT_INT1_FLAG (CSL_RTI_RTISETINT_SETINT1_MASK)
140 
141 #define RTI_TMR_INT_INT2_FLAG (CSL_RTI_RTISETINT_SETINT2_MASK)
142 
143 #define RTI_TMR_INT_INT3_FLAG (CSL_RTI_RTISETINT_SETINT3_MASK)
144 
146 #define RTI_TMR_INT_DMA0_FLAG (CSL_RTI_RTISETINT_SETDMA0_MASK)
147 
148 #define RTI_TMR_INT_DMA1_FLAG (CSL_RTI_RTISETINT_SETDMA1_MASK)
149 
150 #define RTI_TMR_INT_DMA2_FLAG (CSL_RTI_RTISETINT_SETDMA2_MASK)
151 
152 #define RTI_TMR_INT_DMA3_FLAG (CSL_RTI_RTISETINT_SETDMA3_MASK)
153 
155 #define RTI_TMR_INT_TB_FLAG (CSL_RTI_RTISETINT_SETTBINT_MASK)
156 
157 #define RTI_TMR_INT_OVL0_FLAG (CSL_RTI_RTISETINT_SETOVL0INT_MASK)
158 
159 #define RTI_TMR_INT_OVL1_FLAG (CSL_RTI_RTISETINT_SETOVL1INT_MASK)
160 
162 #define RTI_TMR_INT_STATUS_ALL (RTI_TMR_INT_INT0_FLAG | \
163  RTI_TMR_INT_INT1_FLAG | \
164  RTI_TMR_INT_INT2_FLAG | \
165  RTI_TMR_INT_INT3_FLAG | \
166  RTI_TMR_INT_TB_FLAG | \
167  RTI_TMR_INT_OVL0_FLAG | \
168  RTI_TMR_INT_OVL1_FLAG)
169 
170 #define RTI_TMR_INT_REQ_ALL (RTI_TMR_INT_INT0_FLAG | \
171  RTI_TMR_INT_INT1_FLAG | \
172  RTI_TMR_INT_INT2_FLAG | \
173  RTI_TMR_INT_INT3_FLAG | \
174  RTI_TMR_INT_DMA0_FLAG | \
175  RTI_TMR_INT_DMA1_FLAG | \
176  RTI_TMR_INT_DMA2_FLAG | \
177  RTI_TMR_INT_DMA3_FLAG | \
178  RTI_TMR_INT_TB_FLAG | \
179  RTI_TMR_INT_OVL0_FLAG | \
180  RTI_TMR_INT_OVL1_FLAG)
181 
190 #define RTI_TMR_INT_AUTO_CLR_ENABLE_FLAG (0x0000000FU)
191 
192 #define RTI_TMR_INT_AUTO_CLR_DISABLE_FLAG (0x00000005U)
193 
204 #define RTI_TMR_NTU_0 (0x0U)
205 
206 #define RTI_TMR_NTU_1 (0x5U)
207 
208 #define RTI_TMR_NTU_2 (0xAU)
209 
210 #define RTI_TMR_NTU_3 (0xFU)
211 
222 #define RTI_TMR_CAPTURE_EVT_0 (0U)
223 
224 #define RTI_TMR_CAPTURE_EVT_1 (1U)
225 
226 #define RTI_TMR_CAPTURE_EVT_MAX (RTI_TMR_CAPTURE_EVT_1)
227 
238 #define RTI_TMR_CLK_SRC_COUNTER (0U)
239 
240 #define RTI_TMR_CLK_SRC_NTU (1U)
241 
243 /* ========================================================================== */
244 /* Function Declarations */
245 /* ========================================================================== */
246 
260 int32_t RTIG_setStallMode(uint32_t baseAddr, uint32_t stallMode);
261 
275 int32_t RTI_counterEnable(uint32_t baseAddr, uint32_t cntIndex);
276 
287 int32_t RTI_counterDisable(uint32_t baseAddr, uint32_t cntIndex);
288 
303 int32_t RTI_counterClear(uint32_t baseAddr, uint32_t cntIndex);
304 
316 int32_t RTI_compareClear(uint32_t baseAddr, uint32_t cmpIndex);
317 
333 int32_t RTI_counterGet(uint32_t baseAddr, uint32_t cntIndex, uint32_t *counterLow, uint32_t *counterHigh);
334 
347 int32_t RTI_captureConfig(uint32_t baseAddr, uint32_t cntIndex, uint32_t cntrCapSrc);
348 
362 int32_t RTI_captureCounterGet(uint32_t baseAddr, uint32_t cntIndex, uint32_t *counterLow, uint32_t *counterHigh);
363 
377 int32_t RTI_compareEventConfig(uint32_t baseAddr, uint32_t cmpIndex, uint32_t cntBlkIndex, uint32_t cmpVal, uint32_t period);
378 
392 int32_t RTI_counterConfigure(uint32_t baseAddr, uint32_t cntBlkIndex, uint32_t clkSrc, uint32_t ntu, uint32_t prescaler);
393 
403 uint32_t RTI_compareGet(uint32_t baseAddr, uint32_t cmpIndex);
404 
416 int32_t RTI_compareClearConfig(uint32_t baseAddr, uint32_t cmpIndex, uint32_t cmpClearVal);
417 
426 uint32_t RTI_intStatusGet(uint32_t baseAddr);
427 
440 int32_t RTI_intStatusClear(uint32_t baseAddr, uint32_t intFlags);
441 
455 int32_t RTI_intEnable(uint32_t baseAddr, uint32_t intFlags);
456 
469 int32_t RTI_intDisable(uint32_t baseAddr, uint32_t intFlags);
470 
481 int32_t RTI_intAutoClearEnable(uint32_t baseAddr, uint32_t cmpIndex);
482 
493 int32_t RTI_intAutoClearDisable(uint32_t baseAddr, uint32_t cmpIndex);
494 
495 #ifdef __cplusplus
496 }
497 #endif
498 
499 #endif /* #ifndef RTI_H_ */
500 
RTI_intStatusGet
uint32_t RTI_intStatusGet(uint32_t baseAddr)
Read the status of INTFLAG register.
RTI_compareClear
int32_t RTI_compareClear(uint32_t baseAddr, uint32_t cmpIndex)
Clear Timer Compare block.
RTI_intAutoClearEnable
int32_t RTI_intAutoClearEnable(uint32_t baseAddr, uint32_t cmpIndex)
Enable the Compare interrupt auto clear.
RTI_compareGet
uint32_t RTI_compareGet(uint32_t baseAddr, uint32_t cmpIndex)
Get the compare match register contents.
RTI_compareEventConfig
int32_t RTI_compareEventConfig(uint32_t baseAddr, uint32_t cmpIndex, uint32_t cntBlkIndex, uint32_t cmpVal, uint32_t period)
Confiure Compare operation.
RTI_counterEnable
int32_t RTI_counterEnable(uint32_t baseAddr, uint32_t cntIndex)
Start the timer.
RTI_intAutoClearDisable
int32_t RTI_intAutoClearDisable(uint32_t baseAddr, uint32_t cmpIndex)
Disable the Compare interrupt auto clear.
RTI_counterClear
int32_t RTI_counterClear(uint32_t baseAddr, uint32_t cntIndex)
Clear Timer Counter block.
RTI_intDisable
int32_t RTI_intDisable(uint32_t baseAddr, uint32_t intFlags)
Disable the Timer interrupts.
RTI_intStatusClear
int32_t RTI_intStatusClear(uint32_t baseAddr, uint32_t intFlags)
Clear the status of interrupt events.
RTI_captureConfig
int32_t RTI_captureConfig(uint32_t baseAddr, uint32_t cntIndex, uint32_t cntrCapSrc)
Configure Capture operation.
RTI_compareClearConfig
int32_t RTI_compareClearConfig(uint32_t baseAddr, uint32_t cmpIndex, uint32_t cmpClearVal)
Confiure Compare Clear operation.
RTIG_setStallMode
int32_t RTIG_setStallMode(uint32_t baseAddr, uint32_t stallMode)
Set the stall mode in RTI Global Control.
RTI_counterDisable
int32_t RTI_counterDisable(uint32_t baseAddr, uint32_t cntIndex)
Stop the timer.
RTI_captureCounterGet
int32_t RTI_captureCounterGet(uint32_t baseAddr, uint32_t cntIndex, uint32_t *counterLow, uint32_t *counterHigh)
Get/Read the counter value from the capture registers.
RTI_counterGet
int32_t RTI_counterGet(uint32_t baseAddr, uint32_t cntIndex, uint32_t *counterLow, uint32_t *counterHigh)
Get/Read the counter value from the counter registers.
RTI_counterConfigure
int32_t RTI_counterConfigure(uint32_t baseAddr, uint32_t cntBlkIndex, uint32_t clkSrc, uint32_t ntu, uint32_t prescaler)
Confiure Compare operation.
RTI_intEnable
int32_t RTI_intEnable(uint32_t baseAddr, uint32_t intFlags)
Enable the Timer interrupts.