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AM263x MCU+ SDK
09.01.00
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Go to the documentation of this file.
40 #ifndef SDL_ECC_AGGR_H
41 #define SDL_ECC_AGGR_H
100 #define SDL_ECC_AGGR_INTR_SRC_NONE ((uint32_t) 0U)
102 #define SDL_ECC_AGGR_INTR_SRC_SINGLE_BIT ((uint32_t) 1U)
104 #define SDL_ECC_AGGR_INTR_SRC_DOUBLE_BIT ((uint32_t) 2U)
106 #define SDL_ECC_ADDR_ERROR_TYPE_SUCCESSIVE_SINGLE_BITS ((uint32_t) 3U)
108 #define SDL_ECC_AGGR_INTR_SRC_INVALID ((uint32_t) 4U)
116 #define SDL_ECC_AGGR_SELECT_ERR_CTRL1 (0U)
118 #define SDL_ECC_AGGR_SELECT_ERR_CTRL2 (1U)
120 #define SDL_ECC_AGGR_MAX_NUM_RAM_ERR_CTRL (2U)
128 #define SDL_ECC_AGGR_SELECT_ERR_STAT1 (0U)
130 #define SDL_ECC_AGGR_SELECT_ERR_STAT2 (1U)
132 #define SDL_ECC_AGGR_SELECT_ERR_STAT3 (2U)
134 #define SDL_ECC_AGGR_MAX_NUM_RAM_ERR_STAT (3U)
142 #define SDL_ECC_AGGR_NUM_ENABLE_REGISTERS (8U)
144 #define SDL_ECC_AGGR_VALID_TIMEOUT_ERR (1U)
146 #define SDL_ECC_AGGR_VALID_PARITY_ERR (2U)
149 #define SDL_ECC_AGGR_INJECT_PATTERN_ZERO ((uint32_t) 0U)
151 #define SDL_ECC_AGGR_INJECT_PATTERN_F ((uint32_t) 1U)
153 #define SDL_ECC_AGGR_INJECT_PATTERN_A ((uint32_t) 2U)
155 #define SDL_ECC_AGGR_INJECT_PATTERN_5 ((uint32_t) 3U)
157 #define SDL_ECC_EGGR_INJECT_PATTERN_MAX (SDL_ECC_AGGR_INJECT_PATTERN_A)
160 #define SDL_ECC_AGGR_ERROR_SUBTYPE_NORMAL ((uint32_t) 0U)
162 #define SDL_ECC_AGGR_ERROR_SUBTYPE_INJECT ((uint32_t) 1U)
int32_t SDL_ecc_aggrWriteEccRamErrStatReg(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, uint32_t instSelect, uint32_t val)
int32_t SDL_ecc_aggrAckIntr(SDL_ecc_aggrRegs *pEccAggrRegs, SDL_Ecc_AggrIntrSrc intrSrc)
int32_t SDL_ecc_aggrDisableIntr(const SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, SDL_Ecc_AggrIntrSrc intrSrc)
int32_t SDL_ecc_aggrWriteEccRamReg(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, uint32_t regOffset, uint32_t val)
uint32_t timeOutCnt
Definition: V1/sdl_ip_ecc.h:294
int32_t SDL_ecc_aggrSetEccRamNIntrPending(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, SDL_Ecc_AggrIntrSrc intrSrc, uint32_t numEvents)
uint32_t singleBitErrorCount
Definition: V1/sdl_ip_ecc.h:262
uint32_t REV
Definition: V1/sdl_ip_ecc.h:312
This structure contains error status information returned by the SDL_ecc_aggrGetEccRamGetErrorStatus ...
Definition: V1/sdl_ip_ecc.h:246
uint32_t SDL_Ecc_AggrEDCErrorSubType
This enumerator defines the types of possible EDC errors.
Definition: V1/sdl_ip_ecc.h:190
int32_t SDL_ecc_aggrIsIntrPending(const SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, SDL_Ecc_AggrIntrSrc intrSrc, bool *pIsPend)
uint32_t ECC_CTRL
Definition: V1/sdl_ip_ecc.h:314
int32_t SDL_ecc_aggrClrEccRamNIntrPending(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, SDL_Ecc_AggrIntrSrc intrSrc, uint32_t numEvents)
Definition: V1/sdlr_ecc.h:53
SDL_Ecc_AggrIntrSrc intrSrc
Definition: V1/sdl_ip_ecc.h:225
bool bNextRow
Definition: V1/sdl_ip_ecc.h:235
bool intrEnableTimeoutErr
Definition: V1/sdl_ip_ecc.h:275
int32_t SDL_ecc_aggrDisableIntrs(const SDL_ecc_aggrRegs *pEccAggrRegs, SDL_Ecc_AggrIntrSrc intrSrc)
int32_t SDL_ecc_aggrForceEccRamError(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, const SDL_Ecc_AggrErrorInfo *pEccForceError)
int32_t SDL_ecc_aggrReadStaticRegs(SDL_ecc_aggrRegs *pEccAggrRegs, SDL_ECC_staticRegs *pEccAggrStaticRegs)
int32_t SDL_ecc_aggrClrEccRamIntrPending(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, SDL_Ecc_AggrIntrSrc intrSrc)
uint32_t eccBit1
Definition: V1/sdl_ip_ecc.h:229
int32_t SDL_ecc_aggrIntrEnableCtrl(SDL_ecc_aggrRegs *pEccAggrRegs, const SDL_ecc_aggrEnableCtrl *pEnableCtrl)
bool intrStatusSetTimeoutErr
Definition: V1/sdl_ip_ecc.h:290
int32_t SDL_ecc_aggrReadEccRamErrStatReg(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, uint32_t instSelect, uint32_t *pRegVal)
int32_t SDL_ecc_aggrEnableAllIntrs(const SDL_ecc_aggrRegs *pEccAggrRegs)
This structure contains error forcing information used by the SDL_ecc_aggrForceEccRamError function.
Definition: V1/sdl_ip_ecc.h:223
int32_t SDL_ecc_aggrWriteEccRamErrCtrlReg(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, uint32_t instSelect, uint32_t val)
uint32_t parityCnt
Definition: V1/sdl_ip_ecc.h:296
uint32_t ECC_ERR_CTRL1
Definition: V1/sdl_ip_ecc.h:316
uint32_t ECC_ERR_CTRL2
Definition: V1/sdl_ip_ecc.h:318
uint8_t SDL_ecc_aggrValid
This defines the valid ecc aggr error configuration.
Definition: V1/sdl_ip_ecc.h:198
int32_t SDL_ecc_aggrReadEccRamErrCtrlReg(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, uint32_t instSelect, uint32_t *pRegVal)
bool controlRegErr
Definition: V1/sdl_ip_ecc.h:248
bool intrStatusSetParityErr
Definition: V1/sdl_ip_ecc.h:292
This structure contains the static register group for Ecc aggregator used by the SDL_ecc_aggrReadStat...
Definition: V1/sdl_ip_ecc.h:310
int32_t SDL_ecc_aggrReadEccRamCtrlReg(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, uint32_t *pRegVal)
int32_t SDL_ecc_aggrIntrStatusCtrl(SDL_ecc_aggrRegs *pEccAggrRegs, const SDL_ecc_aggrStatusCtrl *pStatusCtrl)
#define SDL_ECC_AGGR_NUM_ENABLE_REGISTERS
This defines the number of enable registers.
Definition: V1/sdl_ip_ecc.h:142
uint32_t eccBit1
Definition: V1/sdl_ip_ecc.h:260
int32_t SDL_ecc_aggrReadEccRamReg(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, uint32_t regOffset, uint32_t *pRegVal)
uint32_t eccBit2
Definition: V1/sdl_ip_ecc.h:231
bool intrEnableParityErr
Definition: V1/sdl_ip_ecc.h:277
uint32_t eccRow
Definition: V1/sdl_ip_ecc.h:258
int32_t SDL_ecc_aggrEnableIntrs(const SDL_ecc_aggrRegs *pEccAggrRegs, SDL_Ecc_AggrIntrSrc intrSrc)
bool bOneShotMode
Definition: V1/sdl_ip_ecc.h:233
uint32_t parityErrorCount
Definition: V1/sdl_ip_ecc.h:256
bool writebackPend
Definition: V1/sdl_ip_ecc.h:254
int32_t SDL_ecc_aggrDisableAllIntrs(const SDL_ecc_aggrRegs *pEccAggrRegs)
SDL_ecc_aggrValid validCfg
Definition: V1/sdl_ip_ecc.h:279
uint32_t SDL_Ecc_AggrIntrSrc
This enumerator defines the types of possible ECC errors.
Definition: V1/sdl_ip_ecc.h:181
uint32_t SDL_Ecc_injectPattern
This enumerator defines the types of ECC patterns.
Definition: V1/sdl_ip_ecc.h:206
bool sVBUSTimeoutErr
Definition: V1/sdl_ip_ecc.h:252
int32_t SDL_ecc_aggrVerifyConfigEccRam(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, bool bEnable, bool bEccCheck, bool bEnableRMW)
int32_t SDL_ecc_aggrGetNumRams(const SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t *pNumRams)
int32_t SDL_ecc_aggrWriteEccRamCtrlReg(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, uint32_t val)
uint32_t doubleBitErrorCount
Definition: V1/sdl_ip_ecc.h:264
This structure contains the ECC aggr status config.
Definition: V1/sdl_ip_ecc.h:288
bool successiveSingleBitErr
Definition: V1/sdl_ip_ecc.h:250
This structure contains the ECC aggr enable error config.
Definition: V1/sdl_ip_ecc.h:273
int32_t SDL_ecc_aggrEnableAllIntr(const SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId)
int32_t SDL_ecc_aggrGetEccRamErrorStatus(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, SDL_Ecc_AggrEccRamErrorStatusInfo *pEccErrorStatus)
int32_t SDL_ecc_aggrIsAnyIntrPending(const SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, bool *pIsPend)
int32_t SDL_ecc_aggrEnableIntr(const SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, SDL_Ecc_AggrIntrSrc intrSrc)
int32_t SDL_ecc_aggrIntrGetStatus(const SDL_ecc_aggrRegs *pEccAggrRegs, SDL_ecc_aggrStatusCtrl *pStatusCtrl)
int32_t SDL_ecc_aggrGetRevision(const SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t *pRev)
int32_t SDL_ecc_aggrDisableAllIntr(const SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId)
int32_t SDL_ecc_aggrIsEccRamIntrPending(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, SDL_Ecc_AggrIntrSrc intrSrc, bool *pIsPend)
int32_t SDL_ecc_aggrSetEccRamIntrPending(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, SDL_Ecc_AggrIntrSrc intrSrc)
SDL_ecc_aggrValid validCfg
Definition: V1/sdl_ip_ecc.h:298
uint32_t eccRow
Definition: V1/sdl_ip_ecc.h:227
int32_t SDL_ecc_aggrConfigEccRam(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, bool bEnable, bool bEccCheck, bool bEnableRMW)
int32_t SDL_ecc_aggrReadEccRamWrapRevReg(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, uint32_t *pRegVal)