bissc_pruicss_xchg Struct Reference

Detailed Description

Structure defining BiSS-C PRU-ICSS shared memory interface.

This is the primary communication structure between ARM R5F CPU and PRU firmware. Located in PRU Data RAM, it contains configuration parameters, command/control fields, and results. Both ARM and PRU access this structure for data exchange.

Data Fields
volatile uint8_t	pos_crc_len
volatile uint8_t	rx_clk_freq
volatile uint8_t	ctrl_cmd_crc_len
volatile uint8_t	channel
volatile uint8_t	status [BISSC_NUM_CH_PER_SLICE_MAX]
volatile uint8_t	primary_core_mask
volatile uint8_t	cycle_trigger [BISSC_NUM_CH_PER_SLICE_MAX]
volatile uint8_t	measure_proc_delay
volatile uint8_t	opmode [BISSC_NUM_CH_PER_SLICE_MAX]
bissc_enc_len	enc_len [BISSC_NUM_CH_PER_SLICE_MAX]
volatile uint8_t	valid_bit_idx
volatile uint8_t	fifo_bit_idx
volatile uint8_t	ctrl_cmd_status [BISSC_NUM_CH_PER_SLICE_MAX]
volatile uint16_t	proc_delay [BISSC_NUM_CH_PER_SLICE_MAX]
volatile uint32_t	ctrl_cmd [BISSC_NUM_CH_PER_SLICE_MAX]
volatile uint32_t	max_proc_delay
bissc_pos_data_res	pos_data_res [BISSC_NUM_CH_PER_SLICE_MAX]
bissc_ctrl_res	ctrl_res [BISSC_NUM_CH_PER_SLICE_MAX]
volatile uint8_t	execution_state [BISSC_NUM_CH_PER_SLICE_MAX]
volatile uint64_t	register_backup [BISSC_NUM_CH_PER_SLICE_MAX]
volatile uint8_t	bissc_re_measure_proc_delay
volatile uint8_t	has_safety [BISSC_NUM_CH_PER_SLICE_MAX]
volatile uint16_t	safety_crc [BISSC_NUM_ENCODERS_IN_DAISY_CHAIN_MAX][BISSC_NUM_CH_PER_SLICE_MAX]
volatile uint32_t	encoder_timeout [BISSC_NUM_CH_PER_SLICE_MAX]
volatile uint32_t	delay_100ms
volatile uint64_t	icss_clk
volatile uint32_t	iep_base_address
bissc_periodic_trigger_cfg	trigger_params [BISSC_NUM_CH_PER_SLICE_MAX]

Field Documentation

pos_crc_len

volatile uint8_t bissc_pruicss_xchg::pos_crc_len

Position data CRC polynomial length in bits (typically 6 bits for BiSS-C). Configured by ARM, used by PRU firmware for CRC calculation

rx_clk_freq

volatile uint8_t bissc_pruicss_xchg::rx_clk_freq

BiSS-C communication clock frequency in MHz (1, 2, 5, 8, or 10). Used by PRU firmware for timing calculations and delay measurements

ctrl_cmd_crc_len

volatile uint8_t bissc_pruicss_xchg::ctrl_cmd_crc_len

Control command CRC polynomial length in bits (4 bits for BiSS-C). Used by PRU firmware for control communication CRC calculation

channel

volatile uint8_t bissc_pruicss_xchg::channel

Channel enable bitmask (bit 0=ch0, bit 1=ch1, bit 2=ch2). Indicates which channels are active for this BiSS-C instance

status

volatile uint8_t bissc_pruicss_xchg::status[BISSC_NUM_CH_PER_SLICE_MAX]

PRU firmware initialization status for each channel. ARM polls this after loading firmware to confirm readiness

primary_core_mask

volatile uint8_t bissc_pruicss_xchg::primary_core_mask

Primary PRU core mask for load share mode synchronization (0x1, 0x2, or 0x4). Indicates which channel's PRU acts as primary coordinator

cycle_trigger

volatile uint8_t bissc_pruicss_xchg::cycle_trigger[BISSC_NUM_CH_PER_SLICE_MAX]

BiSS-C transaction trigger and completion status for each channel. ARM writes 1 to trigger, PRU clears to 0 when transaction completes ARM polls this in bissc_command_wait to detect completion

measure_proc_delay

volatile uint8_t bissc_pruicss_xchg::measure_proc_delay

Processing delay measurement control flag. 1 = ARM requests PRU to measure encoder delay after configuration change 0 = Measurement complete, PRU has updated proc_delay[]

opmode

volatile uint8_t bissc_pruicss_xchg::opmode[BISSC_NUM_CH_PER_SLICE_MAX]

Operation mode for each channel. 0 (BISSC_OPMODE_PERIODIC_CMP) = Automatic periodic triggering via IEP compare event 1 (BISSC_OPMODE_HOST_TRIGGER) = Manual trigger by ARM via cycle_trigger 2 (BISSC_OPMODE_PERIODIC_CAP) = Automatic periodic triggering via IEP capture event

enc_len

bissc_enc_len bissc_pruicss_xchg::enc_len[BISSC_NUM_CH_PER_SLICE_MAX]

Encoder resolution configuration for each channel. Specifies number of encoders and data length (bits) for parsing position data

valid_bit_idx

volatile uint8_t bissc_pruicss_xchg::valid_bit_idx

Valid bit index

fifo_bit_idx

volatile uint8_t bissc_pruicss_xchg::fifo_bit_idx

Middle bit index for oversampling (4=8x, 3=6x, 2=4x oversampling). PRU samples this bit position for most reliable data recovery

ctrl_cmd_status

volatile uint8_t bissc_pruicss_xchg::ctrl_cmd_status[BISSC_NUM_CH_PER_SLICE_MAX]

Control communication transaction status for each channel. ARM writes 1 to initiate control communication, PRU clears to 0 when complete

proc_delay

volatile uint16_t bissc_pruicss_xchg::proc_delay[BISSC_NUM_CH_PER_SLICE_MAX]

Measured encoder processing delay in clock cycles for each channel. Automatically measured by PRU firmware, read by ARM via bissc_get_enc_proc_delay

ctrl_cmd

volatile uint32_t bissc_pruicss_xchg::ctrl_cmd[BISSC_NUM_CH_PER_SLICE_MAX]

Control communication command for each channel (32-bit hex value). Generated by bissc_generate_ctrl_cmd on ARM, executed by PRU firmware

max_proc_delay

volatile uint32_t bissc_pruicss_xchg::max_proc_delay

Maximum allowed processing delay in clock cycles for current frequency. Used by PRU firmware to validate measured delay is within spec

pos_data_res

bissc_pos_data_res bissc_pruicss_xchg::pos_data_res[BISSC_NUM_CH_PER_SLICE_MAX]

Position data results for each channel (raw data, CRC, error counts). Updated by PRU firmware after each transaction, read by ARM via bissc_get_pos

ctrl_res

bissc_ctrl_res bissc_pruicss_xchg::ctrl_res[BISSC_NUM_CH_PER_SLICE_MAX]

Control communication results for each channel (register data, CRC). Updated by PRU firmware, read by ARM via bissc_set_ctrl_cmd_and_process

execution_state

volatile uint8_t bissc_pruicss_xchg::execution_state[BISSC_NUM_CH_PER_SLICE_MAX]

PRU firmware execution state for load share mode synchronization. Used internally by firmware to coordinate multi-PRU operations

register_backup

volatile uint64_t bissc_pruicss_xchg::register_backup[BISSC_NUM_CH_PER_SLICE_MAX]

PRU register backup storage for context switching (ch0, ch1, ch2). Used by firmware for saving/restoring state during channel operations

bissc_re_measure_proc_delay

volatile uint8_t bissc_pruicss_xchg::bissc_re_measure_proc_delay

Flag to request re-measurement of processing delay. Set to 1 by ARM when frequency changes, cleared by PRU after measurement

has_safety

volatile uint8_t bissc_pruicss_xchg::has_safety[BISSC_NUM_CH_PER_SLICE_MAX]

BiSS Safety protocol enable bitmask for each channel. Each bit represents an encoder in daisy chain: bit 0=enc0, bit 1=enc1, bit 2=enc2 1 = Safety enabled (includes 16-bit CRC and sign-of-life counter)

safety_crc

volatile uint16_t bissc_pruicss_xchg::safety_crc[BISSC_NUM_ENCODERS_IN_DAISY_CHAIN_MAX][BISSC_NUM_CH_PER_SLICE_MAX]

Calculated 16-bit safety CRC for BiSS Safety protocol. Indexed by [encoder][channel], computed by PRU firmware

encoder_timeout

volatile uint32_t bissc_pruicss_xchg::encoder_timeout[BISSC_NUM_CH_PER_SLICE_MAX]

Per-channel encoder timeout delay in PRU clock cycles. Default: 40 microseconds Used by firmware for per-channel BiSS-C encoder timeout

delay_100ms

volatile uint32_t bissc_pruicss_xchg::delay_100ms

Maximum interframe delay in PRU clock cycles equivalent to 100 milliseconds. Calculated as: (core_clk_freq / BISSC_MHZ_TO_HZ) * 100 * 1000 Used by firmware for maximum time between BiSS-C frames

icss_clk

volatile uint64_t bissc_pruicss_xchg::icss_clk

PRU-ICSS core clock frequency in Hz (not MHz). Example: 200000000 for 200 MHz, 300000000 for 300 MHz Used by firmware for precise timing and delay calculations

iep_base_address

volatile uint32_t bissc_pruicss_xchg::iep_base_address

IEP base address used for periodic trigger mode

trigger_params

bissc_periodic_trigger_cfg bissc_pruicss_xchg::trigger_params[BISSC_NUM_CH_PER_SLICE_MAX]

Periodic trigger configuration parameters for each channel (ch0, ch1, ch2). Contains IEP event numbers and capture register addresses