bissc_clk_cfg Struct Reference

Detailed Description

Structure defining BiSS-C clock configuration for selected frequency.

Contains clock divisors and configuration calculated by bissc_calc_clock for achieving the desired baud rate. These values are written to PRU-ICSS registers during hardware initialization.

Data Fields
uint16_t	rx_div
uint16_t	tx_div
uint16_t	rx_div_attr
uint16_t	is_core_clk

Field Documentation

rx_div

uint16_t bissc_clk_cfg::rx_div

Rx clock divisor (value-1 written to register). Determines receive sample rate. Formula: rx_clk = source_clk / ((rx_div + 1) * rx_oversampling) Example: For 8x oversampling at 1 MHz from 200 MHz core: rx_div = 24

tx_div

uint16_t bissc_clk_cfg::tx_div

Tx clock divisor (value-1 written to register). Determines transmit baud rate. Formula: tx_clk = source_clk / (tx_div + 1) Example: For 1 MHz from 200 MHz core: tx_div = 199

rx_div_attr

uint16_t bissc_clk_cfg::rx_div_attr

Rx oversampling rate, start bit polarity and fractional divider configuration. Bits [2:0] : Oversampling divisor (7 = 8x, 5 = 6x, 3 = 4x) Bits [3] : Start bit polarity (0 or 1) Bit [15] : Fractional divider enable (1=enable 1.5x fractional division)

is_core_clk

uint16_t bissc_clk_cfg::is_core_clk

Clock source selection for BiSS-C communication. 0 = Use UART clock (160/192 MHz) 1 = Use Core clock (200/300 MHz)