AM263Px Motor Control SDK  2025.00.00
bissc_attrs Struct Reference

Detailed Description

Structure defining BiSS-C attributes (compile-time/SysConfig configuration data)

Data Fields

uint8_t instance
 
uint8_t mode
 
uint8_t pruicss_instance
 
uint8_t pruicss_slice
 
uint8_t load_share_enabled
 
uint8_t channel_mask
 
uint8_t channel0_enabled
 
uint8_t channel1_enabled
 
uint8_t channel2_enabled
 
uint8_t total_channels
 
uint16_t baud_rate
 
uint32_t core_clk_freq
 
uint32_t uart_clk_freq
 
uint32_t iep_clk_freq
 
uint16_t is_core_clk
 
uint8_t iep_instance
 
uint8_t iep_cmp_event [BISSC_NUM_CH_PER_SLICE_MAX]
 
uint8_t iep_cap_event [BISSC_NUM_CH_PER_SLICE_MAX]
 
void * iep_base_addr
 

Field Documentation

◆ instance

uint8_t bissc_attrs::instance

BiSS-C instance index (0, 1, ...) for multi-instance configurations. Used to distinguish between multiple BiSS-C instances in the system

◆ mode

uint8_t bissc_attrs::mode

BiSS-C configuration mode. 0 = BISSC_MODE_SINGLE_CHANNEL_SINGLE_PRU (one channel, one PRU) 1 = BISSC_MODE_MULTI_CHANNEL_SINGLE_PRU (multiple channels, one PRU) 2 = BISSC_MODE_MULTI_CHANNEL_MULTI_PRU (multiple channels, load-shared across PRUs)

◆ pruicss_instance

uint8_t bissc_attrs::pruicss_instance

PRU-ICSS hardware instance number (0 or 1). 0 = PRU-ICSSG0/PRU-ICSSM0 1 = PRU-ICSSG1/PRU-ICSSM1

◆ pruicss_slice

uint8_t bissc_attrs::pruicss_slice

PRU-ICSS slice selection (0 or 1). Each PRU-ICSS has 2 slices, each with its own set of PRU cores. 0 = Slice 0 (contains PRU0/RTU-PRU0/TX-PRU0 on PRU-ICSSG, PRU0 on PRU-ICSSM) 1 = Slice 1 (contains PRU1/RTU-PRU1/TX-PRU1 on PRU-ICSSG, PRU1 on PRU-ICSSM)

◆ load_share_enabled

uint8_t bissc_attrs::load_share_enabled

Load share mode enable flag. 0 = Disabled (single PRU handles all channels) 1 = Enabled (channels distributed across RTU-PRU, PRU, and TX-PRU in PRU-ICSSG only)

◆ channel_mask

uint8_t bissc_attrs::channel_mask

Bit mask indicating which channels are enabled (0-7). Bit 0 (0x1): Channel 0 enabled Bit 1 (0x2): Channel 1 enabled Bit 2 (0x4): Channel 2 enabled Example: 0x5 = channels 0 and 2 enabled

◆ channel0_enabled

uint8_t bissc_attrs::channel0_enabled

Channel 0 enable flag (1=enabled, 0=disabled)

◆ channel1_enabled

uint8_t bissc_attrs::channel1_enabled

Channel 1 enable flag (1=enabled, 0=disabled)

◆ channel2_enabled

uint8_t bissc_attrs::channel2_enabled

Channel 2 enable flag (1=enabled, 0=disabled)

◆ total_channels

uint8_t bissc_attrs::total_channels

Total number of enabled channels (1, 2, or 3). Calculated as: channel0_enabled + channel1_enabled + channel2_enabled

◆ baud_rate

uint16_t bissc_attrs::baud_rate

BiSS-C communication baud rate in MHz (configured from SysConfig). Valid values: 1, 2, 5, 8, or 10 MHz

◆ core_clk_freq

uint32_t bissc_attrs::core_clk_freq

PRU-ICSS Core Clock frequency in Hz (not MHz).

◆ uart_clk_freq

uint32_t bissc_attrs::uart_clk_freq

PRU-ICSS UART Clock frequency in Hz (not MHz).

◆ iep_clk_freq

uint32_t bissc_attrs::iep_clk_freq

PRU-ICSS IEP (Industrial Ethernet Peripheral) timer clock frequency in Hz.

◆ is_core_clk

uint16_t bissc_attrs::is_core_clk

Clock source selection for BiSS-C communication. 0 = Use UART clock as source (uart_clk_freq) 1 = Use Core clock as source (core_clk_freq)

◆ iep_instance

uint8_t bissc_attrs::iep_instance

IEP instance number used for periodic trigger mode

◆ iep_cmp_event

uint8_t bissc_attrs::iep_cmp_event[BISSC_NUM_CH_PER_SLICE_MAX]

IEP compare event number used for periodic trigger mode

◆ iep_cap_event

uint8_t bissc_attrs::iep_cap_event[BISSC_NUM_CH_PER_SLICE_MAX]

IEP capture event number used for periodic trigger mode

◆ iep_base_addr

void* bissc_attrs::iep_base_addr

IEP base address for IEP timer configuration in periodic trigger mode