bissc_drv.h

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/*
 *  Copyright (C) 2023-2026 Texas Instruments Incorporated
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
 
#ifndef BISSC_DRV_H_
#define BISSC_DRV_H_
 
/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */
 
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <drivers/pruicss.h>
#include <position_sense/bissc/include/bissc_interface.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
/* ========================================================================== */
/*                           Macros & Typedefs                                */
/* ========================================================================== */
 
 
#define BISSC_DEFAULT_CMD_PROCESS_DELAY_US      (1000U)
 
#define BISSC_DEFAULT_FW_WAIT_DELAY_US          (1000U)
 
#define BISSC_DEFAULT_MAX_WAIT_LOOP_COUNT         (5U)
 
#define BISSC_DEFAULT_ENCODER_TIMEOUT_US          (40U)
 
#define BISSC_MODE_SINGLE_CHANNEL_SINGLE_PRU    (0U)
 
#define BISSC_MODE_MULTI_CHANNEL_SINGLE_PRU     (1U)
 
#define BISSC_MODE_MULTI_CHANNEL_MULTI_PRU      (2U)
 
#define BISSC_MAX_PROC_DELAY_1MHZ           40
 
#define BISSC_MAX_PROC_DELAY_2MHZ           80
 
#define BISSC_MAX_PROC_DELAY_5MHZ           200
 
#define BISSC_MAX_PROC_DELAY_8MHZ           320
 
#define BISSC_MAX_PROC_DELAY_10MHZ          400
 
#define BISSC_CTS_BIT                       1
 
#define BISSC_ENC_ID_LEN                    3
 
#define BISSC_ENC_ID_MASK                   0x7
 
#define BISSC_REG_ADDR_LEN                  7
 
#define BISSC_REG_ADDR_MASK                 0x7F
 
#define BISSC_RWS_LEN                       3
 
#define BISSC_RWS_MASK                      0x7
 
#define BISSC_CTRL_READ_ACCESS              0x5
 
#define BISSC_CTRL_WRITE_ACCESS             0x3
 
#define BISSC_REG_DATA_LEN                  8
 
#define BISSC_REG_DATA_MASK                 0xFF
 
#define BISSC_CTRL_STOP_LEN                 2
 
#define BISSC_RX_SAMPLE_SIZE                7
 
#define BISSC_RX_SAMPLE_SIZE_6X             5
 
#define BISSC_RX_SAMPLE_SIZE_4X             3
 
#define BISSC_POS_CRC_LEN                   6
 
#define BISSC_EW_LEN                        2
 
#define BISSC_CTRL_CMD_CRC_LEN              4
 
#define BISSC_CTRL_CMD_CRC_MASK             0xF
 
#define BISSC_POS_DATA_LEN_DEFAULT          12
 
#define BISSC_SAFETY_CRC_LEN                16
 
#define BISSC_SIGN_OF_LIFE_LEN              6
 
#define BISSC_MAX_FRAME_SIZE                64
 
#define BISSC_RX_ENABLE_FRACTIONAL_DIV      (1<<15)
 
#define BISSC_FREQ_1MHZ                     1
 
#define BISSC_FREQ_2MHZ                     2
 
#define BISSC_FREQ_5MHZ                     5
 
#define BISSC_FREQ_8MHZ                     8
 
#define BISSC_FREQ_10MHZ                    10
 
#define BISSC_FIFO_BIT_IDX_8X_OS            4
 
#define BISSC_FIFO_BIT_IDX_6X_OS            3
 
#define BISSC_FIFO_BIT_IDX_4X_OS            2
 
#define BISSC_CLEAR_STATUS_FLAG             0x0
 
#define BISSC_SET_STATUS_FLAG               0x1
 
#define BISSC_PRU_CORE_CLK_FREQ_200MHZ            200
 
#define BISSC_PRU_CORE_CLK_FREQ_300MHZ            300
 
#define BISSC_PRU_UART_CLK_FREQ_160MHZ            160
 
#define BISSC_PRU_UART_CLK_FREQ_192MHZ            192
 
#define BISSC_VALID_BIT_IDX                       (24U)
 
#define BISSC_CLOCK_FRACTIONAL_DIVIDER            (1.5)
 
#define BISSC_MHZ_TO_HZ                          (1000000U)
 
#define BISSC_EW_FIELD_MASK                      (0x03U)
 
#define BISSC_6BIT_FIELD_MASK                    (0x3FU)
 
#define BISSC_SAFETY_CRC_FIELD_MASK              (0xFFFFU)
 
#define BISSC_OPMODE_PERIODIC_CMP           (0x0U)
 
#define BISSC_OPMODE_HOST_TRIGGER           (0x1U)
 
#define BISSC_OPMODE_PERIODIC_CAP           (0x2U)
 
#define BISSC_MEASURE_PROC_DELAY_DISABLE    (0x0U)
 
#define BISSC_MEASURE_PROC_DELAY_ENABLE     (0x1U)
 
 
#define BISSC_CFG_REG_SIZE         (4U)
#define BISSC_CSL_ICSS_PR1_IEP0_SLV_CAP0_REG0  (CSL_ICSS_PR1_IEP0_SLV_CAP_CFG_REG + 2U*BISSC_CFG_REG_SIZE)
 
#define BISSC_8_BYTE_REG_OFFSET    (8U)
 
#define BISSC_IEP_MAX_CAP_EVENT    (0x8U)
 
#define BISSC_IEP_MAX_CMP_EVENT    (0x10U)
 
/* ========================================================================== */
/*                         Structure Declarations                             */
/* ========================================================================== */
 
typedef struct bissc_clk_cfg_s
{
    uint16_t  rx_div;
    uint16_t  tx_div;
    uint16_t  rx_div_attr;
    uint16_t  is_core_clk;
} bissc_clk_cfg;
 
typedef struct bissc_position_info_s
{
    uint64_t          position[BISSC_NUM_ENCODERS_IN_DAISY_CHAIN_MAX];
    float             angle[BISSC_NUM_ENCODERS_IN_DAISY_CHAIN_MAX];
    uint32_t          num_of_turns[BISSC_NUM_ENCODERS_IN_DAISY_CHAIN_MAX];
    uint8_t           ew[BISSC_NUM_ENCODERS_IN_DAISY_CHAIN_MAX];
    uint8_t           rcv_crc[BISSC_NUM_ENCODERS_IN_DAISY_CHAIN_MAX];
    uint8_t           otf_crc[BISSC_NUM_ENCODERS_IN_DAISY_CHAIN_MAX];
} bissc_position_info;
 
typedef struct bissc_control_info_s
{
    uint8_t           cmd_result;
    uint8_t           cmd_rcv_crc;
    uint8_t           cmd_otf_crc;
} bissc_control_info;
 
typedef struct bissc_params_s
{
    PRUICSS_Handle pruicss_handle;
    uint32_t cmd_process_delay_us;
    uint32_t fw_wait_delay_us;
    uint32_t max_wait_loop_count;
} bissc_params;
 
typedef struct bissc_priv_s
{
    uint8_t is_open;
    uint32_t data_len[BISSC_NUM_CH_PER_SLICE_MAX][BISSC_NUM_ENCODERS_IN_DAISY_CHAIN_MAX];
    uint32_t single_turn_len[BISSC_NUM_CH_PER_SLICE_MAX][BISSC_NUM_ENCODERS_IN_DAISY_CHAIN_MAX];
    uint32_t multi_turn_len[BISSC_NUM_CH_PER_SLICE_MAX][BISSC_NUM_ENCODERS_IN_DAISY_CHAIN_MAX];
    uint32_t channel[BISSC_NUM_CH_PER_SLICE_MAX];
    bissc_pruicss_xchg *pruicss_xchg;
    uint8_t has_safety[BISSC_NUM_CH_PER_SLICE_MAX][BISSC_NUM_ENCODERS_IN_DAISY_CHAIN_MAX];
    uint8_t sign_of_life_cnt[BISSC_NUM_CH_PER_SLICE_MAX][BISSC_NUM_ENCODERS_IN_DAISY_CHAIN_MAX];
    uint16_t rcv_safety_crc[BISSC_NUM_CH_PER_SLICE_MAX][BISSC_NUM_ENCODERS_IN_DAISY_CHAIN_MAX];
    uint16_t calc_safety_crc[BISSC_NUM_CH_PER_SLICE_MAX][BISSC_NUM_ENCODERS_IN_DAISY_CHAIN_MAX];
    uint8_t is_continuous_mode;
    uint64_t raw_data;
    bissc_position_info enc_pos_data[BISSC_NUM_CH_PER_SLICE_MAX];
    bissc_control_info enc_ctrl_data[BISSC_NUM_CH_PER_SLICE_MAX];
    uint32_t pd_crc_err_cnt[BISSC_NUM_CH_PER_SLICE_MAX][BISSC_NUM_ENCODERS_IN_DAISY_CHAIN_MAX];
    uint32_t ctrl_crc_err_cnt[BISSC_NUM_CH_PER_SLICE_MAX];
    uint32_t num_encoders[BISSC_NUM_CH_PER_SLICE_MAX];
    uint8_t ctrl_write_status[BISSC_NUM_CH_PER_SLICE_MAX];
    uint32_t ctrl_reg_address[BISSC_NUM_CH_PER_SLICE_MAX];
    uint32_t ctrl_reg_data[BISSC_NUM_CH_PER_SLICE_MAX];
    uint32_t ctrl_enc_id[BISSC_NUM_CH_PER_SLICE_MAX];
    uint16_t proc_delay[BISSC_NUM_CH_PER_SLICE_MAX];
    uint32_t baud_rate;
    uint32_t cmd_process_delay_us;
    uint32_t fw_wait_delay_us;
    uint32_t max_wait_loop_count;
    PRUICSS_Handle pruicss_handle;
} bissc_priv;
 
typedef struct bissc_attrs_s
{
    uint8_t instance;
    uint8_t mode;
    uint8_t pruicss_instance;
    uint8_t pruicss_slice;
    uint8_t load_share_enabled;
    uint8_t channel_mask;
    uint8_t channel0_enabled;
    uint8_t channel1_enabled;
    uint8_t channel2_enabled;
    uint8_t total_channels;
    uint16_t baud_rate;
    uint32_t core_clk_freq;
    uint32_t uart_clk_freq;
    uint32_t iep_clk_freq;
    uint16_t is_core_clk;
    uint8_t iep_instance;
    uint8_t iep_cmp_event[BISSC_NUM_CH_PER_SLICE_MAX];
    uint8_t iep_cap_event[BISSC_NUM_CH_PER_SLICE_MAX];
    void *iep_base_addr;
} bissc_attrs;
 
typedef struct bissc_config_s
{
    bissc_priv *priv;
    const bissc_attrs *attrs;
} bissc_config;
 
typedef bissc_config *bissc_handle;
 
#ifdef __cplusplus
}
#endif
 
#endif