bissc_drv.h File Reference

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Data Structures
struct	bissc_clk_cfg
	Structure defining BiSS-C clock configuration for selected frequency. More...
struct	bissc_position_info
	Structure defining BiSS-C Position data results. More...
struct	bissc_control_info
	Structure defining BiSS-C Channel specific control communication(ctrl) results. More...
struct	bissc_params
	Structure defining BiSS-C initialization parameters. More...
struct	bissc_priv
	BiSS-C private data structure (runtime state and configuration) More...
struct	bissc_attrs
	Structure defining BiSS-C attributes (compile-time/SysConfig configuration data) More...
struct	bissc_config
	Structure defining BiSS-C configuration handle. More...

Macros
#define	BISSC_DEFAULT_CMD_PROCESS_DELAY_US   (1000U)
	Delay in microseconds for command processing (1000 us = 1 ms) More...
#define	BISSC_DEFAULT_FW_WAIT_DELAY_US   (1000U)
	Delay in microseconds between firmware initialization status checks (1000 us = 1 ms) More...
#define	BISSC_DEFAULT_MAX_WAIT_LOOP_COUNT   (5U)
	Maximum wait loop count for BiSS-C cycle timeout. More...
#define	BISSC_DEFAULT_ENCODER_TIMEOUT_US   (40U)
	Default encoder timeout in microseconds. More...
#define	BISSC_MODE_SINGLE_CHANNEL_SINGLE_PRU   (0U)
	Single PRU - Single channel configuration mode. More...
#define	BISSC_MODE_MULTI_CHANNEL_SINGLE_PRU   (1U)
	Single PRU - Multichannel configuration mode. More...
#define	BISSC_MODE_MULTI_CHANNEL_MULTI_PRU   (2U)
	Multichannel - Load Share configuration mode. More...
#define	BISSC_MAX_PROC_DELAY_1MHZ   40
	Maximum encoder processing delay at 1 MHz in valid bits/clock cycles (40 cycles) More...
#define	BISSC_MAX_PROC_DELAY_2MHZ   80
	Maximum encoder processing delay at 2 MHz in valid bits/clock cycles (80 cycles) More...
#define	BISSC_MAX_PROC_DELAY_5MHZ   200
	Maximum encoder processing delay at 5 MHz in valid bits/clock cycles (200 cycles) More...
#define	BISSC_MAX_PROC_DELAY_8MHZ   320
	Maximum encoder processing delay at 8 MHz in valid bits/clock cycles (320 cycles) More...
#define	BISSC_MAX_PROC_DELAY_10MHZ   400
	Maximum encoder processing delay at 10 MHz in valid bits/clock cycles (400 cycles) More...
#define	BISSC_CTS_BIT   1
	CTS (Control Transfer Status) bit value for control communication. More...
#define	BISSC_ENC_ID_LEN   3
	Number of Encoder ID bits in control communication (3 bits) More...
#define	BISSC_ENC_ID_MASK   0x7
	Bit mask for extracting Encoder ID (0x7 = 0b111) More...
#define	BISSC_REG_ADDR_LEN   7
	Number of bits for Register address in control communication (7 bits) More...
#define	BISSC_REG_ADDR_MASK   0x7F
	Bit mask for extracting Register address (0x7F = 0b1111111) More...
#define	BISSC_RWS_LEN   3
	Number of RWS bits (3 bits) More...
#define	BISSC_RWS_MASK   0x7
	Bit mask for extracting RWS bits (0x7 = 0b111) More...
#define	BISSC_CTRL_READ_ACCESS   0x5
	RWS value for read access of encoder register (0x5 = 0b101) More...
#define	BISSC_CTRL_WRITE_ACCESS   0x3
	RWS value for write access of encoder register (0x3 = 0b011) More...
#define	BISSC_REG_DATA_LEN   8
	Number of Register data bits (8 bits = 1 byte) More...
#define	BISSC_REG_DATA_MASK   0xFF
	Bit mask for extracting Register data (0xFF = 0b11111111) More...
#define	BISSC_CTRL_STOP_LEN   2
	Number of stop bits for control communication (2 bits: P and S) More...
#define	BISSC_RX_SAMPLE_SIZE   7
	Rx divisor value for 8x oversampling (divisor = 8, register value = 7) More...
#define	BISSC_RX_SAMPLE_SIZE_6X   5
	Rx divisor value for 6x oversampling (divisor = 6, register value = 5) More...
#define	BISSC_RX_SAMPLE_SIZE_4X   3
	Rx divisor value for 4x oversampling (divisor = 4, register value = 3) More...
#define	BISSC_POS_CRC_LEN   6
	Number of position data CRC bits (6-bit CRC polynomial) More...
#define	BISSC_EW_LEN   2
	Number of Error and Warning bits (2 bits total) More...
#define	BISSC_CTRL_CMD_CRC_LEN   4
	Number of control command CRC bits (4-bit CRC polynomial) More...
#define	BISSC_CTRL_CMD_CRC_MASK   0xF
	Bit mask for extracting control command CRC (0xF = 0b1111) More...
#define	BISSC_POS_DATA_LEN_DEFAULT   12
	Default position data length in bits (12 bits) More...
#define	BISSC_SAFETY_CRC_LEN   16
	Number of Safety CRC bits for BiSS Safety protocol (16-bit CRC) More...
#define	BISSC_SIGN_OF_LIFE_LEN   6
	Number of Sign-of-Life counter bits in BiSS Safety protocol (6 bits) More...
#define	BISSC_MAX_FRAME_SIZE   64
	Maximum total frame size in bits (64 bits) More...
#define	BISSC_RX_ENABLE_FRACTIONAL_DIV   (1<<15)
	Enable fractional clock divider (1.5x) for Rx clock (bit 15 = 1) More...
#define	BISSC_FREQ_1MHZ   1
	Allowed BiSS-C communication frequency: 1 MHz. More...
#define	BISSC_FREQ_2MHZ   2
	Allowed BiSS-C communication frequency: 2 MHz. More...
#define	BISSC_FREQ_5MHZ   5
	Allowed BiSS-C communication frequency: 5 MHz. More...
#define	BISSC_FREQ_8MHZ   8
	Allowed BiSS-C communication frequency: 8 MHz. More...
#define	BISSC_FREQ_10MHZ   10
	Allowed BiSS-C communication frequency: 10 MHz. More...
#define	BISSC_FIFO_BIT_IDX_8X_OS   4
	Middle bit index for 8x oversampling (index 4 out of 0-7) More...
#define	BISSC_FIFO_BIT_IDX_6X_OS   3
	Middle bit index for 6x oversampling (index 3 out of 0-5) More...
#define	BISSC_FIFO_BIT_IDX_4X_OS   2
	Middle bit index for 4x oversampling (index 2 out of 0-3) More...
#define	BISSC_CLEAR_STATUS_FLAG   0x0
	General purpose macro for clearing any status flag (value = 0) More...
#define	BISSC_SET_STATUS_FLAG   0x1
	General purpose macro for setting any status flag (value = 1) More...
#define	BISSC_PRU_CORE_CLK_FREQ_200MHZ   200
	PRU-ICSS Core Clock frequency: 200 MHz (in MHz units) More...
#define	BISSC_PRU_CORE_CLK_FREQ_300MHZ   300
	PRU-ICSS Core Clock frequency: 300 MHz (in MHz units) More...
#define	BISSC_PRU_UART_CLK_FREQ_160MHZ   160
	PRU-ICSS UART Clock frequency: 160 MHz (in MHz units) More...
#define	BISSC_PRU_UART_CLK_FREQ_192MHZ   192
	PRU-ICSS UART Clock frequency: 192 MHz (in MHz units) More...
#define	BISSC_VALID_BIT_IDX   (24U)
	Valid bit index (value = 24) More...
#define	BISSC_CLOCK_FRACTIONAL_DIVIDER   (1.5)
	Clock fractional divider factor (value = 1.5) More...
#define	BISSC_MHZ_TO_HZ   (1000000U)
	MHz to Hz conversion factor (value = 1000000) More...
#define	BISSC_EW_FIELD_MASK   (0x03U)
	Error/Warning field bit mask (value = 0x03) More...
#define	BISSC_6BIT_FIELD_MASK   (0x3FU)
	6-bit field mask (value = 0x3F) More...
#define	BISSC_SAFETY_CRC_FIELD_MASK   (0xFFFFU)
	Safety CRC field mask (value = 0xFFFF) More...
#define	BISSC_OPMODE_PERIODIC_CMP   (0x0U)
	BiSS-C Periodic/Continuous operation mode using IEP compare (CMP) event. More...
#define	BISSC_OPMODE_HOST_TRIGGER   (0x1U)
	BiSS-C Host trigger operation mode. More...
#define	BISSC_OPMODE_PERIODIC_CAP   (0x2U)
	BiSS-C Periodic trigger with IEP CAP mode. More...
#define	BISSC_MEASURE_PROC_DELAY_DISABLE   (0x0U)
	Disable encoder processing delay measurement (value = 0x0) More...
#define	BISSC_MEASURE_PROC_DELAY_ENABLE   (0x1U)
	Enable encoder processing delay measurement (value = 0x1) More...
#define	BISSC_CFG_REG_SIZE   (4U)
	IEP cap 0 register , cslr common file does not have defined cap registers FIXME: Remove these definitions once they are available in cslr_common.h. More...
#define	BISSC_CSL_ICSS_PR1_IEP0_SLV_CAP0_REG0   (CSL_ICSS_PR1_IEP0_SLV_CAP_CFG_REG + 2U*BISSC_CFG_REG_SIZE)
#define	BISSC_8_BYTE_REG_OFFSET   (8U)
	8-byte register offset for IEP registers More...
#define	BISSC_IEP_MAX_CAP_EVENT   (0x8U)
	Maximum number of IEP capture events (0-7) More...
#define	BISSC_IEP_MAX_CMP_EVENT   (0x10U)
	Maximum number of IEP compare events (0-15) More...

Typedefs
typedef bissc_config *	bissc_handle
	BiSS-C handle type. More...

Macro Definition Documentation

BISSC_DEFAULT_CMD_PROCESS_DELAY_US

#define BISSC_DEFAULT_CMD_PROCESS_DELAY_US   (1000U)

Delay in microseconds for command processing (1000 us = 1 ms)

Default value for delay used in bissc_command_wait polling loop to avoid excessive CPU usage. Different value can be configured by changing cmd_process_delay_us of bissc_params before calling bissc_init.

BISSC_DEFAULT_FW_WAIT_DELAY_US

#define BISSC_DEFAULT_FW_WAIT_DELAY_US   (1000U)

Delay in microseconds between firmware initialization status checks (1000 us = 1 ms)

Default value for delay used in bissc_wait_for_fw_initialization, bissc_wait_measure_proc_delay and bissc_set_ctrl_cmd_and_process. Different value can be configured by changing fw_wait_delay_us of bissc_params before calling bissc_init.

BISSC_DEFAULT_MAX_WAIT_LOOP_COUNT

#define BISSC_DEFAULT_MAX_WAIT_LOOP_COUNT   (5U)

Maximum wait loop count for BiSS-C cycle timeout.

Actual timeout (ms) = max_wait_loop_count * cmd_process_delay_us / 1000 BiSS-C cycle time formula: TCycle_min = TMA * (5 + DLEN + CRCLEN) + tLineDelay + tbusy_max + busy_s_max + tTO Default value is 5, which with default cmd_process_delay_us of 1000us results in 5ms timeout. This accommodates various encoders and daisy chain configurations.

Different value can be configured by changing max_wait_loop_count of bissc_params before calling bissc_init. Value must be greater than 0.

BISSC_DEFAULT_ENCODER_TIMEOUT_US

#define BISSC_DEFAULT_ENCODER_TIMEOUT_US   (40U)

Default encoder timeout in microseconds.

BISSC_MODE_SINGLE_CHANNEL_SINGLE_PRU

#define BISSC_MODE_SINGLE_CHANNEL_SINGLE_PRU   (0U)

Single PRU - Single channel configuration mode.

Only one channel (ch0, ch1, or ch2) is used with a single PRU core. This is the simplest configuration for single encoder applications.

BISSC_MODE_MULTI_CHANNEL_SINGLE_PRU

#define BISSC_MODE_MULTI_CHANNEL_SINGLE_PRU   (1U)

Single PRU - Multichannel configuration mode.

Multiple channels (up to 3: ch0, ch1, ch2) are managed by a single PRU core. All channels share the same PRU core resources without load sharing.

BISSC_MODE_MULTI_CHANNEL_MULTI_PRU

#define BISSC_MODE_MULTI_CHANNEL_MULTI_PRU   (2U)

Multichannel - Load Share configuration mode.

Multiple channels are distributed across multiple PRU cores for load sharing. Each channel is handled by a dedicated PRU core. Mapping: RTU-PRU - Channel 0, PRU - Channel 1, TX-PRU - Channel 2.

BISSC_MAX_PROC_DELAY_1MHZ

#define BISSC_MAX_PROC_DELAY_1MHZ   40

Maximum encoder processing delay at 1 MHz in valid bits/clock cycles (40 cycles)

BISSC_MAX_PROC_DELAY_2MHZ

#define BISSC_MAX_PROC_DELAY_2MHZ   80

Maximum encoder processing delay at 2 MHz in valid bits/clock cycles (80 cycles)

BISSC_MAX_PROC_DELAY_5MHZ

#define BISSC_MAX_PROC_DELAY_5MHZ   200

Maximum encoder processing delay at 5 MHz in valid bits/clock cycles (200 cycles)

BISSC_MAX_PROC_DELAY_8MHZ

#define BISSC_MAX_PROC_DELAY_8MHZ   320

Maximum encoder processing delay at 8 MHz in valid bits/clock cycles (320 cycles)

BISSC_MAX_PROC_DELAY_10MHZ

#define BISSC_MAX_PROC_DELAY_10MHZ   400

Maximum encoder processing delay at 10 MHz in valid bits/clock cycles (400 cycles)

BISSC_CTS_BIT

#define BISSC_CTS_BIT   1

CTS (Control Transfer Status) bit value for control communication.

BISSC_ENC_ID_LEN

#define BISSC_ENC_ID_LEN   3

Number of Encoder ID bits in control communication (3 bits)

BISSC_ENC_ID_MASK

#define BISSC_ENC_ID_MASK   0x7

Bit mask for extracting Encoder ID (0x7 = 0b111)

BISSC_REG_ADDR_LEN

#define BISSC_REG_ADDR_LEN   7

Number of bits for Register address in control communication (7 bits)

BISSC_REG_ADDR_MASK

#define BISSC_REG_ADDR_MASK   0x7F

Bit mask for extracting Register address (0x7F = 0b1111111)

BISSC_RWS_LEN

#define BISSC_RWS_LEN   3

Number of RWS bits (3 bits)

BISSC_RWS_MASK

#define BISSC_RWS_MASK   0x7

Bit mask for extracting RWS bits (0x7 = 0b111)

BISSC_CTRL_READ_ACCESS

#define BISSC_CTRL_READ_ACCESS   0x5

RWS value for read access of encoder register (0x5 = 0b101)

BISSC_CTRL_WRITE_ACCESS

#define BISSC_CTRL_WRITE_ACCESS   0x3

RWS value for write access of encoder register (0x3 = 0b011)

BISSC_REG_DATA_LEN

#define BISSC_REG_DATA_LEN   8

Number of Register data bits (8 bits = 1 byte)

BISSC_REG_DATA_MASK

#define BISSC_REG_DATA_MASK   0xFF

Bit mask for extracting Register data (0xFF = 0b11111111)

BISSC_CTRL_STOP_LEN

#define BISSC_CTRL_STOP_LEN   2

Number of stop bits for control communication (2 bits: P and S)

P: stop bit indicating end of one control communication frame S: stop bit indicating end of sequential control communication sequence

BISSC_RX_SAMPLE_SIZE

#define BISSC_RX_SAMPLE_SIZE   7

Rx divisor value for 8x oversampling (divisor = 8, register value = 7)

8x oversampling samples each bit 8 times for robust clock recovery and data sampling. The register is programmed with (divisor - 1), so 8x oversampling uses value 7.

BISSC_RX_SAMPLE_SIZE_6X

#define BISSC_RX_SAMPLE_SIZE_6X   5

Rx divisor value for 6x oversampling (divisor = 6, register value = 5)

BISSC_RX_SAMPLE_SIZE_4X

#define BISSC_RX_SAMPLE_SIZE_4X   3

Rx divisor value for 4x oversampling (divisor = 4, register value = 3)

BISSC_POS_CRC_LEN

#define BISSC_POS_CRC_LEN   6

Number of position data CRC bits (6-bit CRC polynomial)

6-bit CRC protects position data integrity during transmission.

BISSC_EW_LEN

#define BISSC_EW_LEN   2

Number of Error and Warning bits (2 bits total)

BISSC_CTRL_CMD_CRC_LEN

#define BISSC_CTRL_CMD_CRC_LEN   4

Number of control command CRC bits (4-bit CRC polynomial)

4-bit CRC protects control communication command and response data.

BISSC_CTRL_CMD_CRC_MASK

#define BISSC_CTRL_CMD_CRC_MASK   0xF

Bit mask for extracting control command CRC (0xF = 0b1111)

BISSC_POS_DATA_LEN_DEFAULT

#define BISSC_POS_DATA_LEN_DEFAULT   12

Default position data length in bits (12 bits)

Used as a safe default value before actual encoder resolution is configured. Prevents garbage data interpretation during initialization.

BISSC_SAFETY_CRC_LEN

#define BISSC_SAFETY_CRC_LEN   16

Number of Safety CRC bits for BiSS Safety protocol (16-bit CRC)

BiSS Safety uses a 16-bit CRC along with sign-of-life counter.

BISSC_SIGN_OF_LIFE_LEN

#define BISSC_SIGN_OF_LIFE_LEN   6

Number of Sign-of-Life counter bits in BiSS Safety protocol (6 bits)

The 6-bit sign-of-life counter increments with each transaction to detect communication interruptions in BiSS Safety mode.

BISSC_MAX_FRAME_SIZE

#define BISSC_MAX_FRAME_SIZE   64

Maximum total frame size in bits (64 bits)

BiSS-C protocol uses 64-bit data frames. Total frame includes:

• Without Safety: Position Data + E/W(2) + CRC(6) <= 64 bits
• With Safety: Position Data + E/W(2) + sign-of-life(6) + safety CRC(16) <= 64 bits

BISSC_RX_ENABLE_FRACTIONAL_DIV

#define BISSC_RX_ENABLE_FRACTIONAL_DIV   (1<<15)

Enable fractional clock divider (1.5x) for Rx clock (bit 15 = 1)

Fractional divider allows achieving 1.5x clock division for frequencies that cannot be achieved with integer division.

BISSC_FREQ_1MHZ

#define BISSC_FREQ_1MHZ   1

Allowed BiSS-C communication frequency: 1 MHz.

BISSC_FREQ_2MHZ

#define BISSC_FREQ_2MHZ   2

Allowed BiSS-C communication frequency: 2 MHz.

BISSC_FREQ_5MHZ

#define BISSC_FREQ_5MHZ   5

Allowed BiSS-C communication frequency: 5 MHz.

BISSC_FREQ_8MHZ

#define BISSC_FREQ_8MHZ   8

Allowed BiSS-C communication frequency: 8 MHz.

BISSC_FREQ_10MHZ

#define BISSC_FREQ_10MHZ   10

Allowed BiSS-C communication frequency: 10 MHz.

BISSC_FIFO_BIT_IDX_8X_OS

#define BISSC_FIFO_BIT_IDX_8X_OS   4

Middle bit index for 8x oversampling (index 4 out of 0-7)

For 8x oversampling, bit 4 is the center sample point used for received data.

BISSC_FIFO_BIT_IDX_6X_OS

#define BISSC_FIFO_BIT_IDX_6X_OS   3

Middle bit index for 6x oversampling (index 3 out of 0-5)

BISSC_FIFO_BIT_IDX_4X_OS

#define BISSC_FIFO_BIT_IDX_4X_OS   2

Middle bit index for 4x oversampling (index 2 out of 0-3)

BISSC_CLEAR_STATUS_FLAG

#define BISSC_CLEAR_STATUS_FLAG   0x0

General purpose macro for clearing any status flag (value = 0)

BISSC_SET_STATUS_FLAG

#define BISSC_SET_STATUS_FLAG   0x1

General purpose macro for setting any status flag (value = 1)

BISSC_PRU_CORE_CLK_FREQ_200MHZ

#define BISSC_PRU_CORE_CLK_FREQ_200MHZ   200

PRU-ICSS Core Clock frequency: 200 MHz (in MHz units)

Used on devices like AM243x with 200 MHz PRU-ICSS core clock.

BISSC_PRU_CORE_CLK_FREQ_300MHZ

#define BISSC_PRU_CORE_CLK_FREQ_300MHZ   300

PRU-ICSS Core Clock frequency: 300 MHz (in MHz units)

Used on devices like AM263x with 300 MHz PRU-ICSS core clock.

BISSC_PRU_UART_CLK_FREQ_160MHZ

#define BISSC_PRU_UART_CLK_FREQ_160MHZ   160

PRU-ICSS UART Clock frequency: 160 MHz (in MHz units)

BISSC_PRU_UART_CLK_FREQ_192MHZ

#define BISSC_PRU_UART_CLK_FREQ_192MHZ   192

PRU-ICSS UART Clock frequency: 192 MHz (in MHz units)

BISSC_VALID_BIT_IDX

#define BISSC_VALID_BIT_IDX   (24U)

Valid bit index (value = 24)

BISSC_CLOCK_FRACTIONAL_DIVIDER

#define BISSC_CLOCK_FRACTIONAL_DIVIDER   (1.5)

Clock fractional divider factor (value = 1.5)

Fractional divider applied in BiSS-C clock calculations for achieving precise baud rates with oversampling.

BISSC_MHZ_TO_HZ

#define BISSC_MHZ_TO_HZ   (1000000U)

MHz to Hz conversion factor (value = 1000000)

Multiplication factor for converting frequency values from MHz to Hz. Used in clock configuration calculations.

BISSC_EW_FIELD_MASK

#define BISSC_EW_FIELD_MASK   (0x03U)

Error/Warning field bit mask (value = 0x03)

2-bit mask for extracting Error/Warning (E/W) field from BiSS-C position data.

BISSC_6BIT_FIELD_MASK

#define BISSC_6BIT_FIELD_MASK   (0x3FU)

6-bit field mask (value = 0x3F)

BISSC_SAFETY_CRC_FIELD_MASK

#define BISSC_SAFETY_CRC_FIELD_MASK   (0xFFFFU)

Safety CRC field mask (value = 0xFFFF)

16-bit mask for extracting safety CRC from BiSS-C Safety protocol data. BiSS Safety adds 16-bit CRC for enhanced data integrity.

BISSC_OPMODE_PERIODIC_CMP

#define BISSC_OPMODE_PERIODIC_CMP   (0x0U)

BiSS-C Periodic/Continuous operation mode using IEP compare (CMP) event.

In periodic mode, the PRU firmware automatically triggers BiSS-C transactions at regular intervals using IEP timer compare events, without host CPU intervention.

BISSC_OPMODE_HOST_TRIGGER

#define BISSC_OPMODE_HOST_TRIGGER   (0x1U)

BiSS-C Host trigger operation mode.

In host trigger mode, each BiSS-C transaction must be explicitly triggered by the host CPU via bissc_command_send or bissc_command_process.

BISSC_OPMODE_PERIODIC_CAP

#define BISSC_OPMODE_PERIODIC_CAP   (0x2U)

BiSS-C Periodic trigger with IEP CAP mode.

In periodic trigger CAP mode, the PRU firmware automatically triggers BiSS-C transactions based on IEP capture input events, without host CPU intervention.

BISSC_MEASURE_PROC_DELAY_DISABLE

#define BISSC_MEASURE_PROC_DELAY_DISABLE   (0x0U)

Disable encoder processing delay measurement (value = 0x0)

BISSC_MEASURE_PROC_DELAY_ENABLE

#define BISSC_MEASURE_PROC_DELAY_ENABLE   (0x1U)

Enable encoder processing delay measurement (value = 0x1)

BISSC_CFG_REG_SIZE

#define BISSC_CFG_REG_SIZE   (4U)

IEP cap 0 register , cslr common file does not have defined cap registers FIXME: Remove these definitions once they are available in cslr_common.h.

BISSC_CSL_ICSS_PR1_IEP0_SLV_CAP0_REG0

#define BISSC_CSL_ICSS_PR1_IEP0_SLV_CAP0_REG0   (CSL_ICSS_PR1_IEP0_SLV_CAP_CFG_REG + 2U*BISSC_CFG_REG_SIZE)

BISSC_8_BYTE_REG_OFFSET

#define BISSC_8_BYTE_REG_OFFSET   (8U)

8-byte register offset for IEP registers

BISSC_IEP_MAX_CAP_EVENT

#define BISSC_IEP_MAX_CAP_EVENT   (0x8U)

Maximum number of IEP capture events (0-7)

BISSC_IEP_MAX_CMP_EVENT

#define BISSC_IEP_MAX_CMP_EVENT   (0x10U)

Maximum number of IEP compare events (0-15)

Typedef Documentation

bissc_handle

typedef bissc_config* bissc_handle

BiSS-C handle type.

Opaque handle to a BiSS-C instance. Obtained from bissc_init() and used in all subsequent BiSS-C API calls.