Encoder Examples Debug Guide

This section provides a debugging guide for troubleshooting issues that may arise during testing or development.

Encoder Register Configuration

The ICSSM_PR1_CFG_SLV registers from offset 0xE0 to 0x11C are allocated for encoder configuration. To review and verify the encoder settings:

Halt the Arm® Cortex®-R5F core
Open the memory browser window
Enter the address of the ICSSM_PR1_CFG_SLV register and view the configured values

Note: Ensure you are entering the correct base address for encoder registers. Each ICSS instance has a different address for the CFG register.

For detailed register descriptions, refer to: Table 4-415 of the AM263x Sitara Processors Technical Reference Manual Register Addendum

Key registers and their configurations:

ICSS_PRU0_ED_RX_CFG_REG
- Division factor for Rx clock
- RX clock source
- Polarity of the RX Start Bit
- RX Over Sample size
ICSS_PRU0_ED_TX_CFG_REG
- Division factor for Tx clock
- Load share mode configuration
- TX clock source
ICSS_PRU0_ED_CH0_CFG0_REG
- RX frame size
- TX frame size
- TX wire delay configuration
ICSS_PRU0_ED_CH0_CFG1_REG
- Rx arm counter value if Rx auto arm is enabled
- TST delay
ICSS_GPCFG0_REG
- Controls the ICSS wrap mux select (should be in EnDAT mode)

PRU-ICSS 3 channel register view

Hardware Setup and Pin Configuration

The RS485 interface card, control card, and encoder should be connected to the correct PRU GPIO pins mapped for the Encoder interface Peripheral IF mode. All associated pins must be selected in SysConfig.

LP-AM263P + BP-AM2BLDCSERVO Booster Pack Pin Multiplexing for SDK example

Pin name	Jumper number	Function
PR0_PRU0_GPIO3	J2.19	Channel 1 clock
PR0_PRU0_GPO4	J2.17	Channel 1 transmit
PR0_PRU0_GPO5	J2.13	Channel 1 transmit enable
PR0_PRU0_GPI10	J1.8	Channel 1 receive
GPIO Pin (SDFM0_D1/D13)	J8.73	Enable encoder voltage in Axis 1 of BP (Fix this pin to high with SoC GPIO mode)

PRU Firmware Debug

For PRU-related issues, verify that the application is loading the PRU firmware into the correct PRU core. If firmware loading fails:

Check the PRU core selection
Verify the PRU slice selection
Review application-level configuration

Debugging Steps for PRU Core with Loaded Firmware:

Import the PRU firmware for the target core
Build the firmware
Open the debug window and connect to the PRU core
Load symbols into the connected core:
- Click the Load button
- Select Load Symbols
- Load the firmware .out file from the firmware project
After symbols are loaded, use the step-into button to execute debug commands

Load EnDAT RTU firmware symbols

Multi-channel modes

Multi-channel with single PRU mode

Note: This subsection is applicable for BiSS-C, EnDat, Nikon A-format, and Tamagawa only.

Data transmission and reception must happen simultaneously on all channels.
The encoder configuration and cable length should be the same on all channels.
If encoders across channels don't respond at the same time, this mode will not work. Load share configuration should be used instead.

Multi-channel with load share mode

Note: This subsection is not applicable for EnDAT3.

Data transmission and reception can happen independently on all channels.
After a command is sent, all channels wait for a response and process the response independently. However, all channels must finish processing before the next command can be triggered. (This restriction does not apply to HDSL. HDSL channels can continue operating independently.)

Periodic Trigger Mode

Note: This subsection is not applicable for HDSL.

SDK examples uses IEP compare/capture event(s) to trigger commands in periodic mode. Firmware triggers a R5F interrupt after getting a response from the encoder. The application code uses a callback function to clear the PRU interrupt, which can be modified as per the use case. CMP/CAP event number can be configured using SysConfig module of encoder. Refer the example specific page for details (see Periodic Trigger Modes).

When programming the values for periodic trigger CMP/CAP mode, ensure that the command send and receive can complete within the cycle time. In multi-channel, ensure that command completion for timings for all channels are considered. Incorrect values may send PRU FW in bad state. Also, refer to encoder specifications to ensure that requirement for mimimum interval between two commands is met.

IEP Registers Configuration

The Industrial Ethernet Peripheral (IEP) is used for periodic trigger mode. If the IEP is not configured correctly, periodic trigger mode will not work.

To verify IEP configuration:

Check if the IEP is running by examining IEP_COUNT_REG0/1 registers
Verify counter increment by monitoring count values
Review IEP_CMP_CFG_REG to ensure all compare events are properly configured for trigger mode
Check IEP_CMP_STATUS_REG to verify that corresponding compare events are setting status flags correctly
Validate that Compare Registers are configured with correct trigger point values

Note: Ensure you are entering the correct address for IEP registers. Each ICSS instance has a different base address for the IEP registers.

PRU-ICSS IEP register view

PRU-ICSS IEP CMP events register view

For detailed register descriptions, refer to: Table 4-417 of the AM263x Sitara Processors Technical Reference Manual Register Addendum

Interrupt Controller Internal Signals Mapping

If you experience missing PRU interrupts or incorrect IRQ mapping, verify the interrupt mapping between PRU and R5F.

The host interrupt numbers defined in "*_periodic_trigger.c" file(s) in SDK examples (e.g., ICSS_PRU_ENDAT_INT_NUM) must match the interrupt channel assignments in SysConfig PRU(ICSS) module -> INTC section -> INTC Host Interrupt
Host interrupt channels route PRU events to the R5F core
Mapping: Host Interrupt 2-9 in SysConfig = HOST_INTR_PEND_0-7 registers
If the host interrupt assignments are changed in SysConfig, macros in "*_periodic_trigger.c" file(s) need to be updated accordingly to maintain proper interrupt delivery from PRU to R5F.
The INTC event numbers defined "*_periodic_trigger.c" file(s) must match the corresponding definitions in the PRU firmware header file (e.g., "source/position_sense/endat/firmware/endat_icss_reg_defs.h")
These event numbers are used for communication between the R5F and PRU firmware. Any changes to these values must be synchronized between both files (firmware and application) to ensure proper interrupt handling.

For example, the EnDAT single channel example uses:

PRU Event: 18: pr0_pru_mst_intr[2]_intr_req
Channel: 2
Host Interrupt: 2

PRU-ICSS INTC view

The interrupt service routine (ISR) configuration is implemented in endat_periodic_trigger.c. Here's a key code snippet showing the configuration:

/* Register and enable PRU FW interrupt */
HwiP_Params_init(&hwi_params);
hwi_params.intNum   = ICSS_PRU_ENDAT_INT_NUM;
hwi_params.callback = &endat_pru_irq_handler;
hwi_params.args     = pruicss_handle;
hwi_params.isPulse  = FALSE;
hwi_params.isFIQ    = FALSE;
status              = HwiP_construct(&gEndatHwiObject[CONFIG_ENDAT0][0], &hwi_params);
DebugP_assert(status == SystemP_SUCCESS);
 
/* PRU FW IRQ handler */
void endat_pru_irq_handler(void *pruicss_handle)
{
   if(pruicss_handle == NULL)
   {
      return;
   }
 
   /* Increment IRQ count */
#if(CONFIG_ENDAT0_MODE == ENDAT_MODE_MULTI_CHANNEL_MULTI_PRU)
   /* In load share mode, index 1 is used for channel 1 connected to PRU */
   gPruEndatIrqCnt[CONFIG_ENDAT0][1]++;
#else
   /* In single PRU mode, index 0 is used for any channel connected to PRU */
   gPruEndatIrqCnt[CONFIG_ENDAT0][0]++;
#endif
   /* Clear interrupt at source */
   PRUICSS_clearEvent((PRUICSS_Handle)pruicss_handle, PRU_TRIGGER_HOST_ENDAT_EVT);
}

The R5F interrupt number "ICSS_PRU_ENDAT_INT_NUM" and PRU event number "PRU_TRIGGER_HOST_ENDAT_EVT" and is defined in endat_periodic_trigger.h.

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