Introduction

The HDSL firmware running on ICSS-PRU provides a well-defined interface to execute the HDSL protocol.

Note: This implementation using Peripheral input/output mode of PRU-ICSS. Refer Peripheral IF mode for more details.

Features Supported

Safe position
Fast position, speed
Communication status
External pulse synchronization using IEP CAP (capture) event
- 1 to 10 frames per cycle
- 8 kHz to 50 kHz cycle frequency
- Uses IEP CAP6 for PRU slice 1 and CAP7 for PRU slice 0 (NOTE: CAP6 and CAP7 support falling edge detection as well. In HDSL, rising edge is used always.)
Register interface to be compatible with SICK HDSL FPGA IP Core (apart from the differences listed in TI HDSL Exceptions List)
Parameter channel communication
- Short message
- Long message
Safety
Pipeline Channel Data
Single channel support (with PRU Core Clock frequency of 225 MHz) per PRU slice
- Cores used: PRU0/PRU1
Multi-channel support (with PRU Core Clock frequency of 300 MHz) per PRU slice
- Support for multi-channel encoders of different make under load share mode (Refer Load Share Mode for more details)
- Cores used: RTU_PRU0/RTU_PRU1 for channel 0, PRU0/PRU1 for channel 1 and TX_PRU0/TX_PRU1 for channel 2
- Three channel example on TMDS243EVM and two channel example on LP-AM243 (tested on ICSSG0 instance and PRU1 slice)
Tested with three different encoder makes (EDM35, EKS36, EKM36)

Attention: Channel 2 can be enabled only if channel 0 is enabled because of the code overlay scheme needed in TX-PRU. See Overlay Scheme for TX-PRU for more details.

Features Not Supported

In general, peripherals or features not mentioned as part of the "Features Supported" section are not supported, including the below:

100m cable
Pipeline Channel Status

SysConfig Features

Note: It is strongly recommend to use SysConfig where it is available instead of using direct SW API calls. This will help simplify the SW application and also catch common mistakes early in the development cycle.

Attention: For each PRU-ICSS slice being used for HDSL, one module instance should be created in SysConfig. For up to 3 channels using 1 slice, only 1 instance needs to be added.

SysConfig can be used to configure the following:

Selecting the ICSSG instance (Tested on ICSSG0)
Selecting the ICSSG PRU slice (Tested on ICSSG0-PRU1)
Configuring PINMUX
Channel selection
Selecting multi Channel with encoders of different make using load share mode
Enabling SA Mux mode
Mode Selection (Free Run / Sync mode)
Booster Pack Support: Enable when using BP-AM2BLDCSERVO

Note: HDSL firmware supports operation with PRU-ICSS Core Clock running at 225/300 MHz only due to clock divider requirements.

PRU-ICSS Resource Usage

Utilizes the Peripheral IF mode (3-channel peripheral interface mode) for HDSL communication. Maximum of 3 channels are available per PRU slice. (Refer Peripheral IF mode for more details)
Each channel has 4 pins (Clock, Data out, Data in, Output enable)
Following table contains details of memory usage, IEP usage and interrupt controller usage:

Attention: In addition to the following resources used by PRU firmware, SDK examples also configure ICSSG0 IEP1 CMP1 for generating SYNC OUT0 used as sync pulse input.

Configuration per slice	PRU Core(s)	Memory Usage	IEP Usage	Interrupt Controller (INTC) Usage	Description
Single channel	PRUx	DMEM: 1773 Bytes: 256B for HDSL Registers (0x0 to 0xFF) + 1517B for LUTs (0x100 to 0x6EC) IMEM: ~ 7.6 kB (For Sync mode. For Free Run mode, less IMEM is used)	IEP1: CAP7 (slice 0) or CAP6 (slice 1)	INTC events/inputs numbers 16, 18, 19, 20, 21, 22 (pr[0/1]_pru_mst_intr[0/2/3/4/5/6]_intr_req) are used to trigger interrupts to Arm® Cortex®-R5F for EVENT, V-frame, H-frame, EVENT_S and H-frame respectively	IEP CAP event is used for external pulse synchronization in Sync mode only
Multi-channel with load share across 3 PRU cores (Refer Load Share Mode for more details)	PRUx	DMEM: 5101 Bytes: 3 * 256B for HDSL Registers per channel (0x0 to 0xFF, 0x700 to 0x7FF and 0xE00 to 0xEFF) + 1517B for LUTs (0x100 to 0x6EC) + 2816 Bytes for instructions storage related to TXPRU dynamic overlay (0x1500 to 0x1FFF) IMEM (per core): ~ 7.44 kB (For Sync mode. For Free Run mode, less IMEM is used)	IEP1: CAP7 (slice 0) or CAP6 (slice 1)	INTC events/inputs numbers 16, 18, 19, 20, 21, 22 (pr[0/1]_pru_mst_intr[0/2/3/4/5/6]_intr_req) are used to trigger interrupts to Arm® Cortex®-R5F for EVENT, V-frame, H-frame, EVENT_S and H-frame respectively	IEP CAP event is used for external pulse synchronization in Sync mode only
	RTU_PRUx
	TX_PRUx

Note: For pin usage see Pin Multiplexing page.

HDSL Design

HDSL Protocol Design explains the design in detail.

Register List

TI HDSL Register List contains the description of registers in TI's HDSL implementation.

Exceptions

TI HDSL Exceptions List lists the exceptions in TI's HDSL implementation when compared with SICK HDSL FPGA IP Core. Please note that not all the corresponding register fields are implemented, and see the description of register for more details.

Datasheet

Synchronization Pulse Jitter

Synchronization Pulse Jitter is under 100ns. Please refer to the image below for jitter calculation waveforms.

HDSL Sync mode waveforms for 2 channels

HDSL Sync mode jitter analysis

Protocol Package Lengths with different ES and Sync Pulse Frequency values

NOTE: Images below show TX_EN signal in "Red" and RX signal in "Yellow".

ES Value	Cycle Time (in us)	Cycle Frequency (in kHz)	Observed Protocol Package Length (in us)
1	25	40	25.06
1	20	50	19.942
2	25	40	Between 12.26 and 12.80
5	62.5	16	Between 11.94 and 12.60
10	125	8	Between 11.94 and 12.90

Example

HDSL Diagnostic

API

APIs for HDSL Encoder

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