Introduction

The HDSL firmware running on ICSS-PRU provides a defined well interface to execute the HDSL protocol.

Features Supported

Safe position
Fast position, speed
Communication status
External pulse synchronization
- 1 to 10 frames per cycle
- 8 kHz to 50 kHz cycle frequency
Register interface to be compatible with SICK HDSL FPGA IP Core (apart from the differences listed in TI HDSL Exceptions List)
Parameter channel communication
- Short message
- Long message
Safety
Pipeline Channel Data
Three channel support using single PRU-ICSSG slice
- Three channel support on am243x-evm
- Two channel support on am243x-lp
Tested with three different encoder makes (EDM35, EKS36, EKM36)

Note: Channel 2 can be enabled only if channel 0 is enabled because of code overlay scheme needed in TX-PRU. See Overlay Scheme for TX-PRU for more details

Features Not Supported

In general, peripherals or features not mentioned as part of "Features Supported" section are not supported, including the below

100m cable
Pipeline Channel Status

SysConfig Features

Note: It is strongly recommend to use SysConfig where it is available instead of using direct SW API calls. This will help simplify the SW application and also catch common mistakes early in the development cycle.

SysConfig can be used to configure things mentioned below:

Selecting the ICSSG PRU slice instance.(Tested on ICSSG0-PRU1)
Configuring PINMUX
Channel selection
Mode Selection (Free run/Sync mode)
Hardware selection (Booster Pack for am243x-lp)

HDSL Design

HDSL Protocol Design explains the design in detail.

Register List

TI HDSL Register List contains the description of registers in TI's HDSL implementation. Please note that all the corresponding register fields are not implemented.

Exceptions

TI HDSL Exceptions List lists the exceptions TI's HDSL implementation when compared with SICK HDSL FPGA IP Core. Please note that all the corresponding register fields are not implemented.

Datasheet

Synchronization Pulse Jitter

Synchronization Pulse Jitter is under 100ns. Please refer to the image below for jitter calculation waveforms.

HDSL Sync mode waveforms for 2 channels

HDSL Sync mode jitter analysis

Protocol Package Lengths with different ES and Sync Pulse Frequency values

NOTE: Images below show TX_EN signal in "Red" and RX signal in "Yellow".

ES Value	Cycle Time (in us)	Cycle Frequency (in kHz)	Observed Protocol Package Length (in us)
1	25	40	25.06
1	20	50	19.942
2	25	40	Between 12.26 and 12.80
5	62.5	16	Between 11.94 and 12.60
10	125	8	Between 11.94 and 12.90

Example

HDSL Diagnostic

API

APIs for HDSL Encoder

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