HDSL

Table of Contents

• Introduction
• Features Supported
• Features Not Supported
• SysConfig Features
• ICSS PRU Resource Usage
• HDSL Design
• Register List
• Exceptions
• Datasheet
  • Synchronization Pulse Jitter
  • Protocol Package Lengths with different ES and Sync Pulse Frequency values
• Example
• API

Introduction

The HDSL firmware running on ICSS-PRU provides a well-defined interface to execute the HDSL protocol.

Note

This implementation using Peripheral input/output mode of PRU-ICSS. Refer Peripheral IF mode for more details.

Features Supported

• Safe position
• Fast position, speed
• Communication status
• External pulse synchronization
  • 1 to 10 frames per cycle
  • 8 kHz to 50 kHz cycle frequency
• Register interface to be compatible with SICK HDSL FPGA IP Core (apart from the differences listed in TI HDSL Exceptions List)
• Parameter channel communication
  • Short message
  • Long message
• Safety
• Pipeline Channel Data
• Support for multi-channel encoders of different make under load share mode (Refer Load Share Mode for more details)
  • Three channel support on TMDS243EVM and 2 channel support on LP-AM243 (tested on ICSSG0 instance and PRU1 slice).
• Tested with three different encoder makes (EDM35, EKS36, EKM36)

Note

Channel 2 can be enabled only if channel 0 is enabled because of the code overlay scheme needed in TX-PRU. See Overlay Scheme for TX-PRU for more details.

Features Not Supported

In general, peripherals or features not mentioned as part of the "Features Supported" section are not supported, including the below:

• 100m cable
• Pipeline Channel Status

SysConfig Features

Note

It is strongly recommend to use SysConfig where it is available instead of using direct SW API calls. This will help simplify the SW application and also catch common mistakes early in the development cycle.

SysConfig can be used to configure the following:

• Selecting the ICSS PRU slice instance (Tested on ICSSG0-PRU1 for AM243x (EVM, LP) and ICSSM1-PRU0 for LP-AM261)
• Configuring PINMUX
• Channel selection
• Mode Selection (Free run/Sync mode)
• Hardware selection (Booster Pack for LP-AM243 and LP-AM261)

ICSS PRU Resource Usage

Configuration	PRU Core	Memory Usage	IEP Usage	Other Peripheral Usage	Description
Single channel	PRUx	DMEM: 1773 Bytes: 256B for HDSL Registers (0x0 to 0xFF) + 1517B for LUTs (0x100 to 0x6ED) IMEM: 7284 Bytes	IEP1: CMP1	INTC events/inputs numbers 16, 18, 19, 20, 21, 22 (pr[0/1]_pru_mst_intr[0/2/3/4/5/6]_intr_req) are used to trigger interrupts to Arm® Cortex®-R5F for EVENT, V-frame, H-frame, EVENT_S and H-frame respectively	IEP, CMP events and INTC signal are used only in periodic continuous mode.
Multi-channel with load share across 3 PRU cores (Refer Load Share Mode for more details)	PRUx	DMEM:5101 Bytes: 3 * 256B for HDSL Registers per channel (0x0 to 0xFF, 0x700 to 0x7FF and 0xE00 to 0xEFF) + 1517B for LUTs (0x100 to 0x6ED) + 2816 Bytes for instructions storage related to TXPRU dynamic overlay (0x1500 to 0x1FFF) IMEM: 7428 Bytes	IEP1: CMP1	INTC events/inputs numbers 16, 18, 19, 20, 21, 22 (pr[0/1]_pru_mst_intr[0/2/3/4/5/6]_intr_req) are used to trigger interrupts to R5F for EVENT, V-frame, H-frame, EVENT_S and H-frame respectively	IEP, CMP events and INTC signal are used only in periodic continuous mode.
	RTU_PRUx
	TX_PRUx

Note

For pin usage see Pin Multiplexing page.

HDSL Design

HDSL Protocol Design explains the design in detail.

Register List

TI HDSL Register List contains the description of registers in TI's HDSL implementation.

Exceptions

TI HDSL Exceptions List lists the exceptions in TI's HDSL implementation when compared with SICK HDSL FPGA IP Core. Please note that not all the corresponding register fields are implemented, and see the description of register for more details.

Datasheet

Synchronization Pulse Jitter

• Synchronization Pulse Jitter is under 100ns. Please refer to the image below for jitter calculation waveforms.

HDSL Sync mode waveforms for 2 channels

HDSL Sync mode jitter analysis

Protocol Package Lengths with different ES and Sync Pulse Frequency values

NOTE: Images below show TX_EN signal in "Red" and RX signal in "Yellow".

ES Value	Cycle Time (in us)	Cycle Frequency (in kHz)	Observed Protocol Package Length (in us)
1	25	40	25.06
1	20	50	19.942
2	25	40	Between 12.26 and 12.80
5	62.5	16	Between 11.94 and 12.60
10	125	8	Between 11.94 and 12.90

Example

HDSL Diagnostic

API

APIs for HDSL Encoder

Note

Arm is a registered trademark of Arm Limited (or its subsidiaries or affiliates) in the US and/or elsewhere.