EnDat

Table of Contents

• Introduction
• Features Supported
• Features Not Supported
  • Limitations
• SysConfig Features
• ICSS PRU Resource Usage
• ENDAT Design
• Example
• API

Introduction

EnDat is a bidirectional interface for position encoders. During EnDat operation, the EnDat receiver receives position information from the EnDat position encoder.

Note

This implementation using Peripheral input/output mode of PRU-ICSS. Refer Peripheral IF mode for more details.

Features Supported

• EnDat 2.2 command set
• EnDat 2.1 command set
• Interrupted and continuous clock mode
• Cable length up to 100m @8MHz
• Propagation delay compensation (capable of handling different propagation delays of different channels in concurrent multi-channel configuration) - Automatic estimation of propagation delay
• Receive on-the-fly CRC verification of position, parameters and additional information
• Two modes of operation - host trigger and periodic trigger
• Channel select
• Concurrent multi-channel support (up to 3 encoders with identical part numbers @ 8MHz maximum)
  • In this mode, data transmission and reception must happen simultaneously on all channels.
  • The encoder configuration and cable length should be the same on all channels.
  • If encoders across channels don't respond at the same time, this mode will not work. Load share configuration should be used instead.
• "Multi Channel with encoders of different make" using load share mode (Refer Load Share Mode for more details)
  • In this mode, data transmission and reception can happen independently on all channels.
  • After a command is sent, all channels wait for a response and process the response independently. However, all channels must finish processing before the next command can be triggered.
• Safety Readiness: Recovery time
• Clock up to 16MHz with single channel and load share mode (multi-channel)

  Note

  In three channel interface of PRU-ICSS, receive (Rx) is oversampled at 8x of send (Tx). Therefore, the encoder interface frequency "f" should be such that Tx source clock value is divisible by "f" and Rx source clock value is divisible by "8*f".

• Possible interface speeds with different source clock combinations:

  Clock Source	Interface Speed
  PRU UART Clock (192 MHz)	1MHz, 2MHz, 4MHz, 6MHz, 8MHz, 12MHz, 16MHz
  PRU Core Clock (200 MHz)	1MHz, 5MHz

Features Not Supported

In general, peripherals or features not mentioned as part of "Features Supported" section are not supported in this release, including the below:

• Independent clocks on multi channel mode.
• Continuous clock mode in Multi-channel single PRU mode

Limitations

This section describes known limitations of the current implementation in multi-channel single PRU mode.

• Clock above 8 MHz: it is not possible to oversample, downsample and store one bit for all three channels in one clock cycle time.
• Reset command CRC failure: The encoder which takes more time in reset operation will show CRC failure because the reset time is not the same for each encoder so the acknowledgment will not arrive at the same time for all encoders at the EnDat receiver end.

SysConfig Features

Note

It is strongly recommend to use SysConfig where it is available instead of using direct SW API calls. This will help simplify the SW application and also catch common mistakes early in the development cycle.

SysConfig can be used to configure things mentioned below:

• Selecting the ICSS instance.
• Selecting the ICSSG PRU slice. (Tested on ICSSG0-PRU1)
• Configuring PINMUX.
• Channel selection.
• Selecting "Multi Channel with encoders of different make" using load share mode.
• Enabling SA Mux mode
• Selecting RX and TX source clock

ICSS PRU Resource Usage

Configuration	PRU Core	Memory Usage	IEP Usage	Other Peripheral Usage	Description
Single channel	PRUx	DMEM:160 Bytes, from offset 0x00 to 0xA0 offset IMEM: 5.4 KB TCMB0: 40 Bytes, 40 Bytes of memory can be located anywhere within the offset range 0x00 to 0x78, depending on the selected channel.	IEP0: CMP0 and CMP3	INTC event/input number 18 (pr[0/1]_pru_mst_intr[2]_intr_req) is used to trigger interrupt to Arm® Cortex®-R5F	IEP, CMP events and INTC signal are used only in periodic continuous mode.
Multi-channel with single PRU core	PRUx	DMEM: 160 Bytes, from offset 0x00 to 0xA0 offset IMEM: 6.2 KB TCMB0:120 Bytes, from offset 0x00 to 0x78 offset	IEP0: CMP0 and CMP3	INTC event/input number 18 (pr[0/1]_pru_mst_intr[2]_intr_req) is used to trigger interrupt to R5F	IEP, CMP events and INTC signal are used only in periodic continuous mode Note Multi-Channel single PRU firmware requires more than 6KB IMEM, so it cannot run on TX PRU
Multi-channel with load share across 3 PRU cores	PRUx	DMEM: 160 Bytes, from offset 0x00 to 0xA0 offset PRU_IMEM: 4 KB RTU_IMEM: 4 KB TX_IMEM: 4 KB TCMB0:120 Bytes, from offset 0x00 to 0x78 offset	IEP0: CMP0, CMP3, CMP5 and CMP6	INTC events/inputs number 18, 19 and 20 (pr[0/1]_pru_mst_intr[2/3/4]_intr_req) are used to trigger interrupts to R5F	IEP, CMP events and INTC signals are used only in periodic continuous mode.
	RTU_PRUx
	TX_PRUx

Note

For pin usage, see Pin Multiplexing section.

ENDAT Design

EnDat Protocol Design explains the design in detail.

Example

EnDAT Diagnostic

API

APIs for ENDAT Encoder

Note

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