BISS-C

Table of Contents

• Introduction
• Features Supported
• Features Not Supported
• SysConfig Features
• ICSS PRU Resource Usage
• BISS-C Design
• Example
• API

Introduction

BiSS is an open-source digital interface for sensors and actuators. BiSS stands for bidirectional serial synchronous. The BiSS interface was introduced by iC-Haus GmbH as an open-source protocol in 2002. BiSS-C mode is the continuous mode in which the BiSS-C interface receiver reads out the position data cyclically. Control communication is available for the receiver to send commands to the encoders and to read and write the encoder local registers. The BiSS interface is used in position-control applications. The interface enables a complete closed-loop position control system by providing the real-time position feedback to the receiver to control the motor.

BiSS Safety is a profile definition for BiSS that has been certified by TÜV Rheinland for safety-critical applications up to SIL3 according to IEC61508:2010. BiSS Safety uses the concept of a "Black Channel" transmission and specifies the data channel contents in order to ensure failure mode detection as defined in IEC61784-3 using redundant position words, different CRC polynomials and a sign-of-life counter. BiSS Safety is fully compatible with BiSS and all of its features including line delay compensation, processing times. BiSS Safety is implemented by assuming 2 encoders connected in daisy chain, one will send CPW and another one will send SPW. Daisy chaining is also possible on top of safety (2 encoders dedicated safety - one for CPW and another one for SPW) up to 3 encoders per channel.

Note

This implementation using Peripheral input/output mode of PRU-ICSS. Refer Peripheral IF mode for more details.

Features Supported

• BiSS-C interface receiver for point-to-point communication
• Support for single channel implementation with one encoder
• Receive on-the-fly CRC verification of position and control data
• Interface speed of 1, 2, 5, 8, and 10 MHz
• Support for oversampling ratio with different interface speeds

  Clock Source	Interface Speed
  	1 MHz	2 MHz	5 MHz	8 MHz	10 MHz
  PRU UART Clock (192 MHz)	8x	8x	Not tested	8x	Not tested
  PRU Core Clock (200 MHz)	Not tested	Not tested	8x	Not tested	4x
  PRU Core Clock (300 MHz)	Not tested	Not tested	8x with fractional div	Not tested	4x with Fractional div

• Two modes of operation - host trigger and periodic trigger
• Support for control communication
• Support for automatic processing delay detection and compensation
• Support for multiple encoders connected via daisy-chain configuration (up to 3 encoders)
• Support for concurrent multi-channel support on a single PRU (up to 3 identical encoders)
  • In this mode, data transmission and reception must happen simultaneously on all channels.
  • The encoder configuration and cable length should be the same on all channels.
  • If encoders across channels don't respond at the same time, this mode will not work. Load share configuration should be used instead.
• Support for multi-channel encoders of different make under load share mode (Refer Load Share Mode for more details)
  • In this mode, data transmission and reception can happen independently on all channels.
  • After a command is sent, all channels wait for a response and process the response independently. However, all channels must finish processing before the next command can be triggered.
• Support for up to 100 meter cable
• Readiness for BiSS Safety profile by supporting 16 bit CRC and sign-of-life counter

Features Not Supported

In general, peripherals or features not mentioned as part of "Features Supported" section are not supported in this release, including the below:

• BISS Line
• Independent clocks on multi channel mode.

SysConfig Features

Note

It is strongly recommend to use SysConfig where it is available instead of using direct SW API calls. This will help simplify the SW application and also catch common mistakes early in the development cycle.

SysConfig can be used to configure things mentioned below:

• Selecting the ICSSG instance. (Tested on ICSSG0)
• Selecting the ICSSG PRU slice. (Tested on ICSSG0-PRU1)
• Configuring PINMUX.
• Frequency selection.
• Channel selection.
• Selecting Multi Channel with encoders of different make using load share mode.
• Enabling SA Mux mode
• Selecting clock source

Note

BiSS-C firmware supports operation with ICSS Core Clock running at 200 MHz/300 MHz frequency or ICSS UART Clock running at 192 MHz only. ICSS Core Clock at 225/250/333 MHz is not supported due to clock divider requirements.

ICSS PRU Resource Usage

Configuration	PRU Core	Memory Usage	IEP Usage	Other Peripheral Usage	Description
Single channel	PRUx	DMEM: (0x0 to 0x10A) 272 Bytes IMEM: 3080 Bytes	IEP0: CMP0 and CMP3	INTC event/input number 18 (pr[0/1]_pru_mst_intr[2]_intr_req) is used to trigger interrupt to Arm® Cortex®-R5F	IEP, CMP events and INTC signal are used only in periodic continuous mode.
Multi-channel with single PRU core	PRUx	DMEM: (0x0 to 0x10A) 272 Bytes IMEM: 3380 Bytes	IEP0: CMP0 and CMP3	INTC event/input number 18 (pr[0/1]_pru_mst_intr[2]_intr_req) is used to trigger interrupt to R5F	IEP, CMP events and INTC signal are used only in periodic continuous mode.
Multi-channel with load share across 3 PRU cores	PRUx	DMEM: (0x0 to 0x10A) 272 Bytes IMEM: 3484 Bytes	IEP0: CMP0, CMP3, CMP5 and CMP6	INTC events/inputs number 18, 19 and 20 (pr[0/1]_pru_mst_intr[2/3/4]_intr_req) are used to trigger interrupts to R5F	IEP, CMP events and INTC signals are used only in periodic continuous mode.
	RTU_PRUx
	TX_PRUx

Note

For pin usage, see Pin Multiplexing section.

BISS-C Design

BISS-C Protocol Design explains the design in detail.

Example

BISS-C Diagnostic

API

APIs for BiSSC Encoder

Note

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