AM243x Motor Control SDK  2025.00.00
BISS-C

Table of Contents

Introduction

BiSS is an open-source digital interface for sensors and actuators. BiSS stands for bidirectional serial synchronous. The BiSS interface was introduced by iC-Haus GmbH as an open-source protocol in 2002. BiSS-C mode is the continuous mode in which the BiSS-C interface receiver reads out the position data cyclically. Control communication is available for the receiver to send commands to the encoders and to read and write the encoder local registers. The BiSS interface is used in position-control applications. The interface enables a complete closed-loop position control system by providing the real-time position feedback to the receiver to control the motor.

BiSS Safety is a profile definition for BiSS that has been certified by TÜV Rheinland for safety-critical applications up to SIL3 according to IEC61508:2010. BiSS Safety uses the concept of a "Black Channel" transmission and specifies the data channel contents in order to ensure failure mode detection as defined in IEC61784-3 using redundant position words, different CRC polynomials and a sign-of-life counter. BiSS Safety is fully compatible with BiSS and all of its features including line delay compensation, processing times. BiSS Safety is implemented by assuming 2 encoders connected in daisy chain, one will send CPW and another one will send SPW. Daisy chaining is also possible on top of safety (2 encoders dedicated safety - one for CPW and another one for SPW) up to 3 encoders per channel.

Note
This implementation using Peripheral input/output mode of PRU-ICSS. Refer Peripheral IF mode for more details.

Features Supported

  • BiSS-C interface receiver for point-to-point communication
  • Support for single channel implementation with one encoder
  • Receive on-the-fly CRC verification of position and control data
  • Interface speed of 1, 2, 5, 8, and 10 MHz
  • Support for oversampling ratio with different interface speeds
    Clock Source Interface Speed
    1 MHz 2 MHz 5 MHz 8 MHz 10 MHz
    PRU UART Clock (192 MHz) 8x 8x Not tested 8x Not tested
    PRU Core Clock (200 MHz) Not tested Not tested 8x Not tested 4x
    PRU Core Clock (300 MHz) Not tested Not tested 8x with fractional div Not tested 4x with Fractional div
  • Two modes of operation - host trigger and periodic trigger
  • Support for periodic trigger using PRU-ICSS IEP timer module
  • Support for single byte register communication using control communication
  • Support for automatic processing delay detection and compensation
  • Support for multiple encoders connected via daisy-chain configuration (up to 3 encoders)
  • Support for concurrent multi-channel support on a single PRU
    • Up to 3 channels with identical number of encoders of the same frequency connected to all configured channels.
    • Data transmission and reception must happen simultaneously on all channels.
    • The encoder configuration and cable length should be the same on all channels.
    • If encoders across channels don't respond at the same time, this mode will not work. Load share configuration should be used instead.
  • Support for multi-channel with encoders of different make and different numbers of encoders connected across channels under load share mode (Refer Load Share Mode for more details).
    • Up to 3 channels with encoders of the same frequency connected to all configured channels.
    • Data transmission and reception can happen independently on all channels.
    • After a command is sent, all channels wait for a response and process the response independently. However, all channels must finish processing before the next command can be triggered.
  • Same clock frequency for all channels in multi channel mode within the same PRU-ICSS slice
    • Different PRU slices can simultaneously handle encoders operating at different frequencies
  • Support for up to 100 meter cable
  • Readiness for BiSS Safety profile by supporting 16 bit CRC and sign-of-life counter

Features Not Supported

In general, peripherals or features not mentioned as part of "Features Supported" section are not supported in this release, including the following:

  • Control communication
    • BiSS-C Commands (Control Select bit (CTS) = 0)
    • Following features with Register Communication (Control Select bit (CTS) = 1):
      • Start bit delay
      • Sequential multi-byte access
  • BiSS Line
  • Independent clock frequency for each channel in multi channel mode within the same PRU-ICSS slice
    • Clock frequency is a PRU-ICSS slice level configuration
    • Each channel within the same PRU-ICSS slice in multi-channel mode will have same clock frequencies

SysConfig Features

Note
It is strongly recommend to use SysConfig where it is available instead of using direct SW API calls. This will help simplify the SW application and also catch common mistakes early in the development cycle.
Attention
For each PRU-ICSS slice being used for BiSS-C, one module instance should be created in SysConfig. For up to 3 channels using 1 slice, only 1 instance needs to be added.

SysConfig can be used to configure the following:

  • Selecting the ICSSG instance (Tested on ICSSG0)
  • Selecting the ICSSG PRU slice (Tested on ICSSG0-PRU1)
  • Configuring PINMUX
  • Frequency selection
  • Channel selection
  • Selecting Multi Channel with encoders of different make using load share mode
  • Enabling SA Mux mode
  • Selecting clock source
  • IEP instance and IEP event selection for periodic trigger mode
  • Booster Pack Support: Enable when using BP-AM2BLDCSERVO
    Note
    BiSS-C firmware is tested with ICSS Core Clock running at 200 MHz/300 MHz frequency or ICSS UART Clock running at 192 MHz only. ICSS Core Clock at 225/250/333 MHz is not supported due to clock divider requirements.

Periodic Trigger Modes

The BiSS-C driver supports two types of periodic trigger modes for continuous position sampling:

CMP Mode (Compare Event Mode)

In CMP mode, the IEP timer compare event triggers position sampling. Compare events occur when the IEP timer counter matches the configured compare value. This mode enables fixed-rate periodic sampling.

Configuration:

  • Compare event range: CMP0-CMP15 (0-15)
  • Configured via bissc_config_periodic_trigger_cmp_mode() API
  • IEP compare event number set via bissc_config_iep_cmp_event() API
  • Event selection can be done in SysConfig
  • IEP configuration and CMP event configuration should be done in application. Driver uses above APIs to inform firmware to enable CMP periodic mode and uses the configured CMP event to start sampling periodically.

CAP Mode (Capture Event Mode)

In CAP mode, external signals trigger position sampling through IEP capture events. The capture event is triggered on the rising edge of the external input pulse, enabling event-driven position capture. Internal signals can also be mapped to IEP capture events via TIMESYNC/GPIOMUX router.

Configuration:

  • Capture event range: CAP0-CAP7 (0-7)
  • Configured via bissc_config_periodic_trigger_cap_mode() API
  • IEP capture event number set via bissc_config_iep_cap_event() API
  • Event selection can be done in SysConfig
  • IEP configuration and CAP event configuration should be done in application. Driver uses above APIs to inform firmware to enable CAP periodic mode and uses the configured CAP event to start sampling periodically.
Note
  • External signal must be routed to IEP capture input (if needed) in application
  • CAP6 and CAP7 support falling edge detection as well. In BiSS-C, rising edge is used always.
Attention
Both IEP event configuration APIs (bissc_config_iep_cmp_event() and bissc_config_iep_cap_event()) are automatically called during bissc_init() with values configured in SysConfig.

PRU-ICSS Resource Usage

  • Utilizes the Peripheral IF mode (3-channel peripheral interface mode) for BiSS-C communication. Maximum of 3 channels are available per PRU slice. (Refer Peripheral IF mode for more details)
  • Each channel has 4 pins (Clock, Data out, Data in, Output enable)
    • For BiSS-C, only clock and data pins are needed
    • If RS485 is used, ensure that TX enable is always pulled low
  • Following table contains details of memory usage, IEP usage and interrupt controller usage:
Attention
In addition to the following resources used by PRU firmware, SDK examples also configure IEPx CMP0 for IEP counter reset in periodic trigger CMP mode and IEPx CMP1 for generating SYNC OUT0 used as input to CAP in periodic trigger CAP mode.
Configuration per slice PRU Core(s) Memory Usage IEP Usage Interrupt Controller (INTC) Usage Description
Single channel PRUx DMEM: (0x0 to 0x133) 308 Bytes
IMEM: ~ 3.13 kB 		CMP Mode: IEPx CMPy for trigger (IEPx and CMPy selected in SysConfig)
CAP Mode: IEPx CAPy for trigger (IEPx and CAPy selected in SysConfig) 		INTC event/input number 18 or 21 (prx_pru_mst_intr[2/3]_intr_req) is used to trigger interrupt to Arm® Cortex®-R5F based on slice IEP, CMP/CAP events and INTC signals are used only in periodic trigger modes
Multi-channel with single PRU core PRUx DMEM: (0x0 to 0x133) 308 Bytes
IMEM: ~ 3.43 kB 		CMP Mode: IEPx CMPy for trigger (IEPx and CMPy selected in SysConfig)
CAP Mode: IEPx CAPy for trigger (IEPx and CAPy selected in SysConfig) 		INTC event/input number 18 or 21 (prx_pru_mst_intr[2/3]_intr_req) is used to trigger interrupt to R5F based on slice IEP, CMP/CAP events and INTC signals are used only in periodic trigger modes
Multi-channel with load share across 3 PRU cores PRUx DMEM: (0x0 to 0x133) 308 Bytes
IMEM (per core): ~ 3.74 kB 		CMP Mode: IEPx CMPy for trigger per channel (IEPx and CMPy selected in SysConfig)
CAP Mode: IEPx CAPy for trigger per channel (IEPx and CAPy selected in SysConfig) 		INTC events/inputs number 18, 19, 20 or 21, 22, 23 (prx_pru_mst_intr[2/3/4/5/6/7]_intr_req) are used to trigger interrupts to R5F IEP, CMP/CAP events and INTC signals are used only in periodic trigger modes
RTU_PRUx
TX_PRUx
Note
For pin usage, see Pin Multiplexing section.

BISS-C Design

BISS-C Protocol Design explains the design in detail.

Example

BISS-C Diagnostic

API

APIs for BiSS-C Encoder

Note
Arm is a registered trademark of Arm Limited (or its subsidiaries or affiliates) in the US and/or elsewhere.