Introduction
This example uses the PRUICSS PWM module to generate a signal with a specified duty cycle and deadband at rise edge and fall edge of PWM, syncing PRUICSS PWM with EPWM sync count.
The default parameters in the example are:
- Frequency : 16kHz
- PWM0_0_POS(alias signal PWM0_A0) is configured with duty cycle of 25%, rise edge delay as 0ns and fall edge delay as 0ns
- PWM0_0_NEG(alias signal PWM0_B0) is configured with duty cycle of 25%, rise edge delay as 200ns and fall edge delay as 400ns
- PWM2_0_POS(alias signal PWM2_A0) is configured with duty cycle of 25%, rise edge delay as 0ns and fall edge delay as 0ns
- PWM2_0_NEG(alias signal PWM2_B0) is configured with duty cycle of 25%, rise edge delay as 600ns and fall edge delay as 800ns
All these parameters are configurable.
Code Flow
PRUICSS IEP configuration
- IEP shadow mode and slave mode are enabled (Refer to section 6.4.13 of Technical Reference Manual) and IEP is configured to reset twice on every PWM period as mentioned below.
- EPWM0 sync out is configured to generate every PRUICSS PWM period, PRUICSS IEP COMPARE 0 is configured with one IEP cycle delay ((PWM_PERIOD/2)+1).
- By configuring PRUICSS IEP COMPARE 0 with one IEP cycle delay, IEP COMPARE 0 event is missed at the end of PRUICSS PWM period.
- PRUICSS IEP CMP0 resets IEP counter in middle of PRUICSS PWM period.
- EPWM0 sync out resets IEP counter at end of PRUICSS PWM period.
PRUICSS PWM configuration
- PWM signal is configured to low in Initial state, Toggle in Active state, Change of state from Active to Initial is disabled on IEP0 CMP0 event.
- PWM Duty cycle, rise edge delay, fall edge delay can be configured or updated using PRUICSS_PWM_config API call.
- PWM Period can be configured or updated using PRUICSS_PWM_pruIcssPwmFrequencyInit API call.
- PWM0_0_POS, PWM0_0_NEG, PWM2_0_POS, PWM2_0_NEG uses IEP0 CMP0 and EPWM0 sync out signal to achieve PWM synchronization.
- Individual compare event mapped to PWM_x signals controls duty cycle.
Below two steps are executed once in PWM period
GENERATION OF PRUICSS PWM SIGNAL
- Step1: When EPWM0 sync out resets IEP counter, PWM signals are moved to initial state on software reset, shadow compare register values which decide rise edge are moved to active register values, next compare value which decides fall edge of PWM signal is computed and shadow compare register field is updated.
- Step2: When PRUICSS IEP CMP0 resets IEP counter, shadow compare register values which decide fall edge are moved to active register values, new compare values which decide rise edge of PWM signal are computed from updated duty cycle and shadow compare register field is updated.
The PRUICSS PWM signal generated is similar to EPWM signal when EPWM counter is configured in up-down mode.
Note
This example uses EPWM0 sync out to reset IEP at the PWM period, PRUICSS IEP CMP0 can also be used to do this when EPWM sync out signal is disabled.
LP-AM243
- When LP-AM243 PROC109A revision is used to test this example, SW6 should be in open state to probe PRG0_PWM0_B0 on J2.15, Refer LP-AM243 User Guide Section 4.2.1
- PRG0_PWM0_A0 can be probed on J1.5
- PRG0_PWM0_B0 can be probed on J2.15
- PRG0_PWM2_A0 can be probed on J4.31
- PRG0_PWM2_B0 can be probed on J4.39
- EPWM0_CHANNEL_A can be probed on J4.40
TMDS243EVM
An IO Breakout Board is required to probe the PWM outputs
- PRG0_PWM0_A0 can be probed on J3.1
- PRG0_PWM0_B0 can be probed on J3.3
- PRG0_PWM2_A0 can be probed on J2.5
- PRG0_PWM2_B0 can be probed on J6.9
- EPWM0_CHANNEL_A can be probed on J6.7
Probe Output
PRU-ICSS0 PWM0_A0 and PWM0_B0 DUTY CYCLE and FREQUENCY
PRU-ICSS0 PWM2_A0 and PWM2_B0 DUTY CYCLE and FREQUENCY
PRU-ICSS0 PWM0_A0 and PWM0_B0 DEADBAND and PRU-ICSS0 PWM0_A0 and PWM0_B0 DEADBAND
Supported Combinations
| Parameter | Value |
| CPU + OS | r5fss0-0 freertos |
| r5fss0-0 nortos |
| Toolchain | ti-arm-clang |
| Boards | am243x-evm, am243x-lp |
| Example folder | examples/pruicss_pwm/pruicss_pwm_dead_band_epwm_sync |
Steps to Run the Example
- When using CCS projects to build, import the CCS project for the required combination and build it using the CCS project menu (see Using SDK with CCS Projects ).
- When using makefiles to build, note the required combination and build using make command (see Using SDK with Makefiles )
- Launch a CCS debug session and run the executable, see CCS Launch, Load and Run
- To probe the PRUICSS PWM output please refer to setup details as mentioned above in Introduction section
PRUICSS PWM Deadband Example Debug Guide
No PRUICSS PWM Output
- Verify pin configurations in SysConfig.
- Open
example.syscfg file for correct PWM pin assignments.
- Verify IEP counter is running.
- Check IEP0_GLOBAL_CFG for counter enable.
- Monitor IEP0_COUNT_REG0/1 to verify incrementing.
- Verify PWM active state configuration.
- Using CCS memory browser, check CSL_ICSSCFG_PWM0_0 register.
- Verify CSL_ICSSCFG_PWM0_0_PWM0_0_POS_ACT field = 0 (TOGGLE).
- Check same field for all PWM channels in use.
- Check Compare 0 interrupt service.
- Set breakpoint at Compare 0 ISR function and ensure interrupt is configured correctly.
- Add code to toggle GPIO signal inside ISR function.
- Verify GPIO signal is toggled repeatedly at expected frequency.
- Verify EPWM interrupt service.
- Set breakpoint at EPWM sync ISR function and ensure interrupt is configured correctly.
- Add code to toggle GPIO signal inside ISR function.
- Verify GPIO signal is toggled repeatedly at expected frequency.
- Ensure IEP reset on EPWM sync is enabled.
- Check IEP_PWM_REG register.
- Verify bit 1 (EPWM0_SYNC_EN) = 1 for EPWM0 sync reset.
Incorrect PRUICSS PWM Output
- Verify PWM frequency settings.
- Check
CONFIG_PRUICSS_PWM_INSTANCE0_FREQ_HZ value.
- Measure actual frequency with oscilloscope.
- Check EPWM and PRUICSS PWM frequency match.
- Verify
SOC_EPWM_OUTPUT_FREQ == CONFIG_PRUICSS_PWM_INSTANCE0_FREQ_HZ.
- Examine PWM configuration.
- Add
gPruIcssPwmHandle to watch window.
- Check duty cycle and deadband values.
- Note
- use AM243x Technical Reference Manual to find register address mentioned above
See Also
APIs for PRUICSS PWM
Additional Details
Steps to synchronize PRUICSS PWM from SOC EPWM
This example demonstrates synchronization of PRUICSS PWM with SOC EPWM. For synchronization of SOC EPWM with PRUICSS PWM, follow the steps below:
- Compare 0 event which controls period of PRUICSS PWM is mapped to cmp_event_router_input_16.
- Configure compare event router to mux cmp_event_router_output_40 with cmp_event_router_input_16.
- Select source of SOC EPWM sync input signal as cmp_event_router_output_40.
/* define the unlock and lock values */
#define KICK_LOCK_VAL (0x00000000U)
#define KICK0_UNLOCK_VAL (0x68EF3490U)
#define KICK1_UNLOCK_VAL (0xD172BC5AU)
void unlock_Partition_1_CTRLMMR()
{
/* EPWMCTRL MMR is present at Proxy0 Offset Range 0x4000 t0 0x5FFF
* Refer 5.1.3.1.2 of TRM to find Lock register and its unlock value
* */
volatile uint32_t *kickAddr;
kickAddr = (volatile uint32_t *) (0x43005008);
CSL_REG32_WR(kickAddr, KICK0_UNLOCK_VAL); /* KICK 0 */
kickAddr++;
CSL_REG32_WR(kickAddr, KICK1_UNLOCK_VAL); /* KICK 1 */
}
void lock_Partition_1_CTRLMMR()
{
volatile uint32_t *kickAddr;
kickAddr = (volatile uint32_t *) (0x43005008);
CSL_REG32_WR(kickAddr, KICK_LOCK_VAL); /* KICK 0 */
kickAddr++;
CSL_REG32_WR(kickAddr, KICK_LOCK_VAL); /* KICK 1 */
}
void EPWM_config_syncin_event()
{
unlock_Partition_1_CTRLMMR();
CSL_REG32_WR(CSL_MAIN_CTRL_MMR_CFG0_EPWM0_CTRL+CSL_CTRL_MMR0_CFG0_BASE,0x300);
lock_Partition_1_CTRLMMR();
}
void config_compare_event_router_out()
{
/*Configure compare event router to mux cmp_event_router_output_40 with cmp_event_router_input_16*/
volatile uint32_t *Addr;
uint32_t CMP_EVENT_INTROUTER_MUXCTRL_ADDR_OFFSET = 0x00000004;
uint32_t CMP_EVENT_INTROUTER0_OUTP_40_EPWM0_SYNC_IN_ADDR_OFFSET = 0x28 * 4;
Addr =(uint32_t *)( CSL_CMP_EVENT_INTROUTER0_CFG_BASE + CMP_EVENT_INTROUTER_MUXCTRL_ADDR_OFFSET + CMP_EVENT_INTROUTER0_OUTP_40_EPWM0_SYNC_IN_ADDR_OFFSET);
CSL_REG32_WR(Addr,0x10010);
}
1.8.20