AM243x Motor Control SDK  11.00.00
Position Sense Examples

Table of Contents

This page lists all the examples related to position sense.

  1. EnDAT Diagnostic
  2. HDSL Diagnostic
  3. Tamagawa Diagnostic
  4. EnDAT Diagnostic
  5. HDSL Diagnostic
  6. Tamagawa Diagnostic
  7. BISS-C Diagnostic
  8. NIKON Diagnostic

Encoder Examples Debug Guide

This section provides a debugging guide for troubleshooting issues that may arise during testing or development.

Encoder Register Configuration

The PRU_ICSSG_CFG registers from offset 0xE0 to 0x11C are allocated for encoder configuration. To review and verify the encoder settings:

  1. Halt the Arm® Cortex®-R5F core
  2. Open the memory browser window
  3. Enter the address of the PRU_ICSSG_CFG register and view the configured values

    Note: Ensure you are entering the correct base address for encoder registers. Each ICSS instance has a different address for the CFG register.

For detailed register descriptions, refer to: Section 6.4.14.5 PRU_ICSSG_CFG Registers in the AM243x Technical Reference Manual (TRM)

Key registers and their configurations:

  1. ICSS_PRU0_ED_RX_CFG_REG
    • Division factor for Rx clock
    • RX clock source
    • Polarity of the RX Start Bit
    • RX Over Sample size
  2. ICSS_PRU0_ED_TX_CFG_REG
    • Division factor for Tx clock
    • Load share mode configuration
    • TX clock source
  3. ICSS_PRU0_ED_CH0_CFG0_REG
    • RX frame size
    • TX frame size
    • TX wire delay configuration
  4. ICSS_PRU0_ED_CH0_CFG1_REG
    • Rx arm counter value if Rx auto arm is enabled
    • TST delay
  5. ICSS_GPCFG0_REG
    • Controls the ICSS wrap mux select (should be in EnDAT mode)
  6. ICSSG_SA_MX_REG
    • Use alternative encoder pins
PRU-ICSS 3 channel register view

Hardware Setup and Pin Configuration

The RS485 interface card, control card, and encoder should be connected to the correct PRU GPIO pins mapped for the Encoder interface Peripheral IF mode. All associated pins must be selected in SysConfig.

When using alternative pin options, the 'G_MUX_EN' bit of the 'ICSSG_SA_MX_REG' register must be set.

LP-AM243 Booster Pack Pin Configuration

Pin name Jumper number Function
PRG0_PRU1_GPO0 J2.11 Channel 0 clock
PRG0_PRU1_GPO1 J7.67 Channel 0 transmit
PRG0_PRU1_GPO2 J7.68 Channel 0 transmit enable
PRG0_PRU1_GPI13 J8.71 Channel 0 receive
GPIO1_78 Pin (J8.73) ENC1_EN (J8.73) Enable 3 channel peripheral interface in Axis 1 of BP (C16 GPIO pin)
PRG0_PRU1_GPO6 J7.69 Channel 2 clock
PRG0_PRU1_GPO12 J8.72 Channel 2 transmit
PRG0_PRU1_GPO8 J6.57 Channel 2 transmit enable
PRG0_PRU1_GPI11 J7.70 Channel 2 receive
GPIO1_77 Pin (J8.74) ENC2_EN Enable 3 channel peripheral interface in Axis 2 of BP (B17 GPIO pin)

PRU Firmware Debug

For PRU-related issues, verify that the application is loading the PRU firmware into the correct PRU core. If firmware loading fails:

  1. Check the PRU core selection
  2. Verify the PRU slice selection
  3. Review application-level configuration

Debugging Steps for PRU Core with Loaded Firmware:

  1. Import the PRU firmware for the target core
  2. Build the firmware
  3. Open the debug window and connect to the PRU core
  4. Load symbols into the connected core:
    • Click the Load button
    • Select Load Symbols
    • Load the firmware .out file from the firmware project
  5. After symbols are loaded, use the step-into button to execute debug commands
Load EnDAT RTU firmware symbols

Multi-channel modes

Multi-channel with single PRU mode

Note
This subsection is applicable for BiSS-C, EnDat, Nikon A-format, and Tamagawa only.
  • In this mode, data transmission and reception must happen simultaneously on all channels.
  • The encoder configuration and cable length should be the same on all channels.
  • If encoders across channels don't respond at the same time, this mode will not work. Load share configuration should be used instead.

Multi-channel with load share mode

Note
This subsection is applicable for BiSS-C, EnDat, HDSL, and Nikon A-format only.
  • In this mode, data transmission and reception can happen independently on all channels.
  • After a command is sent, all channels wait for a response and process the response independently. However, all channels must finish processing before the next command can be triggered. (This restriction does not apply to HDSL. HDSL channels can continue operating independently.)

Periodic Continuous Mode

Note
This subsection is applicable for BiSS-C, EnDat, Nikon A-format and Tamagawa only. Load share mode is not available for Tamagawa.

SDK examples uses IEP CMP event to trigger periodic mode. CMP0 is used to get periodic CMP events by resetting the IEP counter continuously. Firmware triggers a R5F interrupt after getting a response from the encoder. The application code uses a callback function to clear the PRU interrupt, which can be modified as per the use case. CMP3 is used for single channel and single PRU multi-channel mode. For multi-channel load share mode, CMP3 is used for RTU core, CMP5 is used for PRU core and CMP6 is used for TX PRU core channel. Refer the example specific page for details on how to modify the compare events.

When programming the values for CMP based trigger events, ensure that the command send and receive can complete within the cycle time (configured with CMP0). In multi-channel, ensure that command completion for timings for all channels are considered. Incorrect values may send PRU FW in bad state. Also, refer to encoder specifications to ensure that requirement for mimimum interval between two commands is met.

IEP Registers Configuration

The Industrial Ethernet Peripheral (IEP) is used for periodic continuous mode. If the IEP is not configured correctly, periodic continuous mode will not work.

To verify IEP configuration:

  1. Check if the IEP is running by examining IEP_COUNT_REG0/1 registers
  2. Verify counter increment by monitoring count values
  3. Review IEP_CMP_CFG_REG to ensure all compare events are properly configured for trigger mode
  4. Check IEP_CMP_STATUS_REG to verify that corresponding compare events are setting status flags correctly
  5. Validate that Compare Registers are configured with correct trigger point values

Note: Ensure you are entering the correct address for IEP registers. Each ICSS instance has a different base address for the IEP registers.

PRU-ICSS IEP register view
PRU-ICSS IEP CMP events register view

For detailed register descriptions, refer to: Section 6.4.14.9 PRU_IEP_IEP Registers in the AM243x TRM

Interrupt Controller Internal Signals Mapping

If you experience missing PRU interrupts or incorrect IRQ mapping, verify the interrupt mapping between PRU and R5F in the SysConfig PRU INTC module. The Host channel number and PRU Event should match your configuration.

For example, the EnDAT example uses:

  • PRU Event: 18: pr0_pru_mst_intr[2]_intr_req
  • Host Channel: 2
PRU-ICSS INTC view

The interrupt service routine (ISR) configuration is implemented in endat_periodic_trigger.c. Here's a key code snippet showing the configuration:

/* R5F interrupt settings for ICSSG */
#define ICSS_PRU_ENDAT_INT_NUM ( CSLR_R5FSS0_CORE0_INTR_PRU_ICSSG0_PR1_HOST_INTR_PEND_0 )
/* Register & enable ICSSG EnDat PRU FW interrupt */
HwiP_Params_init(&hwiPrms);
hwiPrms.intNum = ICSS_PRU_ENDAT_INT_NUM;
hwiPrms.callback = &pruEnDatIrqHandler;
hwiPrms.args = 0;
hwiPrms.isPulse = FALSE;
hwiPrms.isFIQ = FALSE;
status = HwiP_construct(&gIcssgEncoderHwiObject0, &hwiPrms);
DebugP_assert(status == SystemP_SUCCESS);
/* PRU EnDat FW IRQ handler */
void pruEnDatIrqHandler(void *args)
{
/* Increment PRU ENDAT IRQ count */
gPruEnDatIrqCnt0++;
/* Clear interrupt at source */
PRUICSS_clearEvent(gPruIcssXHandle, PRU_TRIGGER_HOST_ENDAT_EVT0);
}

The PRU event number is defined in endat_periodic_trigger.h:

#define PRU_TRIGGER_HOST_ENDAT_EVT0 ( 2+16 )
Note
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