tiescbsp.h

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/*
 *  Copyright (C) 2021 Texas Instruments Incorporated
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef TIESC_BSP_H_
#define TIESC_BSP_H_
 
/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */
 
#ifndef DISABLE_UART_PRINT
#include <stdio.h>
#endif
 
#include <industrial_comms/ethercat_slave/icss_fwhal/tiesc_pruss_intc_mapping.h>
#include <drivers/pruicss.h>
#include <industrial_comms/ethercat_slave/icss_fwhal/tiesc_def.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
/* ========================================================================== */
/*                           Macros & Typedefs                                */
/* ========================================================================== */
 
 
#define TIESC_MAX_FRAME_SIZE    (0x7CF)
 
/*Single datagram accessing contiguous multiple FMMU mapped areas in  a single slave for process data
is supported now by TI ESC firmware.
Process path latency in TI ESC is high when this support is active
For specific use cases (4SM with 3 FMMUs or multiple FMMUs (in a given ESC) are not accessed in a single datagram)
process path latency improvement can be achieved by disabling below define */
#define ENABLE_MULTIPLE_SM_ACCESS_IN_SINGLE_DATAGRAM     0
 
#define    MAX_SYNC_MAN                         8
#define    SIZEOF_SM_REGISTER                   8
 
#define TIESC_EEPROM_SIZE         0x800
 
#define    MAILBOX_WRITE                        0
#define    MAILBOX_READ                         1
#define    PROCESS_DATA_OUT                     2
#define    PROCESS_DATA_IN                      3
 
#define     MBX_WRITE_EVENT                 ((uint16_t) 0x0100)
#define     MBX_READ_EVENT                  ((uint16_t) 0x0200)
 
//Below constants are not defined in esc.h
#define ESC_ADDR_REV_TYPE       0x000
#define ESC_ADDR_BUILD          0x002
 
#define ESC_ADDR_CONFIG_STATION_ALIAS   0x012
#define ESC_ADDR_DLSTATUS       0x110
#define ESC_ADDR_ALCONTROL      0x120
#define ESC_ADDR_ALSTATUS       0x130
#define ESC_ADDR_PDI_CONTROL    0x140
#define ESC_PDI_CONTROL_ELD_ALL_PORTS_MASK (1 << 1)
#define ESC_ADDR_PDI_CONFIG     0x150
#define ESC_ADDR_AL_EVENT_MASK  0x204
#define ESC_ADDR_AL_EVENT_REQ   0x220
#define ESC_ADDR_SM_WD_STATUS   0x440
#define ESC_ADDR_EEPROM_CTRL    0x502
#define ESC_ADDR_MI_ECAT_ACCESS 0x516
#define ESC_ADDR_MI_PDI_ACCESS  0x517
 
#define ESC_EEPROM_CMD_MASK                     0x0700 //Description (0x502.8:10): Command bit mask
#define ESC_EEPROM_CMD_READ_MASK                0x0100 //Description (0x502.8): Currently executed read command
#define ESC_EEPROM_CMD_WRITE_MASK               0x0200 //Description (0x502.9): Initialize Write Command
#define ESC_EEPROM_CMD_RELOAD_MASK              0x0400 //Description (0x502.10): Trigger EEPROM reload
#define ESC_EEPROM_ERROR_MASK                   0x7800 //Description : Mask all EEPROM error bits; Checksum error (0x0502.11); EEPROM not loaded (0x0502.12); Missing EEPROM Acknowledge (0x0502.13); Write Error (0x0502.14)
#define ESC_EEPROM_ERROR_CRC                    0x0800 //Description (0x502.11): EEPROM CRC Error
#define ESC_EEPROM_ERROR_CMD_ACK                0x2000 //Description (0x502.13): EEPROM Busy
#define ESC_EEPROM_BUSY_MASK                    0x8000  //Description (0x502.15): EEPROM Busy
 
#define ESC_ADDR_SYNCMAN 0x800
 
#define ESC_ADDR_SM1_STATUS 0x80D
#define SM_STATUS_MBX_FULL  0x08
 
#define ESC_ADDR_SM0_STATUS     0x805
#define ESC_ADDR_SM0_ACTIVATE   0x806
#define ESC_ADDR_SM1_ACTIVATE   0x806+8
#define ESC_ADDR_SM2_ACTIVATE   0x806+8*2
#define ESC_ADDR_SM3_ACTIVATE   0x806+8*3
#define ESC_ADDR_SM4_ACTIVATE   0x806+8*4
#define ESC_ADDR_SM5_ACTIVATE   0x806+8*5
#define ESC_ADDR_SM6_ACTIVATE   0x806+8*6
#define ESC_ADDR_SM7_ACTIVATE   0x806+8*7
#define ESC_ADDR_SM0_PDI_CONTROL    0x807
#define ESC_ADDR_SM1_PDI_CONTROL    0x807+8
#define ESC_ADDR_SM2_PDI_CONTROL    0x807+8*2
#define ESC_ADDR_SM3_PDI_CONTROL    0x807+8*3
#define ESC_ADDR_SM4_PDI_CONTROL    0x807+8*4
#define ESC_ADDR_SM5_PDI_CONTROL    0x807+8*5
#define ESC_ADDR_SM6_PDI_CONTROL    0x807+8*6
#define ESC_ADDR_SM7_PDI_CONTROL    0x807+8*7
 
#define SM_PDI_CONTROL_SM_DISABLE      1
 
#define ESC_ADDR_SYSTIME            0x910
#define ESC_ADDR_SYSTIME_HIGH       0x914
#define ESC_ADDR_SYSTIME_OFFSET     0x920
#define ESC_ADDR_SYSTIME_DELAY      0x928
#define ESC_ADDR_SPEEDCOUNTER_START 0x930
#define ESC_ADDR_TIMEDIFF_FILTDEPTH 0x934
#define ESC_ADDR_SPEEDDIFF_FILTDEPTH 0x935
#define ESC_ADDR_SYNC_PULSE_LENGTH  0x982
#define ESC_ADDR_SYNC_STATUS        0x98E
#define ESC_ADDR_LATCH0_CONTROL     0x9A8
#define ESC_ADDR_LATCH1_CONTROL     0x9A9
#define ESC_ADDR_LATCH0_POS_EDGE    0x9B0
#define ESC_ADDR_LATCH0_NEG_EDGE    0x9B8
#define ESC_ADDR_LATCH1_POS_EDGE    0x9C0
#define ESC_ADDR_LATCH1_NEG_EDGE    0x9C8
#define ESC_ADDR_TI_PORT0_ACTIVITY  0xE00
#define ESC_ADDR_TI_PORT1_ACTIVITY  0xE04
#define ESC_ADDR_TI_PORT0_PHYADDR   0xE08
#define ESC_ADDR_TI_PORT1_PHYADDR   0xE09
#define ESC_ADDR_TI_PDI_ISR_PINSEL  0xE0A
#define ESC_ADDR_TI_PHY_LINK_POLARITY   0XE0C
#define ESC_ADDR_TI_PORT0_TX_START_DELAY    0xE10
#define ESC_ADDR_TI_PORT1_TX_START_DELAY    0xE12
#define ESC_ADDR_TI_ESC_RESET       0xE14
#define ESC_ADDR_TI_EDMA_LATENCY_ENHANCEMENT    0xE24
#define ESC_ADDR_TI_PHY_RX_ER_REG               0xE28
#define ESC_ADDR_TI_PRU_CLK_FREQUENCY           0xE34
#define ESC_ADDR_TI_MDIO_MANUAL_MODE            0xE35
#define ESC_ADDR_TI_ENHANCED_LINK_DETECT        0xE36
#define TI_ESC_RST_CMD_U    0x545352
#define TI_ESC_RST_CMD_L    0x747372
 
#define ESC_ADDR_MEMORY         0x1000
 
#define CMD_DL_USER_CLEAR_AL_EVENT_HIGH     0x0
#define CMD_DL_USER_GET_BUFFER_READ_ADDR    0x1
#define CMD_DL_USER_GET_BUFFER_WRITE_ADDR   0x2
#define CMD_DL_USER_SET_BUFFER_WRITE_DONE   0x3
 
#define CMD_DL_USER_ACK_MBX_READ            0x4
 
#define CMD_DL_USER_ACK_MBX_WRITE           0x5
 
#define CMD_DL_USER_EEPROM_CMD_ACK          0x6
 
#define CMD_DL_USER_READ_SYNC_STATUS        0x7
#define SYNC0   0
#define SYNC1   1
 
#define CMD_DL_USER_READ_AL_CONTROL         0x8
 
#define CMD_DL_USER_WRITE_AL_STATUS         0x9
 
#define CMD_DL_USER_READ_PD_WD_STATUS       0xA
 
#define CMD_DL_USER_READ_SM_ACTIVATE        0xB
 
#define CMD_DL_USER_WRITE_SM_PDI_CTRL       0xC
 
#define CMD_DL_USER_READ_LATCH_TIME         0xD
#define LATCH0_POS_EDGE 0
#define LATCH0_NEG_EDGE 1
#define LATCH1_POS_EDGE 2
#define LATCH1_NEG_EDGE 3
 
#define CMD_DL_USER_READ_SYS_TIME           0xE
 
#define CMD_DL_USER_CLEAR_AL_EVENT_LOW      0xF
#ifdef SYSTEM_TIME_PDI_CONTROLLED
 
#define CMD_DL_USER_SYSTIME_PDI_CONTROL    0x10
#define WRITE_SYSTIME              0
#define WRITE_SYSTIME_OFFSET       1
#define WRITE_FILTER_CONFIG        2
#endif
 
#define SWAPWORD
#define SWAPDWORD
 
#define ICSS_MDIO_USRPHYSEL_LINKINT_ENABLE 0x40
#define ICSS_MDIO_USRPHYSEL_LINKSTAT_MLINK 0x80
 
#define TIESC_PERM_RW       0x0
#define TIESC_PERM_WRITE_ONLY 0x1
#define TIESC_PERM_READ_ONLY 0x2
 
#define TIESC_PERM_WRITE TIESC_PERM_WRITE_ONLY
#define TIESC_PERM_READ TIESC_PERM_READ_ONLY
 
#define PDI_PERM_RW        0x0
#define PDI_PERM_READ_ONLY 0x1
 
#define PDI_PERM_WRITE PDI_PERM_RW
#define PDI_PERM_READ PDI_PERM_READ_ONLY
 
#define TIESC_MDIO_CLKDIV   79 //For 2.5MHz MDIO clock: 200/(TIESC_MDIO_CLKDIV+1)
 
/* For EtherCAT, Fast link detection using MLINK mode is required to support complete functionality */
#define TIESC_MDIO_RX_LINK_DISABLE  0 //Slow MDIO state m/c based link detection
#define TIESC_MDIO_RX_LINK_ENABLE   1 //Fast link detect using RXLINK forward from PHY to MDIO MLINK
#define TIESC_LINK_POL_ACTIVE_LOW       1
#define TIESC_LINK_POL_ACTIVE_HIGH      0
 
#define PDI_WD_TRIGGER_RX_SOF       (0 << 4)
 
#define PDI_WD_TRIGGER_LATCH_IN     (1 << 4)
 
#define PDI_WD_TRIGGER_SYNC0_OUT    (2 << 4)
 
#define PDI_WD_TRIGGER_SYNC1_OUT    (3 << 4)
 
#if ENABLE_MULTIPLE_SM_ACCESS_IN_SINGLE_DATAGRAM
#define TIESC_PORT0_TX_DELAY_200_MHZ_CLOCK    0x98
#else
#define TIESC_PORT0_TX_DELAY_200_MHZ_CLOCK    0x48
#endif
#define TIESC_PORT1_TX_DELAY_200_MHZ_CLOCK    TIESC_PORT0_TX_DELAY_200_MHZ_CLOCK
 
#if ENABLE_MULTIPLE_SM_ACCESS_IN_SINGLE_DATAGRAM
#define TIESC_PORT0_TX_DELAY_333_MHZ_CLOCK    0xA0
#else
#define TIESC_PORT0_TX_DELAY_333_MHZ_CLOCK    0x50
#endif
#define TIESC_PORT1_TX_DELAY_333_MHZ_CLOCK    TIESC_PORT0_TX_DELAY_333_MHZ_CLOCK
 
#define PDI_ISR_EDIO_NUM    7 //GPMC_CSN(2) -> pr1_edio_data_out7 for ICEv2.J4.Pin21
 
/* PDI  side register protection using register permission table (4KB) in memory - disable if you care for performance and memory foot print */
/* #define ENABLE_PDI_REG_PERMISSIONS */
 
/* Use ESC system time instead of SYS/BIOS Timestamp_get32 for timing info */
#define USE_ECAT_TIMER
 
 
/* Uncomment following to enable DC feature of system time compensation via PDI interface instead of ECAT interface
   for synchronizing two independent EtherCAT networks */
//#define SYSTEM_TIME_PDI_CONTROLLED
/*Comment to following to enable PDI  ISR and SYNC ISR in HWI context */
#define  ENABLE_PDI_TASK
#define  ENABLE_SYNC_TASK
 
/* #define  SUPPORT_CMDACK_POLL_MODE */
 
#if defined (__aarch64__)
#define ASSERT_DMB()  __asm__("    dmb ISH")
#define ASSERT_DSB()  __asm__("    dsb ISH")
#else
#define ASSERT_DMB() __asm__ __volatile__ ("    dmb" "\n\t": : : "memory")
#define ASSERT_DSB() __asm__ __volatile__ ("    dsb" "\n\t": : : "memory")
#endif
 
#ifdef USE_ECAT_TIMER
#define ECAT_TIMER_INC_P_MS 1000000
#else
#define ECAT_TIMER_INC_P_MS ecat_timer_inc_p_ms /* ARM frequency: Will be detected during bsp_init*/
extern volatile uint32_t ecat_timer_inc_p_ms;
#endif
 
#define ESC_SYSTEMTIME_OFFSET_OFFSET        0x0920
#define ESC_SPEED_COUNTER_START_OFFSET      0x0930
#define ESC_DC_START_TIME_CYCLIC_OFFSET     0x0990
 
#define DRIFTCTRL_TASK_SYNC_ZERO_CROSS_ADJUST   0xE0 //PRU_DMEM0
 
#define LOCK_PD_BUF_AVAILABLE_FOR_HOST  0
 
#define LOCK_PD_BUF_HOST_ACCESS_START   1
 
#define LOCK_PD_BUF_HOST_ACCESS_FINISH  2
 
#define LOCK_PD_BUF_CHECK_AVAILABILITY_RETRY_COUNT    (10U)
 
#define TIESC_PRUICSS_CLOCK_FREQUENCY_200_MHZ (0)
 
#define TIESC_PRUICSS_CLOCK_FREQUENCY_333_MHZ (1)
 
#define TIESC_MDIO_HW_MODE                    (0)
 
#define TIESC_MDIO_MANUAL_MODE_FW             (1)
 
typedef int32_t (*bsp_eeprom_read_t)(uint8_t *buf, uint32_t len);
typedef int32_t (*bsp_eeprom_write_t)(uint8_t *buf, uint32_t len);
typedef void (*bsp_init_spinlock_t)(void);
typedef uint32_t (*bsp_hwspinlock_lock_t)(int num);
typedef void (*bsp_hwspinlock_unlock_t)(int num);
typedef void (*bsp_ethphy_init_t)(PRUICSS_Handle pruIcssHandle, uint8_t phy0addr, uint8_t phy1addr, uint8_t enhancedlink_enable);
typedef int8_t (*bsp_get_phy_address_t)(uint8_t instance, uint8_t portNumber);
typedef void (*bsp_ethercat_stack_isr_function)(void);
 
/* ========================================================================== */
/*                         Structure Declarations                             */
/* ========================================================================== */
 
typedef struct bsp_params_s
{
    PRUICSS_Handle                      pruicss_handle;
    int32_t                             interrupt_offset;
    bsp_eeprom_read_t                   eeprom_read;
    bsp_eeprom_write_t                  eeprom_write;
    uint32_t                            spinlock_base_address;
    bsp_ethphy_init_t                   ethphy_init;
    uint8_t                             enhancedlink_enable;
    uint32_t                            link0_polarity;
    uint32_t                            link1_polarity;
    uint32_t                            phy0_address;
    uint32_t                            phy1_address;
    const unsigned char                 *default_tiesc_eeprom;
    uint8_t                             **eeprom_pointer_for_stack;
    bsp_ethercat_stack_isr_function     pdi_isr;
    bsp_ethercat_stack_isr_function     sync0_isr;
    bsp_ethercat_stack_isr_function     sync1_isr;
    uint16_t                            phy_rx_err_reg;
    uint8_t                             pruicssClkFreq;
    uint8_t                             mdioManualMode;
} bsp_params;
 
typedef struct
{
    uint8_t sm_buf_index;     
    uint8_t lock_state;       
    uint16_t addr;            
} t_sm_processdata;
 
typedef struct
{
    uint8_t reserved1[0x90];          
    uint32_t system_time_low;         
    uint32_t system_time_high;        
    uint8_t sm_config_ongoing;        
    uint8_t reserved2[7];             
    uint16_t cmdlow;                  
    uint16_t cmdlow_ack;              
    uint16_t param1low;               
    uint16_t param2low;               
    uint16_t resp1low;                
    uint16_t resp2low;                
#ifndef SYSTEM_TIME_PDI_CONTROLLED
    uint8_t reserved3[212];           
#else
    uint8_t reserved3[24];            
    uint32_t systime_offset_low;      
    uint32_t systime_offset_high;     
    uint8_t reserved4[180];           
#endif
    t_sm_processdata sm_processdata[6]; 
} t_host_interface;
 
typedef struct
{
    uint8_t reserved[1024];       
    uint8_t reg_properties[4096]; 
} t_register_properties;
 
typedef struct
{
    uint16_t physical_start_addr;
    uint16_t length;
} t_sm_properties;
 
typedef struct
{
    uint16_t clkdiv;      
    uint8_t addr0;        
    uint8_t addr1;        
    uint8_t link0pol; /* LINK_MII signal polarity of PHY hooked to PRU-ICSS MII0. 1: Active lLow 0: Active High */
    uint8_t link1pol; /* LINK_MII signal polarity of PHY hooked to PRU-ICSS MII1. 1: Active lLow 0: Active High */
    uint8_t enhancedlink_enable;  
} t_mdio_params;
 
/* ========================================================================== */
/*                       Function Declarations                                */
/* ========================================================================== */
 
void bsp_params_init(bsp_params *init_params);
 
extern int32_t bsp_init(bsp_params *init_params);
 
extern void bsp_esc_reg_perm_init(PRUICSS_Handle
                                 pruIcssHandle);  //Internal API - invoked by bsp_init
 
extern void bsp_start_esc_isr(PRUICSS_Handle pruIcssHandle);
 
extern void bsp_exit(PRUICSS_Handle pruIcssHandle);
 
extern void bsp_set_pdi_wd_trigger_mode(PRUICSS_Handle pruIcssHandle,
                                       uint32_t mode);
extern void bsp_send_command_to_firmware(PRUICSS_Handle pruIcssHandle,
                                        uint32_t command, uint16_t param1, uint16_t param2);
extern void bsp_eeprom_emulation_init(void);
 
extern int32_t bsp_eeprom_load_esc_registers(PRUICSS_Handle pruIcssHandle,
        int32_t reload_flag);
 
extern int32_t bsp_eeprom_emulation_reload(PRUICSS_Handle pruIcssHandle);
 
extern void bsp_eeprom_emulation_command_ack(PRUICSS_Handle pruIcssHandle);
 
extern void bsp_eeprom_emulation_flush(void);
 
extern void bsp_eeprom_emulation_exit(void);
 
extern uint8_t *bsp_get_eeprom_cache_base(void);
 
void bsp_set_eeprom_updated_time(void);
 
uint32_t bsp_get_eeprom_updated_time(void);
 
extern void bsp_set_eeprom_update_status(uint8_t status);
 
extern uint8_t bsp_get_eeprom_update_status(void);
 
extern void bsp_set_sm_properties(PRUICSS_Handle pruIcssHandle, uint8_t sm,
                                 uint16_t address, uint16_t len);
extern t_sm_properties *bsp_get_sm_properties(uint8_t sm);
 
extern int16_t bsp_get_sm_index(uint16_t address, uint16_t len);
extern uint8_t bsp_pdi_sm_config_ongoing(PRUICSS_Handle pruIcssHandle);
extern void bsp_pdi_mbx_read_start(PRUICSS_Handle pruIcssHandle);
 
extern void bsp_pdi_mbx_read_complete(PRUICSS_Handle pruIcssHandle);
 
extern void bsp_pdi_mbx_write_start(PRUICSS_Handle pruIcssHandle);
 
extern void bsp_pdi_mbx_write_complete(PRUICSS_Handle pruIcssHandle);
 
extern uint16_t bsp_get_process_data_address(PRUICSS_Handle pruIcssHandle,
        uint16_t address, uint16_t len, int16_t *p_sm_index);
 
extern void bsp_process_data_access_complete(PRUICSS_Handle pruIcssHandle,
        uint16_t address, uint16_t len, int16_t sm_index);
 
extern uint8_t bsp_read_byte(PRUICSS_Handle pruIcssHandle, uint16_t address);
 
extern uint16_t bsp_read_word(PRUICSS_Handle pruIcssHandle, uint16_t address);
 
extern uint32_t bsp_read_dword(PRUICSS_Handle pruIcssHandle, uint16_t address);
 
extern void bsp_read(PRUICSS_Handle pruIcssHandle, uint8_t *pdata,
                    uint16_t address,
                    uint16_t len);
 
extern uint8_t bsp_read_byte_isr(PRUICSS_Handle pruIcssHandle, uint16_t address);
 
extern uint16_t bsp_read_word_isr(PRUICSS_Handle pruIcssHandle,
                                 uint16_t address);
 
extern uint32_t bsp_read_dword_isr(PRUICSS_Handle pruIcssHandle,
                                  uint16_t address);
 
extern void bsp_pdi_post_read_indication(PRUICSS_Handle pruIcssHandle,
                                        uint16_t address, uint16_t length);
extern void bsp_pdi_write_indication(PRUICSS_Handle pruIcssHandle,
                                    uint16_t address, uint16_t length,
                                    uint16_t value);
extern void bsp_write_byte(PRUICSS_Handle pruIcssHandle, uint8_t val,
                          uint16_t address);
 
extern void bsp_write_word(PRUICSS_Handle pruIcssHandle, uint16_t val,
                          uint16_t address);
 
extern void bsp_write_dword(PRUICSS_Handle pruIcssHandle, uint32_t val,
                           uint16_t address);
 
extern void bsp_write(PRUICSS_Handle pruIcssHandle, uint8_t *pdata,
                     uint16_t address, uint16_t len);
 
extern uint32_t bsp_pruss_mdioreg_read(PRUICSS_Handle pruIcssHandle,
                                      uint32_t regoffset);
 
extern void bsp_pruss_mdioreg_write(PRUICSS_Handle pruIcssHandle, uint32_t val,
                                   uint32_t regoffset);
 
extern uint32_t bsp_pruss_iepreg_read(PRUICSS_Handle pruIcssHandle,
                                     uint32_t regoffset);
 
extern void bsp_pruss_iepreg_write(PRUICSS_Handle pruIcssHandle, uint32_t val,
                                  uint32_t regoffset);
 
extern void bsp_pruss_cmd_intfc_write_word(uint16_t val, volatile uint16_t *ptr);
 
extern uint16_t bsp_pruss_cmd_intfc_read_word(volatile uint16_t *ptr);
 
extern uint8_t  bsp_get_pdi_access_perm(uint16_t address, uint8_t access);
 
extern uint8_t  bsp_pdi_access_perm_word(uint16_t address, uint8_t access);
 
extern uint8_t  bsp_pdi_access_perm_dword(uint16_t address, uint8_t access);
 
extern uint8_t  bsp_pdi_access_perm_array(uint16_t address, uint8_t access,
        uint16_t size);
 
extern void bsp_set_pdi_perm_read_only(uint16_t *perm_array, uint16_t address);
 
extern void bsp_set_pdi_perm_read_write(uint16_t *perm_array, uint16_t address);
 
extern uint8_t bsp_is_pdi_perm_read_only(uint16_t *perm_array, uint16_t address);
 
extern uint32_t bsp_get_pdi_read_access_fail_cnt();
 
extern uint32_t bsp_get_pdi_write_access_fail_cnt();
 
extern int16_t bsp_pruss_mdio_init(PRUICSS_Handle pruIcssHandle,
                                  t_mdio_params *pmdio_params);
 
extern int16_t bsp_pruss_mdio_phy_read(PRUICSS_Handle pruIcssHandle,
                                      uint8_t phyaddr, uint8_t regoffset, uint16_t *regval);
 
extern int16_t bsp_pruss_mdio_phy_write(PRUICSS_Handle pruIcssHandle,
                                       uint8_t phyaddr, uint8_t regoffset, uint16_t regval);
 
extern uint32_t bsp_pruss_mdio_phy_link_state(PRUICSS_Handle pruIcssHandle,
        uint8_t phyaddr);
extern  void bsp_set_digio_sw_dataout_enable(PRUICSS_Handle pruIcssHandle);
 
extern void bsp_set_digio_out(PRUICSS_Handle pruIcssHandle, uint8_t num);
 
extern void bsp_clear_digio_out(PRUICSS_Handle pruIcssHandle, uint8_t num);
 
extern void bsp_hwspinlock_init(void);
 
extern uint32_t bsp_hwspinlock_lock(int num);
 
extern void bsp_hwspinlock_unlock(int num);
 
#ifdef SYSTEM_TIME_PDI_CONTROLLED
 
extern void bsp_pdi_latch0_control(PRUICSS_Handle pruIcssHandle, uint8_t val);
 
extern void bsp_pdi_latch1_control(PRUICSS_Handle pruIcssHandle, uint8_t val);
 
extern void bsp_pdi_write_system_time(PRUICSS_Handle pruIcssHandle,
                                     uint32_t systime);
extern void bsp_pdi_write_system_timeoffset(PRUICSS_Handle pruIcssHandle,
        unsigned long long systime);
extern void bsp_pdi_write_systime_delay(PRUICSS_Handle pruIcssHandle,
                                       uint32_t systime);
extern void bsp_pdi_write_filterconfig(PRUICSS_Handle pruIcssHandle,
                                      uint16_t speedcount_start,
                                      uint8_t speedcount_filtdepth, uint8_t systime_filtdepth);
#endif
 
extern uint32_t bsp_get_timer_register(void);
 
extern void bsp_clear_timer_register(void);
extern void bsp_get_local_sys_time(uint32_t *systime_low,
                                  uint32_t *systime_high);
 
extern void bsp_get_latch0_posedge_time(PRUICSS_Handle pruIcssHandle,
                                       uint32_t *systime_low, uint32_t *systime_high);
 
extern void bsp_get_latch0_negedge_time(PRUICSS_Handle pruIcssHandle,
                                       uint32_t *systime_low, uint32_t *systime_high);
 
extern void bsp_get_latch1_posedge_time(PRUICSS_Handle pruIcssHandle,
                                       uint32_t *systime_low, uint32_t *systime_high);
 
extern void bsp_get_latch1_negedge_time(PRUICSS_Handle pruIcssHandle,
                                       uint32_t *systime_low, uint32_t *systime_high);
 
extern void bsp_global_mutex_lock(void);
 
extern void bsp_global_mutex_unlock(void);
void Sync0Isr(void *args);
void Sync1Isr(void *args);
void EcatIsr(void *args);
 
#ifndef SUPPORT_CMDACK_POLL_MODE
 
void EscCmdLowAckIsr(void *args);
#endif
 
extern void bsp_set_pru_firmware(uint32_t *frameProc, uint32_t frameProcLen,
                                uint32_t *hostProc, uint32_t hostProcLen);
#ifdef __cplusplus
}
#endif
 
#endif/*TIESC_BSP_H_ */