• 0 = Normal protocol action
• 1 = A forced reset of the protocol status will be initiated. If the bit is deleted, a restart of the connection is triggered.

• 0 = Normal Parameters Channel action
• 1 = The Parameters Channel is reset. Current short and long messages are discarded.

• 0 = Position sampling during free running at the shortest cycle time.
• All other values = Position sampling with the sync signal synchronized. The value from ES determines the number of position samplings carried out in one sync cycle.

• 0 = No connection present or connection error due to a communications error.
• 1 = Protocol connection between DSL Master and Slave was established.

• Quality monitoring is initiated with the value "8".
• The maximum quality monitoring value is "15". This is the standard value during operation.
• Higher values indicate a better connection.

• It contains the messaging bits for warning and error modes of the DSL system.
• All messaging bits are set by the DSL Master if a corresponding status is determined.
• An event bit that has been set is not reset by the DSL Master.
• It should be noted that all event register bits are also transferred to ONLINE_STATUS_D register. The event bits are not static there and contain the actual status of each individual event.

SUM: Remote event monitoring

• 0 = All DSL Slave events are deleted.
• 1 = The DSL Slave has signaled an event and the summary mask is set accordingly (see registers MASK_SUM and SUMMARY).

When the SUM bit is set, an error or a warning has been transmitted from the DSL Slave. The application must check the SUMMARY register to obtain a detailed description.

• 0 = The data for the fast position was correctly transmitted.
• 1 = Fast position data consistency error. The fast position read through drive interface is supplied by the estimator. This error usually indicates a transmission error on the DSL connection. If this error occurs frequently, the wiring of the DSL connection should be checked. If this error occurs continuously, there is probably an error in the motor feedback system.

• 0 = Current value of deviation smaller than the specified maximum.
• 1 = Current value of deviation greater than the specified maximum.
  NOTE : Not available in TI HDSL Solution.

• 0 = Normal protocol action
• 1 = The forced protocol reset was triggered.

• It contains the messaging bits for warning and error modes of the DSL system.
• All messaging bits are set by the DSL Master if a corresponding status is determined.
• An event bit that has been set is not reset by the DSL Master.
• It should be noted that all event register bits are also transferred to ONLINE_STATUS_D register. The event bits are not static there and contain the actual status of each individual event.

MIN: Message initialization

• 0 = No acknowledgment for the initialization received.
• 1 = An acknowledgment was received from the Slave for the initialization of a message.

When this warning is displayed, the Parameters Channel is still in the initialization status and no "short message" or "long message" can be triggered.

ANS: Erroneous answer to "long message"

• 0 = The last answers to "long messages" were error free.
• 1 = An error occurred during the answer to a long message. The effectiveness of the previous transaction is not known.

This error indicates that the transmission of an answer from the DSL Slave to the last "long message" failed. The application must send the "long message" again.

• 0 = Quality monitoring value greater than or equal to "14"
• 1 = Quality monitoring value (see register 03h) below "14"

FREL: Channel free for "long message"

• 1 = A "long message" can be sent on the Parameters Channel.
• 0 = No "long message" can be sent.

If the bit is set, the application can trigger a "long message". Provided no answer has been received from the DSL Slave, this bit remains deleted. As the processing duration of a "long message" in the motor feedback system is not specified, a user time limit condition should be installed via the application. When a time limit is exceeded, the MRST bit in the SYS_CTRL register is set, which causes the Parameters Channel to be reset.

• In the event mask registers MASK_H/MASK_L, the events are set with which the event interrupt is set.
• Several events can be masked to trigger an event interrupt.

• 0 = DSL Slave events that are masked in the SUMMARY register do not set the event interrupt.
• 1 = DSL Slave events that are masked in the SUMMARY register set the event interrupt.

• 0 = An error in the fast position does not set the event interrupt.
• 1 = An error in the fast position sets the event interrupt.

• 0 = A high deviation threshold error value does not set the event interrupt.
• 1 = A high estimator deviation threshold error sets the event interrupt.
  NOTE : Not available in TI HDSL Solution.

• 0 = A protocol reset does not set the event interrupt.
• 1 = A protocol reset sets the event interrupt.

• In the event mask registers MASK_H/MASK_L, the events are set with which the event interrupt is set.
• Several events can be masked to trigger an event interrupt.

• 0 = The acknowledgment for the initialization of a DSL Slave message does not set the event interrupt.
• 1 = The acknowledgment for the initialization of a DSL Slave message sets the event interrupt.

• 0 = A transmission error during the answer to a long message does not set the event interrupt.
• 1 = A transmission error during the answer to a long message sets the event interrupt.

• 0 = A low quality monitoring value does not set the event interrupt.
• 1 = A low quality monitoring value (see registers MASTER_QM and EVENT_L) sets the event interrupt.

• In this register, the DSL Slave collective events are determined with which the SUM event monitoring in the event register as well as the signal to the interrupt pin are set (interrupt).

• 0 = In the set status, the corresponding status summary bit does not set the SUM event monitoring and the signal at the interrupt pin.
• 1 = In the set status, the corresponding status summary bit sets the SUM event monitoring and the signal at the interrupt pin.

• This register contains the time control for the DSL cable bit sampling and can be used to monitor the connection quality.
• Each individual edge register bit is set if, at system start-up, an edge of the test signal is detected during the time period of the corresponding bit. An edge is defined as a change in cable value between successive detections.
• The sampling is carried out eight times as fast as the cable bit rate.
• Clean cable signals mean that only a few bits are set in the edge register, whilst noisy cable signals set a large number of bits.
  NOTE : Not available in TI HDSL Solution in this release

• 0 = No edge was detected in the time period of the corresponding bit.
• 1 = An edge was detected in the time period of the corresponding bit.

• 4 bit value for cable delay, which gives the cable signal round trip delay of cable and transceivers in bits.
• This value enables a rough estimate of cable length to be made.
• The value for Line Delay does not change after the start-up phase. A fresh value for Line Delay is only measured after a forced reset of the protocol.

  Cable Delay	DSL Connection Cable Delay (ns)	DSL Connection Cable Length (m)
  0	< 100	< 10
  1	100-200	10-20
  2	200-300	20-30
  3	300-400	30-40
  4	400-500	40-50
  5	500-600	50-60
  6	600-700	60-70
  7	700-800	70-80
  8	800-900	80-90
  9	900-1000	90-100

• 4 bit value for the cable signal strength, from "0" to "12".
• Higher values indicate better connection quality.
• RSSI is continuously updated during operation and used for signal monitoring during run time.

• 1 = ENC_ID is longer than 20 bits (for future use).

• 0 = Position value is signed.
• 1 = Position value is not signed.

Fast Position (Byte 4)

• The POS registers for the fast position contain the value of the motor feedback system connected.
• This position is generated incrementally from the safe position at start-up and is updated with every protocol frame.
• After every eight protocol frames, the fast position is checked against the safe position (see registers 0x18 to 0x1C).
• The position sampling point is determined by the ES value of the synchronization control register.
• Only those POS bits are activated that lie within the range that the motor feedback system has actually measured. All other higher value bits are read as "0".
  • The number of measurable bits can be taken from ENC_ID bits 9 to 0 in the ENC_ID0 and ENC_ID1 registers.
  • If Sign is set in the ENC_ID1 register, the value of the fast position is given signed in the two's complement.
  • The units of the position value are (steps).

NOTE : The fast position must not be used for safety functions.

Speed (Byte 2)

• The VEL speed registers contain the speed values of the connected motor feedback system.
• This value is calculated as a delta position from the acceleration value (delta-delta position) transmitted on the process data channel and the currently updated protocol frame.
• The speed sampling point is determined by the ES value of the SYNC_CTRL register.
• The units of the speed value are (steps/frame cycle time).

NOTE : The speed value must not be used for safety functions.

• The VPOS registers for the safe position contain the position value from the primary channel of the motor feedback system connected.
• This safe position is transmitted in every eighth protocol frame.
• Only those VPOS bits are activated that lie within the range that the motor feedback system has actually measured. All other higher value bits are read as "0".
  • The number of measurable bits can be taken from ENC_ID bits 9 to 0 in the ENC_ID0 and ENC_ID1 registers.
  • If Sign is set in the ENC_ID1 register, the value of the fast position is given signed in the two's complement.
  • The units of the position value are (steps).
• The safe position will have the same data format as the fast position.

• The VPOSCRC registers for the position checksum contain the CRC checksum of the safe position VPOS and the SUMMARY status.
• The CRC is checked in the DSL Master IP Core.
• In order to guarantee, in a safety related application, that the CRC machine in the IP Core is functioning, these registers can be checked with an external cross check in the diagnostics test interval.
• The CRC is generated with the following CRC parameters:
  • CRC Sequence : 16 Bit
  • CRC Polynomial : 0xC86C (x¹⁶ + x¹⁵ + x¹² + x⁷ + x⁶ + x⁴ + x³ + 1), Normal representation: 0x90D9
  • Starting Value : 0x0000
  • Closing XOR Value : 0x00FF
  • Reverse Data Bytes : No
  • Reverse CRC before closing XOR : No
  • Sequence of the bytes for calculation : SAFE_SUM, VPOS4, VPOS3, VPOS2, VPOS1, VPOS0

• The eight PC_BUFFER registers of the Parameters Channel buffer contain the answer to the last "long message" request or the data for a "long message" write operation.
• Depending on the length of the "long message" answer, the registers are used as follows:

  Length of the "long message"	Registers used
  8 bytes	0x20 to 0x27
  4 bytes	0x20 to 0x23
  2 bytes	0x20 to 0x21
  0 bytes	None

• These registers are also for the reporting of error conditions arising from a "long message" operation. If, when accessing a resource, an error due to a "long message" arises (e.g. invalid data, error in the A/D conversion), after the answering message has been received the LOFF bit in the PC_ADD_H register (28h) is set. In this case the Parameters Channel buffer bytes 0 and 1 contain an error code.
• The meaning of the error code depends on the particular encoder.

• The addresses and the addressing mode for "long messages" sent over the Parameters Channel are determined in the PC_ADD_H/PC_ADD_L long message address registers.
• In addition, the long message address register 0x28 (PC_ADD_H) contains indications of errors arising from "long message" operations. For this sort of error, the Parameters Channel buffer contains the error code in bytes 0 and 1 associated with this status.

• 0 = "Long message" write operation
• 1 = "Long message" read operation

• Write Access
  • 0 = Addressing of "long messages" without offset. The offset value from the PC_OFF_H/PC_OFF_Lregisters is not used.
  • 1 = Offset addressing of "long messages". The offset value from the PC_OFF_H/PC_OFF_L registers is used in the resource of the selected database entry as a sub-address.
• Read Access
  • 0 = The last "long message" was correctly processed.
  • 1 = The last "long message" caused an error.

• 0 = Direct addressing of "long messages". The operation affects the database entry given in the current address.
• 1 = Indirect addressing of "long messages". During this operation, the stored address content in the given database entry is evaluated.

• 00 = No data bytes
• 01 = 2 data bytes
• 10 = 4 data bytes
• 11 = 8 data bytes

• The PC_OFF_H/PC_OFF_L address offset registers for long messages are used in "long message" operations, if LOFF is set in the register 0x28.
• In this case the LOFFADD value from these registers is used to communicate with the sub-address of a multiple byte encoder resource.

• This register for the Parameters Channel handles the start of "long message" transactions. After setting all "long message" registers (registers PC_BUFFER0 to 7, PC_ADD_H/PC_ADD_L and PC_OFF_H/L), the "long message" is transmitted to the DSL Slave by setting the LSTA bit.

• 0 = No effect.
• 1 = A "long message" transaction is started with the values currently stored in the "long message" registers.

• 0 = Normal protocol action.
• 1 = A forced reset of the protocol status will be initiated. If the bit is deleted, a restart of the connection is triggered.

• 0 = Normal Parameters Channel action.
• 1 = The Parameters Channel is reset. Current short and long messages are discarded.

• This register contains the summarized DSL Slave status information for the safety related application.
• It is based on the encoder status ENC_ST7:0.
• Each status summary bit contains the summarized information from 8 error, warning and event modes of the DSL Slave.

• 0 = The corresponding error, warning or event is not active.
• 1 = An error, a warning or an event associated with DSL Slave external resources was triggered.

• 0 = The DSL Slave protocol has not triggered an error, a warning or event.
• 1 = An error, a warning or an event associated with the DSL Slave protocol interface was triggered.

• This register for the Parameters Channel short message contains the results of “short message” transactions.
• “Short message” transactions are generated if operations are carried out with remote registers (DSL Slave).
• Generally, FRES (in the EVENT_S register) must be set after a transaction is started. Only then will S_PC_DATA contain valid information.

• This register gives the count of transmitted fast position values with consecutive transmission errors.
• Writing to this register does not set any threshold for setting an error signal.

• It contains the messaging bits for warning and error modes of the DSL system.
• All messaging bits are set by the DSL Master if a corresponding status is determined.
• An event bit that has been set is not reset by the DSL Master.
• The safety related application must delete bits that have been set.
• It should be noted that all event register bits are also transferred to Online Status 1. The event bits are not static there and contain the actual status of each individual event.
• The following bit description lists the effects of warning and error conditions as well as the reactions to errors that must be installed in the safety related application.

SSUM: Remote event monitoring

• 0 = All DSL Slave events are deleted.
• 1 = The DSL Slave has signaled an event.

When the bit is set, an error or a warning has been transmitted from the DSL Slave. The safety related application must check the SAFE_SUM register to obtain a detailed description.

SCE: Error on the Safe Channel

• 0 = Safe Channel data was correctly transmitted.
• 1 = Data consistency error on the Safe Channel.

This error usually indicates a transmission error on the DSL connection. If this error occurs frequently, the wiring of the DSL connection should be checked. If this error occurs continuously, there is probably an error in the motor feedback system. This error affects quality monitoring and produces the QMLW warning or a protocol reset.

VPOS: Safe position error

• 0 = The safe position is correct.
• 1 = Sensor error.

This error usually indicates an encoder sensor error. If this error occurs continuously, there is probably an error in the motor feedback system.

QMLW: Quality monitoring low value warning

• 0 = Quality monitoring value greater than or equal to “14”
• 1 = Quality monitoring value (see register 0x03) below “14”

This warning indicates that a transmission error occurred. If this error occurs frequently, the wiring of the DSL connection should be checked.

PRST: Protocol reset warning

• 0 = Normal protocol action.
• 1 = The forced protocol reset was triggered.

This error message indicates that the protocol connection to the DSL Slave has been re-initialized. This error message can be caused by a frequency inverter application request (PRST bit in SYS_CTRL), a safety related application request (PRST bit in SAFE_CTRL), or generated by the DSL Master itself. The DSL Master causes a protocol reset if too many transmission errors indicate a connection problem. A protocol reset causes a re-synchronization with the DSL Slave that can improve the connection quality.

MIN: Message init

• 0 = No acknowledgment for the initialization received.
• 1 = An acknowledgment was received from the Slave for the initialization of a message.

When this warning is displayed, the Parameters Channel is still in the initialization status and no “short message” or “long message” can be triggered.

FRES: Channel free for “short message”

• 0 = No “short message” can be sent.
• 1 = A “short message” can be sent on the Parameters Channel.

If the bit is set, the frequency inverter application can trigger a “short message”. Provided no answer has been received from the DSL Slave, this bit remains deleted. As the processing duration of a “short message” in the motor feedback system is not specified, a time limit condition is installed in the DSL Master. If the time limit is exceeded, attempts are made again automatically.

• In the safe event mask register, the events are set with which the safe event interrupt is set.
• Several events can be masked to trigger an safe event interrupt.

• 0 = DSL Slave events that are set in the SAFE_SUM register do not set the safe event interrupt.
• 1 = DSL Slave events that are set in the SAFE_SUM register set the safe event interrupt.

• 0 = A transmission error on the Safe Channel does not set the safe event interrupt.
• 1 = A transmission error on the Safe Channel sets the safe event interrupt.

• 0 = An error in the safe position does not set the safe event interrupt.
• 1 = An error in the safe position sets the safe event interrupt.

• 0 = A low quality monitoring value does not set the safe event interrupt.
• 1 = A low quality monitoring value (see registers 03h and 05h) sets the safe event interrupt.

• 0 = A protocol reset does not set the safe event interrupt.
• 1 = A protocol reset sets the safe event interrupt.

• 0 = The acknowledgment for the initialization of a DSL Slave message does not set the safe event interrupt.
• 1 = The acknowledgment for the initialization of a DSL Slave message sets the safe event interrupt.

• 0 = If a “short message” can be sent on the Parameters Channel, the safe event interrupt is not set.
• 1 = If a “short message” can be sent on the Parameters Channel, the safe event interrupt is set.

• 0 = "Short message" write operation
• 1 = "Short message" read operation

• This register contains the status information for Safe Channel 2 of the HDSL motor feedback system.
• A summary of the contents is also available in the SUM2 bit of Online Status 2.
  NOTE : Register address is different from SICK HDSL MASTER IP Core (TI implementation uses 0x46 instead of 0x18)

• 0 = The last safe position received in Safe Channel 2 is correct.
• 1 = The last safe position received in Safe Channel 2 is invalid. Suitable measures must be installed in the user application.

• The VPOS2 registers for the safe position contain the position value from the secondary channel of the motor feedback system connected.
• This safe position is transmitted in every eighth protocol frame if the validity of the data transfer has been checked.
• Only those VPOS2 bits are relevant that lie within the range that the motor feedback system has actually measured.
• Also, typically channel 2 has a lower resolution than channel 1.
• The units of the position value are (steps).
  NOTE : Register address is different from SICK HDSL MASTER IP Core (TI implementation uses 0x47 instead of 0x19)

• The VPOSCRC2 registers for the position checksum contain the CRC checksum of the safe position VPOS2 and STATUS2.
• The CRC is checked in the DSL Master IP Core.
• In order to guarantee, in a safety related application, that the CRC machine in the IP Core is functioning, these registers can be checked with an external cross check in the diagnostics test interval.
• The CRC is generated with the following CRC parameters:
  • CRC Sequence : 16 Bit
  • CRC Polynomial : 0xC86C (x¹⁶ + x¹⁵ + x¹² + x⁷ + x⁶ + x⁴ + x³ + 1), Normal representation: 0x90D9
  • Starting Value : 0x0000
  • Closing XOR Value : 0x00FF
  • Reverse Data Bytes : No
  • Reverse CRC before closing XOR : No
  • Sequence of the bytes for calculation : STATUS2, VPOS24, VPOS23, VPOS22, VPOS21, VPOS20
    NOTE : Register address is different from SICK HDSL MASTER IP Core (TI implementation uses 0x4C instead of 0x1E)

• 1: Reserved
• 2: Fast position was received or position newly updated by estimator
• 3: Safe position 1 and 2 were received

• The Online Status D is a non-storing copy of registers EVENT_H and EVENT_L. The static information in these event registers must be deleted by the user after the read process, by writing the value "0" to the corresponding bit in the register, whilst the Online Status D only shows the current status without storing previous indications.

• 0 = The last valid value from SAFE_SUM was zero.
• 1 = The last valid value from SAFE_SUM was not zero. The importance of this flag depends on the particular error source that leads to a set SAFE_SUM.
  NOTE : Different implementation from SICK HDSL MASTER IP Core
  SAFE_SUM is used instead of MIR_SUM.

• 0 = No fast position error.
• 1 = A source of an error in the fast position was identified or an alignment procedure is currently being carried out. It is probable that the last fast position is invalid.

• 0 = Current value of deviation smaller than the specified maximum.
• 1 = Current value of deviation greater than the specified maximum.
  NOTE : Not available in TI HDSL Solution.

• 0 = Normal protocol action
• 1 = The forced protocol reset was triggered

• 0 = Parameter Channel not functioning.
• 1 = The DSL encoder sends a figure by which the initialization of the Parameter Channel is acknowledged.

• 0 = No error detected in the last answer to a long message.
• 1 = The last answer to a long message was damaged.

• 0 = Current value of quality monitoring greater than or equal to 14.
• 1 = Current value of quality monitoring less than 14.

• 0 = The channel for the “long message” is in use.
• 1 = The channel for the “long message” is free.

• The Online Status D is a non-storing copy of registers EVENT_S. The static information in the event register must be deleted by the user after the read process, by writing the value "0" to the corresponding bit in the register, whilst the Online Status 1 only shows the current status without storing previous indications.
• All fault indications in Online Status 1 are potentially critical and safety-related. Suitable measures must be installed in the user application.

• 0 = The last valid value from SAFE_SUM was zero.
• 1 = The last valid value from SAFE_SUM was not zero. The importance of this flag depends on the particular error source that leads to a set SAFE_SUM.

• 0 = The last Safe Channel 1 CRC received was correct.
• 1 = The last Safe Channel 1 CRC received was wrong. It is expected that the last safe position 1 transmitted is invalid.

• 0 = The last safe position received was correct.
• 1 = An error in the safe position was identified. It is expected that the safe position transmitted from the encoder is invalid.

• 0 = Normal protocol action
• 1 = The forced protocol reset was triggered

• 0 = Parameter Channel not functioning.
• 1 = The DSL encoder sends a figure by which the initialization of the Parameter Channel is acknowledged.

• 0 = Current value of quality monitoring greater than or equal to 14.
• 1 = Current value of quality monitoring less than 14.

• 0 = The channel for the “short message” is in use.
• 1 = The channel for the “short message” is free.

• Online Status 2 provides information about Safe Channel 2 of the DSL encoder.
• The data always indicate the current status, with previous indications not being stored.
• All fault indications in Online Status 2 are potentially critical and safety-related. Suitable measures must be installed in the user application.

• 0 = Neither TEST2 nor ERR2 is set.
• 1 = One of the indications TEST2 or ERR2 is set. The error reaction to this flag depends on the meaning of the bit they are based on.

• 0 = The last data received in Channel 2 was correct.
• 1 = The last Safe Channel 2 CRC received was wrong. It is expected that the last safe position 2 transmitted is invalid. Suitable measures must be installed in the user application.

• 0 = The last safe position received in Channel 2 was correct.
• 1 = A source of an error in the safe position in Channel 2 was identified. It is probable that the safe position transmitted from Channel 2 is invalid. Suitable measures must be installed in the user application.

• 0 = Normal protocol action
• 1 = The forced protocol reset was triggered

• 0 = Current value of quality monitoring greater than or equal to 14.
• 1 = Current value of quality monitoring less than 14.