Notable exceptions in TI HDSL Solution when compared with SICK HDSL MASTER IP Core release version 1.07 are described below:
TI HDSL Solution's register map is register compatible with SICK HDSL MASTER IP Core release version 1.07, with few exceptions listed below:
Register(s) | Remarks |
---|---|
SYS_CTRL Bits 5:0 (FRST, LOOP, PRDY, SPPE, SPOL, OEN) | Not available in TI HDSL Solution |
EVENT_H Bit 7 (INT) | Not available in TI HDSL Solution |
EVENT_H Bit 1 (DTE) MASK_H Bit 1 (MDTE) ONLINE_STATUS_D_H Bit 1 (DTE) | Not available in TI HDSL Solution |
EDGES | Not available in TI HDSL Solution in this release This will be available in future releases. |
VERSION VERSION2 | Different implementation from SICK HDSL MASTER IP Core "Major Release Number" field is 4 bits wide instead of 2 bits. "Coding" field is not available. |
RELEASE | Not available in TI HDSL Solution |
MIR_SUM | Not available in TI HDSL Solution Please see SAFE_SUM (0x36) for getting summary information. |
PIPE_S | Not available in TI HDSL Solution |
PC_DATA | Not available in TI HDSL Solution Please see S_PC_DATA (0x37) for “short message” transactions. |
ACC_ERR_CNT | Different implementation from SICK HDSL MASTER IP Core
|
MAXACC MAXDEV | Not available in TI HDSL Solution |
ENC2_ID | Not available in TI HDSL Solution |
EVENT_S Bit 7 (SINT) | Not available in TI HDSL Solution |
POSTX ONLINE_STATUS_D_L Bits 7:6 (POSTX) ONLINE_STATUS_1_L Bits 7:6 (POSTX) ONLINE_STATUS_2_L Bits 7:6 (POSTX) | Different implementation from SICK HDSL MASTER IP Core POSTX bits are available in a separate register POSTX register (0x4F) instead of ONLINE_STATUS_D_L, ONLINE_STATUS_1_L and ONLINE_STATUS_2_L registers. |
ONLINE_STATUS_D_H Bit 7 (INT) ONLINE_STATUS_1_H Bit 7 (SINT) | Not available in TI HDSL Solution |
ONLINE_STATUS_D_H Bit 6 (SUM) | Different implementation from SICK HDSL MASTER IP Core SAFE_SUM is used instead of MIR_SUM. |
VERSION2 | Register address is different from SICK HDSL MASTER IP Core TI implementation uses 0x44 instead of 0x0B |
ENC2_ID | Register address is different from SICK HDSL MASTER IP Core TI implementation uses 0x45 instead of 0x0F |
STATUS2 | Register address is different from SICK HDSL MASTER IP Core TI implementation uses 0x46 instead of 0x18 |
VPOS24 | Register address is different from SICK HDSL MASTER IP Core TI implementation uses 0x47 instead of 0x19 |
VPOS23 | Register address is different from SICK HDSL MASTER IP Core TI implementation uses 0x48 instead of 0x1A |
VPOS22 | Register address is different from SICK HDSL MASTER IP Core TI implementation uses 0x49 instead of 0x1B |
VPOS21 | Register address is different from SICK HDSL MASTER IP Core TI implementation uses 0x4A instead of 0x1C |
VPOS20 | Register address is different from SICK HDSL MASTER IP Core TI implementation uses 0x4B instead of 0x1D |
VPOSCRC2_H | Register address is different from SICK HDSL MASTER IP Core TI implementation uses 0x4C instead of 0x1E |
VPOSCRC2_L | Register address is different from SICK HDSL MASTER IP Core TI implementation uses 0x4D instead of 0x1F |