Introduction

This example generates a signal for a specified period and duty cycle using PRU-ICSS PWM. The period and duty cycle can be configured by the user.

The example Uses PRU-ICSSG0 PWM module and does below

Configures PWM0_0_POS(alias signal PWM0_A0) to generate a 1KHz signal with 25% duty cycle
Configures PWM3_2_NEG(alias signal PWM3_B2) to generate a 1KHz signal with 25% duty cycle
PWM0_0_POS(alias signal PWM0_A0) uses IEP0 CMP1 EVENT to control Duty cycle and IEP0 CMP0 to control output Frequency
PWM3_2_NEG(alias signal PWM3_B2) uses IEP1 CMP12 EVENT to control Duty cycle and IEP0 CMP0 to control output Frequency
Configures IEP0 CMP0 value with PWM0_0_POS(alias signal PWM0_A0) and PWM3_2_NEG(alias signal PWM3_B2) output period value
Configures IEP counter reset on CMP0 event
Configures IEP0 CMP6 value with PWM0_0_POS(alias signal PWM0_A0) output duty cycle value
Configures IEP1 CMP12 value with PWM3_2_NEG(alias signal PWM3_B2) output duty cycle value
PWM0_0_POS(alias signal PWM0_A0) and PWM3_2_NEG(alias signal PWM3_B2) will be in sync with respect to each other as IEP0 CMP0 value is used to control output period of these signals

An IO Breakout Board (BB) is required to probe the PWM outputs

PRU-ICSS PWM DUTY CYCLE PROBE OUTPUT

Supported Combinations

Parameter	Value
CPU + OS	r5fss0-0 freertos
Toolchain	ti-arm-clang
Boards	am243x-evm, am243x-lp
Example folder	examples/pruicss_pwm/pruicss_pwm_dutycycle

When using CCS projects to build, import the CCS project for the required combination and build it using the CCS project menu (see Using SDK with CCS Projects ).
When using makefiles to build, note the required combination and build using make command (see Using SDK with Makefiles )
Launch a CCS debug session and run the executable, see CCS Launch, Load and Run
To probe the PRUICSS PWM output please refer setup details as mentioned above in Introduction section