ICSS SDFM three channel with phase compensation

This example measures phase compensation for SDFM channel 0 in PRU GPIO mode during initialization. Normal current Over-samping Ratio (OSR), Over current OSR and Normal current trigger time can be configured by the user

Only one core - PRU is used for this example.

The example does the below:

Configure ICSSG1 IEP0 for generating clock for SDFM
Enable Phase Compensation Measurement
Configure SYNC1 Delay register based on the easured phase delay
Set SDFM channels: Channel 0 - Channel 2
Configure normal current sample trigger time (time for read sample) and OSR

Important files and directory structure

Folder/Files	Description
${SDK_INSTALL_PATH}/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation	Application specific sources for ICSS SDFM with phase compensation
${SDK_INSTALL_PATH}/examples/current_sense	Common source for ICSS SDFM applications
${SDK_INSTALL_PATH}/source/current_sense/sdfm
firmware/	Folder containing ICSS SDFM firmware sources
driver/	ICSS SDFM driver source
include/	Folder containing ICSS SDFM structures and APIs declarations

Supported Combinations

Parameter	Value
CPU + OS	r5fss0-0 freertos
ICSSG	ICSSG0
PRU	PRU0
Toolchain	ti-arm-clang
Board	am243x-evm, am243x-lp
Examples folder	examples/current_sense

Steps to Run the Example

Hardware Prerequisites

Other than the basic EVM setup mentioned in EVM Setup , below additional hardware is required to run this demo

TMDS64DC01EVM IO Link/Breakout Board
AMC1035EVM
AM243x-EVM
Signal generator

Hardware Setup

Hardware Setup SDFM

SDFM: EVM and IO breakout board setup view

Hardware Prerequisities for LP

AMC1035EVM
AM243x-LP Board
Signal generator

LP Hardware Setup

LP Hardware setup

SDFM: LP setup view

Build, load and run

When using CCS projects to build, import the CCS project and build it using the CCS project menu (see Using SDK with CCS Projects ).
When using makefiles to build, note the required combination and build using make command (see Using SDK with Makefiles )
Launch a CCS debug session and run the executable, see CCS Launch, Load and Run

Test Case Description

Test Details	Steps	Pass/Fail Criteria
1. To check Phase Compensation	1. Run the example on supported board
	2. probe ch0 SD0_D pin and SD8_CLK pin
	3. Build and run example
	4. Take time stamp of any rising edge of SD0_D pin and upcoming active SD8_CLK edge
	5. Compare this time with measured delay(stored in DMEM at offset 0x18)	Both value should be same or have a maxumum variation of 1 PRU cycle

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